blob: fe6d82c7b4eb4a3f2aac900b15eef3296008b805 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbelle24ea552014-05-05 14:42:31 +01002/*
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Aaron <leafy.myeh@allwinnertech.com>
6 *
7 * MMC driver for allwinner sunxi platform.
Ian Campbelle24ea552014-05-05 14:42:31 +01008 */
9
10#include <common.h>
Simon Glassdd279182017-07-04 13:31:27 -060011#include <dm.h>
Hans de Goede90641f82015-04-22 17:03:17 +020012#include <errno.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010013#include <malloc.h>
14#include <mmc.h>
15#include <asm/io.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/cpu.h>
Hans de Goedecd821132014-10-02 20:29:26 +020018#include <asm/arch/gpio.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010019#include <asm/arch/mmc.h>
Hans de Goedecd821132014-10-02 20:29:26 +020020#include <asm-generic/gpio.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010021
Simon Glassdd279182017-07-04 13:31:27 -060022struct sunxi_mmc_plat {
23 struct mmc_config cfg;
24 struct mmc mmc;
25};
26
Simon Glasse3c794e2017-07-04 13:31:23 -060027struct sunxi_mmc_priv {
Ian Campbelle24ea552014-05-05 14:42:31 +010028 unsigned mmc_no;
29 uint32_t *mclkreg;
Ian Campbelle24ea552014-05-05 14:42:31 +010030 unsigned fatal_err;
Simon Glassdd279182017-07-04 13:31:27 -060031 struct gpio_desc cd_gpio; /* Change Detect GPIO */
Heinrich Schuchardt8be4e612018-02-01 23:39:19 +010032 int cd_inverted; /* Inverted Card Detect */
Ian Campbelle24ea552014-05-05 14:42:31 +010033 struct sunxi_mmc *reg;
34 struct mmc_config cfg;
35};
36
Simon Glassdd279182017-07-04 13:31:27 -060037#if !CONFIG_IS_ENABLED(DM_MMC)
Ian Campbelle24ea552014-05-05 14:42:31 +010038/* support 4 mmc hosts */
Simon Glasse3c794e2017-07-04 13:31:23 -060039struct sunxi_mmc_priv mmc_host[4];
Ian Campbelle24ea552014-05-05 14:42:31 +010040
Hans de Goede967325f2014-10-31 16:55:02 +010041static int sunxi_mmc_getcd_gpio(int sdc_no)
42{
43 switch (sdc_no) {
44 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
45 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
46 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
47 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
48 }
Hans de Goede90641f82015-04-22 17:03:17 +020049 return -EINVAL;
Hans de Goede967325f2014-10-31 16:55:02 +010050}
51
Ian Campbelle24ea552014-05-05 14:42:31 +010052static int mmc_resource_init(int sdc_no)
53{
Simon Glass3f5af122017-07-04 13:31:24 -060054 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
Ian Campbelle24ea552014-05-05 14:42:31 +010055 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Hans de Goede967325f2014-10-31 16:55:02 +010056 int cd_pin, ret = 0;
Ian Campbelle24ea552014-05-05 14:42:31 +010057
58 debug("init mmc %d resource\n", sdc_no);
59
60 switch (sdc_no) {
61 case 0:
Simon Glass3f5af122017-07-04 13:31:24 -060062 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
63 priv->mclkreg = &ccm->sd0_clk_cfg;
Ian Campbelle24ea552014-05-05 14:42:31 +010064 break;
65 case 1:
Simon Glass3f5af122017-07-04 13:31:24 -060066 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
67 priv->mclkreg = &ccm->sd1_clk_cfg;
Ian Campbelle24ea552014-05-05 14:42:31 +010068 break;
69 case 2:
Simon Glass3f5af122017-07-04 13:31:24 -060070 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
71 priv->mclkreg = &ccm->sd2_clk_cfg;
Ian Campbelle24ea552014-05-05 14:42:31 +010072 break;
73 case 3:
Simon Glass3f5af122017-07-04 13:31:24 -060074 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
75 priv->mclkreg = &ccm->sd3_clk_cfg;
Ian Campbelle24ea552014-05-05 14:42:31 +010076 break;
77 default:
78 printf("Wrong mmc number %d\n", sdc_no);
79 return -1;
80 }
Simon Glass3f5af122017-07-04 13:31:24 -060081 priv->mmc_no = sdc_no;
Ian Campbelle24ea552014-05-05 14:42:31 +010082
Hans de Goede967325f2014-10-31 16:55:02 +010083 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
Hans de Goede90641f82015-04-22 17:03:17 +020084 if (cd_pin >= 0) {
Hans de Goede967325f2014-10-31 16:55:02 +010085 ret = gpio_request(cd_pin, "mmc_cd");
Hans de Goede1c09fa32015-05-30 16:39:10 +020086 if (!ret) {
87 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
Axel Linb0c4ae12014-12-20 11:41:25 +080088 ret = gpio_direction_input(cd_pin);
Hans de Goede1c09fa32015-05-30 16:39:10 +020089 }
Axel Linb0c4ae12014-12-20 11:41:25 +080090 }
Hans de Goede967325f2014-10-31 16:55:02 +010091
92 return ret;
Ian Campbelle24ea552014-05-05 14:42:31 +010093}
Simon Glassdd279182017-07-04 13:31:27 -060094#endif
Ian Campbelle24ea552014-05-05 14:42:31 +010095
Simon Glass3f5af122017-07-04 13:31:24 -060096static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
Hans de Goedefc3a8322014-12-07 20:55:10 +010097{
98 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
Maxime Ripardde9b1772017-08-23 12:03:41 +020099 bool new_mode = false;
100 u32 val = 0;
101
102 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
103 new_mode = true;
104
105 /*
106 * The MMC clock has an extra /2 post-divider when operating in the new
107 * mode.
108 */
109 if (new_mode)
110 hz = hz * 2;
Hans de Goedefc3a8322014-12-07 20:55:10 +0100111
112 if (hz <= 24000000) {
113 pll = CCM_MMC_CTRL_OSCM24;
114 pll_hz = 24000000;
115 } else {
Hans de Goededaf22632015-01-14 19:05:03 +0100116#ifdef CONFIG_MACH_SUN9I
117 pll = CCM_MMC_CTRL_PLL_PERIPH0;
118 pll_hz = clock_get_pll4_periph0();
119#else
Hans de Goedefc3a8322014-12-07 20:55:10 +0100120 pll = CCM_MMC_CTRL_PLL6;
121 pll_hz = clock_get_pll6();
Hans de Goededaf22632015-01-14 19:05:03 +0100122#endif
Hans de Goedefc3a8322014-12-07 20:55:10 +0100123 }
124
125 div = pll_hz / hz;
126 if (pll_hz % hz)
127 div++;
128
129 n = 0;
130 while (div > 16) {
131 n++;
132 div = (div + 1) / 2;
133 }
134
135 if (n > 3) {
Simon Glass3f5af122017-07-04 13:31:24 -0600136 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
137 hz);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100138 return -1;
139 }
140
141 /* determine delays */
142 if (hz <= 400000) {
143 oclk_dly = 0;
Hans de Goedebe909742015-09-23 16:13:10 +0200144 sclk_dly = 0;
Hans de Goedefc3a8322014-12-07 20:55:10 +0100145 } else if (hz <= 25000000) {
146 oclk_dly = 0;
147 sclk_dly = 5;
Hans de Goedebe909742015-09-23 16:13:10 +0200148#ifdef CONFIG_MACH_SUN9I
Stefan Mavrodiev4744d812018-03-27 16:57:23 +0300149 } else if (hz <= 52000000) {
Hans de Goedebe909742015-09-23 16:13:10 +0200150 oclk_dly = 5;
151 sclk_dly = 4;
Hans de Goedefc3a8322014-12-07 20:55:10 +0100152 } else {
Stefan Mavrodiev4744d812018-03-27 16:57:23 +0300153 /* hz > 52000000 */
Hans de Goedefc3a8322014-12-07 20:55:10 +0100154 oclk_dly = 2;
155 sclk_dly = 4;
Hans de Goedebe909742015-09-23 16:13:10 +0200156#else
Stefan Mavrodiev4744d812018-03-27 16:57:23 +0300157 } else if (hz <= 52000000) {
Hans de Goedebe909742015-09-23 16:13:10 +0200158 oclk_dly = 3;
159 sclk_dly = 4;
160 } else {
Stefan Mavrodiev4744d812018-03-27 16:57:23 +0300161 /* hz > 52000000 */
Hans de Goedebe909742015-09-23 16:13:10 +0200162 oclk_dly = 1;
163 sclk_dly = 4;
164#endif
Hans de Goedefc3a8322014-12-07 20:55:10 +0100165 }
166
Maxime Ripardde9b1772017-08-23 12:03:41 +0200167 if (new_mode) {
168#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
169 val = CCM_MMC_CTRL_MODE_SEL_NEW;
Chen-Yu Tsai8a647fc2017-08-31 21:57:48 +0800170 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
Maxime Ripardde9b1772017-08-23 12:03:41 +0200171#endif
172 } else {
173 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
174 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
175 }
176
177 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
178 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100179
180 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
Simon Glass3f5af122017-07-04 13:31:24 -0600181 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100182
183 return 0;
184}
185
Simon Glass034e2262017-07-04 13:31:25 -0600186static int mmc_update_clk(struct sunxi_mmc_priv *priv)
Ian Campbelle24ea552014-05-05 14:42:31 +0100187{
Ian Campbelle24ea552014-05-05 14:42:31 +0100188 unsigned int cmd;
189 unsigned timeout_msecs = 2000;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100190 unsigned long start = get_timer(0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100191
192 cmd = SUNXI_MMC_CMD_START |
193 SUNXI_MMC_CMD_UPCLK_ONLY |
194 SUNXI_MMC_CMD_WAIT_PRE_OVER;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100195
Simon Glass3f5af122017-07-04 13:31:24 -0600196 writel(cmd, &priv->reg->cmd);
197 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100198 if (get_timer(start) > timeout_msecs)
Ian Campbelle24ea552014-05-05 14:42:31 +0100199 return -1;
Ian Campbelle24ea552014-05-05 14:42:31 +0100200 }
201
202 /* clock update sets various irq status bits, clear these */
Simon Glass3f5af122017-07-04 13:31:24 -0600203 writel(readl(&priv->reg->rint), &priv->reg->rint);
Ian Campbelle24ea552014-05-05 14:42:31 +0100204
205 return 0;
206}
207
Simon Glass034e2262017-07-04 13:31:25 -0600208static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
Ian Campbelle24ea552014-05-05 14:42:31 +0100209{
Simon Glass3f5af122017-07-04 13:31:24 -0600210 unsigned rval = readl(&priv->reg->clkcr);
Ian Campbelle24ea552014-05-05 14:42:31 +0100211
212 /* Disable Clock */
213 rval &= ~SUNXI_MMC_CLK_ENABLE;
Simon Glass3f5af122017-07-04 13:31:24 -0600214 writel(rval, &priv->reg->clkcr);
Simon Glass034e2262017-07-04 13:31:25 -0600215 if (mmc_update_clk(priv))
Ian Campbelle24ea552014-05-05 14:42:31 +0100216 return -1;
217
Hans de Goedefc3a8322014-12-07 20:55:10 +0100218 /* Set mod_clk to new rate */
Simon Glass3f5af122017-07-04 13:31:24 -0600219 if (mmc_set_mod_clk(priv, mmc->clock))
Ian Campbelle24ea552014-05-05 14:42:31 +0100220 return -1;
Hans de Goedefc3a8322014-12-07 20:55:10 +0100221
222 /* Clear internal divider */
223 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
Simon Glass3f5af122017-07-04 13:31:24 -0600224 writel(rval, &priv->reg->clkcr);
Hans de Goedefc3a8322014-12-07 20:55:10 +0100225
Ian Campbelle24ea552014-05-05 14:42:31 +0100226 /* Re-enable Clock */
227 rval |= SUNXI_MMC_CLK_ENABLE;
Simon Glass3f5af122017-07-04 13:31:24 -0600228 writel(rval, &priv->reg->clkcr);
Simon Glass034e2262017-07-04 13:31:25 -0600229 if (mmc_update_clk(priv))
Ian Campbelle24ea552014-05-05 14:42:31 +0100230 return -1;
231
232 return 0;
233}
234
Simon Glass034e2262017-07-04 13:31:25 -0600235static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
236 struct mmc *mmc)
Ian Campbelle24ea552014-05-05 14:42:31 +0100237{
Hans de Goedefc3a8322014-12-07 20:55:10 +0100238 debug("set ios: bus_width: %x, clock: %d\n",
239 mmc->bus_width, mmc->clock);
Ian Campbelle24ea552014-05-05 14:42:31 +0100240
241 /* Change clock first */
Simon Glass034e2262017-07-04 13:31:25 -0600242 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
Simon Glass3f5af122017-07-04 13:31:24 -0600243 priv->fatal_err = 1;
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900244 return -EINVAL;
Ian Campbelle24ea552014-05-05 14:42:31 +0100245 }
246
247 /* Change bus width */
248 if (mmc->bus_width == 8)
Simon Glass3f5af122017-07-04 13:31:24 -0600249 writel(0x2, &priv->reg->width);
Ian Campbelle24ea552014-05-05 14:42:31 +0100250 else if (mmc->bus_width == 4)
Simon Glass3f5af122017-07-04 13:31:24 -0600251 writel(0x1, &priv->reg->width);
Ian Campbelle24ea552014-05-05 14:42:31 +0100252 else
Simon Glass3f5af122017-07-04 13:31:24 -0600253 writel(0x0, &priv->reg->width);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900254
255 return 0;
Ian Campbelle24ea552014-05-05 14:42:31 +0100256}
257
Simon Glassdd279182017-07-04 13:31:27 -0600258#if !CONFIG_IS_ENABLED(DM_MMC)
Siarhei Siamashka5abdb152015-02-01 00:42:14 +0200259static int sunxi_mmc_core_init(struct mmc *mmc)
Ian Campbelle24ea552014-05-05 14:42:31 +0100260{
Simon Glass3f5af122017-07-04 13:31:24 -0600261 struct sunxi_mmc_priv *priv = mmc->priv;
Ian Campbelle24ea552014-05-05 14:42:31 +0100262
263 /* Reset controller */
Simon Glass3f5af122017-07-04 13:31:24 -0600264 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
Hans de Goedeb6ae6762014-06-09 11:36:55 +0200265 udelay(1000);
Ian Campbelle24ea552014-05-05 14:42:31 +0100266
267 return 0;
268}
Simon Glassdd279182017-07-04 13:31:27 -0600269#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100270
Simon Glass034e2262017-07-04 13:31:25 -0600271static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
272 struct mmc_data *data)
Ian Campbelle24ea552014-05-05 14:42:31 +0100273{
Ian Campbelle24ea552014-05-05 14:42:31 +0100274 const int reading = !!(data->flags & MMC_DATA_READ);
275 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
276 SUNXI_MMC_STATUS_FIFO_FULL;
277 unsigned i;
Ian Campbelle24ea552014-05-05 14:42:31 +0100278 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
Yousong Zhou28f69b92015-08-29 21:26:11 +0800279 unsigned byte_cnt = data->blocksize * data->blocks;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100280 unsigned timeout_msecs = byte_cnt >> 8;
281 unsigned long start;
282
283 if (timeout_msecs < 2000)
284 timeout_msecs = 2000;
Ian Campbelle24ea552014-05-05 14:42:31 +0100285
Hans de Goedeb6ae6762014-06-09 11:36:55 +0200286 /* Always read / write data through the CPU */
Simon Glass3f5af122017-07-04 13:31:24 -0600287 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
Hans de Goedeb6ae6762014-06-09 11:36:55 +0200288
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100289 start = get_timer(0);
290
Ian Campbelle24ea552014-05-05 14:42:31 +0100291 for (i = 0; i < (byte_cnt >> 2); i++) {
Simon Glass3f5af122017-07-04 13:31:24 -0600292 while (readl(&priv->reg->status) & status_bit) {
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100293 if (get_timer(start) > timeout_msecs)
Ian Campbelle24ea552014-05-05 14:42:31 +0100294 return -1;
Ian Campbelle24ea552014-05-05 14:42:31 +0100295 }
296
297 if (reading)
Simon Glass3f5af122017-07-04 13:31:24 -0600298 buff[i] = readl(&priv->reg->fifo);
Ian Campbelle24ea552014-05-05 14:42:31 +0100299 else
Simon Glass3f5af122017-07-04 13:31:24 -0600300 writel(buff[i], &priv->reg->fifo);
Ian Campbelle24ea552014-05-05 14:42:31 +0100301 }
302
303 return 0;
304}
305
Simon Glass034e2262017-07-04 13:31:25 -0600306static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
307 uint timeout_msecs, uint done_bit, const char *what)
Ian Campbelle24ea552014-05-05 14:42:31 +0100308{
Ian Campbelle24ea552014-05-05 14:42:31 +0100309 unsigned int status;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100310 unsigned long start = get_timer(0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100311
312 do {
Simon Glass3f5af122017-07-04 13:31:24 -0600313 status = readl(&priv->reg->rint);
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100314 if ((get_timer(start) > timeout_msecs) ||
Ian Campbelle24ea552014-05-05 14:42:31 +0100315 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
316 debug("%s timeout %x\n", what,
317 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900318 return -ETIMEDOUT;
Ian Campbelle24ea552014-05-05 14:42:31 +0100319 }
Ian Campbelle24ea552014-05-05 14:42:31 +0100320 } while (!(status & done_bit));
321
322 return 0;
323}
324
Simon Glass034e2262017-07-04 13:31:25 -0600325static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
326 struct mmc *mmc, struct mmc_cmd *cmd,
327 struct mmc_data *data)
Ian Campbelle24ea552014-05-05 14:42:31 +0100328{
Ian Campbelle24ea552014-05-05 14:42:31 +0100329 unsigned int cmdval = SUNXI_MMC_CMD_START;
330 unsigned int timeout_msecs;
331 int error = 0;
332 unsigned int status = 0;
Ian Campbelle24ea552014-05-05 14:42:31 +0100333 unsigned int bytecnt = 0;
334
Simon Glass3f5af122017-07-04 13:31:24 -0600335 if (priv->fatal_err)
Ian Campbelle24ea552014-05-05 14:42:31 +0100336 return -1;
337 if (cmd->resp_type & MMC_RSP_BUSY)
338 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
339 if (cmd->cmdidx == 12)
340 return 0;
341
342 if (!cmd->cmdidx)
343 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
344 if (cmd->resp_type & MMC_RSP_PRESENT)
345 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
346 if (cmd->resp_type & MMC_RSP_136)
347 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
348 if (cmd->resp_type & MMC_RSP_CRC)
349 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
350
351 if (data) {
Alexander Graf0ea5a042016-03-29 17:29:09 +0200352 if ((u32)(long)data->dest & 0x3) {
Ian Campbelle24ea552014-05-05 14:42:31 +0100353 error = -1;
354 goto out;
355 }
356
357 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
358 if (data->flags & MMC_DATA_WRITE)
359 cmdval |= SUNXI_MMC_CMD_WRITE;
360 if (data->blocks > 1)
361 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
Simon Glass3f5af122017-07-04 13:31:24 -0600362 writel(data->blocksize, &priv->reg->blksz);
363 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
Ian Campbelle24ea552014-05-05 14:42:31 +0100364 }
365
Simon Glass3f5af122017-07-04 13:31:24 -0600366 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
Ian Campbelle24ea552014-05-05 14:42:31 +0100367 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
Simon Glass3f5af122017-07-04 13:31:24 -0600368 writel(cmd->cmdarg, &priv->reg->arg);
Ian Campbelle24ea552014-05-05 14:42:31 +0100369
370 if (!data)
Simon Glass3f5af122017-07-04 13:31:24 -0600371 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
Ian Campbelle24ea552014-05-05 14:42:31 +0100372
373 /*
374 * transfer data and check status
375 * STATREG[2] : FIFO empty
376 * STATREG[3] : FIFO full
377 */
378 if (data) {
379 int ret = 0;
380
381 bytecnt = data->blocksize * data->blocks;
382 debug("trans data %d bytes\n", bytecnt);
Simon Glass3f5af122017-07-04 13:31:24 -0600383 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
Simon Glass034e2262017-07-04 13:31:25 -0600384 ret = mmc_trans_data_by_cpu(priv, mmc, data);
Ian Campbelle24ea552014-05-05 14:42:31 +0100385 if (ret) {
Simon Glass3f5af122017-07-04 13:31:24 -0600386 error = readl(&priv->reg->rint) &
Ian Campbelle24ea552014-05-05 14:42:31 +0100387 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900388 error = -ETIMEDOUT;
Ian Campbelle24ea552014-05-05 14:42:31 +0100389 goto out;
390 }
391 }
392
Simon Glass034e2262017-07-04 13:31:25 -0600393 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
394 "cmd");
Ian Campbelle24ea552014-05-05 14:42:31 +0100395 if (error)
396 goto out;
397
398 if (data) {
Hans de Goedeb6ae6762014-06-09 11:36:55 +0200399 timeout_msecs = 120;
Ian Campbelle24ea552014-05-05 14:42:31 +0100400 debug("cacl timeout %x msec\n", timeout_msecs);
Simon Glass034e2262017-07-04 13:31:25 -0600401 error = mmc_rint_wait(priv, mmc, timeout_msecs,
Ian Campbelle24ea552014-05-05 14:42:31 +0100402 data->blocks > 1 ?
403 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
404 SUNXI_MMC_RINT_DATA_OVER,
405 "data");
406 if (error)
407 goto out;
408 }
409
410 if (cmd->resp_type & MMC_RSP_BUSY) {
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100411 unsigned long start = get_timer(0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100412 timeout_msecs = 2000;
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100413
Ian Campbelle24ea552014-05-05 14:42:31 +0100414 do {
Simon Glass3f5af122017-07-04 13:31:24 -0600415 status = readl(&priv->reg->status);
Philipp Tomsich5ff8e542018-03-21 12:18:58 +0100416 if (get_timer(start) > timeout_msecs) {
Ian Campbelle24ea552014-05-05 14:42:31 +0100417 debug("busy timeout\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900418 error = -ETIMEDOUT;
Ian Campbelle24ea552014-05-05 14:42:31 +0100419 goto out;
420 }
Ian Campbelle24ea552014-05-05 14:42:31 +0100421 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
422 }
423
424 if (cmd->resp_type & MMC_RSP_136) {
Simon Glass3f5af122017-07-04 13:31:24 -0600425 cmd->response[0] = readl(&priv->reg->resp3);
426 cmd->response[1] = readl(&priv->reg->resp2);
427 cmd->response[2] = readl(&priv->reg->resp1);
428 cmd->response[3] = readl(&priv->reg->resp0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100429 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
430 cmd->response[3], cmd->response[2],
431 cmd->response[1], cmd->response[0]);
432 } else {
Simon Glass3f5af122017-07-04 13:31:24 -0600433 cmd->response[0] = readl(&priv->reg->resp0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100434 debug("mmc resp 0x%08x\n", cmd->response[0]);
435 }
436out:
Ian Campbelle24ea552014-05-05 14:42:31 +0100437 if (error < 0) {
Simon Glass3f5af122017-07-04 13:31:24 -0600438 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
Simon Glass034e2262017-07-04 13:31:25 -0600439 mmc_update_clk(priv);
Ian Campbelle24ea552014-05-05 14:42:31 +0100440 }
Simon Glass3f5af122017-07-04 13:31:24 -0600441 writel(0xffffffff, &priv->reg->rint);
442 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
443 &priv->reg->gctrl);
Ian Campbelle24ea552014-05-05 14:42:31 +0100444
445 return error;
446}
447
Simon Glassdd279182017-07-04 13:31:27 -0600448#if !CONFIG_IS_ENABLED(DM_MMC)
Simon Glass034e2262017-07-04 13:31:25 -0600449static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
450{
451 struct sunxi_mmc_priv *priv = mmc->priv;
452
453 return sunxi_mmc_set_ios_common(priv, mmc);
454}
455
456static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
457 struct mmc_data *data)
458{
459 struct sunxi_mmc_priv *priv = mmc->priv;
460
461 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
462}
463
464static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
Hans de Goedecd821132014-10-02 20:29:26 +0200465{
Simon Glass3f5af122017-07-04 13:31:24 -0600466 struct sunxi_mmc_priv *priv = mmc->priv;
Hans de Goede967325f2014-10-31 16:55:02 +0100467 int cd_pin;
Hans de Goedecd821132014-10-02 20:29:26 +0200468
Simon Glass3f5af122017-07-04 13:31:24 -0600469 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
Hans de Goede90641f82015-04-22 17:03:17 +0200470 if (cd_pin < 0)
Hans de Goedecd821132014-10-02 20:29:26 +0200471 return 1;
472
Axel Linb0c4ae12014-12-20 11:41:25 +0800473 return !gpio_get_value(cd_pin);
Hans de Goedecd821132014-10-02 20:29:26 +0200474}
475
Ian Campbelle24ea552014-05-05 14:42:31 +0100476static const struct mmc_ops sunxi_mmc_ops = {
Simon Glass034e2262017-07-04 13:31:25 -0600477 .send_cmd = sunxi_mmc_send_cmd_legacy,
478 .set_ios = sunxi_mmc_set_ios_legacy,
Siarhei Siamashka5abdb152015-02-01 00:42:14 +0200479 .init = sunxi_mmc_core_init,
Simon Glass034e2262017-07-04 13:31:25 -0600480 .getcd = sunxi_mmc_getcd_legacy,
Ian Campbelle24ea552014-05-05 14:42:31 +0100481};
482
Hans de Goedee79c7c82014-10-02 21:13:54 +0200483struct mmc *sunxi_mmc_init(int sdc_no)
Ian Campbelle24ea552014-05-05 14:42:31 +0100484{
Simon Glassec73d962017-07-04 13:31:26 -0600485 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Simon Glass034e2262017-07-04 13:31:25 -0600486 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
487 struct mmc_config *cfg = &priv->cfg;
Simon Glassec73d962017-07-04 13:31:26 -0600488 int ret;
Ian Campbelle24ea552014-05-05 14:42:31 +0100489
Simon Glass034e2262017-07-04 13:31:25 -0600490 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
Ian Campbelle24ea552014-05-05 14:42:31 +0100491
492 cfg->name = "SUNXI SD/MMC";
493 cfg->ops = &sunxi_mmc_ops;
494
495 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
496 cfg->host_caps = MMC_MODE_4BIT;
Maxime Ripardfb013182016-11-04 16:18:09 +0100497#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200498 if (sdc_no == 2)
499 cfg->host_caps = MMC_MODE_8BIT;
500#endif
Rob Herring5a203972015-03-23 17:56:59 -0500501 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Ian Campbelle24ea552014-05-05 14:42:31 +0100502 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
503
504 cfg->f_min = 400000;
505 cfg->f_max = 52000000;
506
Hans de Goede967325f2014-10-31 16:55:02 +0100507 if (mmc_resource_init(sdc_no) != 0)
508 return NULL;
509
Simon Glassec73d962017-07-04 13:31:26 -0600510 /* config ahb clock */
511 debug("init mmc %d clock and io\n", sdc_no);
512 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
513
514#ifdef CONFIG_SUNXI_GEN_SUN6I
515 /* unassert reset */
516 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
517#endif
518#if defined(CONFIG_MACH_SUN9I)
519 /* sun9i has a mmc-common module, also set the gate and reset there */
520 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
521 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
522#endif
523 ret = mmc_set_mod_clk(priv, 24000000);
524 if (ret)
525 return NULL;
Ian Campbelle24ea552014-05-05 14:42:31 +0100526
Maxime Ripardead36972017-08-23 13:41:33 +0200527 return mmc_create(cfg, priv);
Ian Campbelle24ea552014-05-05 14:42:31 +0100528}
Simon Glassdd279182017-07-04 13:31:27 -0600529#else
530
531static int sunxi_mmc_set_ios(struct udevice *dev)
532{
533 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
534 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
535
536 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
537}
538
539static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
540 struct mmc_data *data)
541{
542 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
543 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
544
545 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
546}
547
548static int sunxi_mmc_getcd(struct udevice *dev)
549{
550 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
551
Heinrich Schuchardt8be4e612018-02-01 23:39:19 +0100552 if (dm_gpio_is_valid(&priv->cd_gpio)) {
553 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
Simon Glassdd279182017-07-04 13:31:27 -0600554
Heinrich Schuchardt8be4e612018-02-01 23:39:19 +0100555 return cd_state ^ priv->cd_inverted;
556 }
Simon Glassdd279182017-07-04 13:31:27 -0600557 return 1;
558}
559
560static const struct dm_mmc_ops sunxi_mmc_ops = {
561 .send_cmd = sunxi_mmc_send_cmd,
562 .set_ios = sunxi_mmc_set_ios,
563 .get_cd = sunxi_mmc_getcd,
564};
565
566static int sunxi_mmc_probe(struct udevice *dev)
567{
568 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
569 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
570 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
571 struct mmc_config *cfg = &plat->cfg;
572 struct ofnode_phandle_args args;
573 u32 *gate_reg;
574 int bus_width, ret;
575
576 cfg->name = dev->name;
577 bus_width = dev_read_u32_default(dev, "bus-width", 1);
578
579 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
580 cfg->host_caps = 0;
581 if (bus_width == 8)
582 cfg->host_caps |= MMC_MODE_8BIT;
583 if (bus_width >= 4)
584 cfg->host_caps |= MMC_MODE_4BIT;
585 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
586 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
587
588 cfg->f_min = 400000;
589 cfg->f_max = 52000000;
590
591 priv->reg = (void *)dev_read_addr(dev);
592
593 /* We don't have a sunxi clock driver so find the clock address here */
594 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
595 1, &args);
596 if (ret)
597 return ret;
598 priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
599
600 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
601 0, &args);
602 if (ret)
603 return ret;
604 gate_reg = (u32 *)ofnode_get_addr(args.node);
605 setbits_le32(gate_reg, 1 << args.args[0]);
606 priv->mmc_no = args.args[0] - 8;
607
608 ret = mmc_set_mod_clk(priv, 24000000);
609 if (ret)
610 return ret;
611
612 /* This GPIO is optional */
613 if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
614 GPIOD_IS_IN)) {
615 int cd_pin = gpio_get_number(&priv->cd_gpio);
616
617 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
618 }
619
Heinrich Schuchardt8be4e612018-02-01 23:39:19 +0100620 /* Check if card detect is inverted */
621 priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
622
Simon Glassdd279182017-07-04 13:31:27 -0600623 upriv->mmc = &plat->mmc;
624
625 /* Reset controller */
626 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
627 udelay(1000);
628
629 return 0;
630}
631
632static int sunxi_mmc_bind(struct udevice *dev)
633{
634 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
635
636 return mmc_bind(dev, &plat->mmc, &plat->cfg);
637}
638
639static const struct udevice_id sunxi_mmc_ids[] = {
640 { .compatible = "allwinner,sun5i-a13-mmc" },
641 { }
642};
643
644U_BOOT_DRIVER(sunxi_mmc_drv) = {
645 .name = "sunxi_mmc",
646 .id = UCLASS_MMC,
647 .of_match = sunxi_mmc_ids,
648 .bind = sunxi_mmc_bind,
649 .probe = sunxi_mmc_probe,
650 .ops = &sunxi_mmc_ops,
651 .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
652 .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
653};
654#endif