Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007-2011 |
| 3 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 4 | * Aaron <leafy.myeh@allwinnertech.com> |
| 5 | * |
| 6 | * MMC driver for allwinner sunxi platform. |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Hans de Goede | 90641f8 | 2015-04-22 17:03:17 +0200 | [diff] [blame] | 12 | #include <errno.h> |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 13 | #include <malloc.h> |
| 14 | #include <mmc.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/arch/clock.h> |
| 17 | #include <asm/arch/cpu.h> |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 18 | #include <asm/arch/gpio.h> |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 19 | #include <asm/arch/mmc.h> |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 20 | #include <asm-generic/gpio.h> |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 21 | |
Simon Glass | e3c794e | 2017-07-04 13:31:23 -0600 | [diff] [blame] | 22 | struct sunxi_mmc_priv { |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 23 | unsigned mmc_no; |
| 24 | uint32_t *mclkreg; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 25 | unsigned fatal_err; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 26 | struct sunxi_mmc *reg; |
| 27 | struct mmc_config cfg; |
| 28 | }; |
| 29 | |
| 30 | /* support 4 mmc hosts */ |
Simon Glass | e3c794e | 2017-07-04 13:31:23 -0600 | [diff] [blame] | 31 | struct sunxi_mmc_priv mmc_host[4]; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 32 | |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 33 | static int sunxi_mmc_getcd_gpio(int sdc_no) |
| 34 | { |
| 35 | switch (sdc_no) { |
| 36 | case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); |
| 37 | case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); |
| 38 | case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); |
| 39 | case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); |
| 40 | } |
Hans de Goede | 90641f8 | 2015-04-22 17:03:17 +0200 | [diff] [blame] | 41 | return -EINVAL; |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 42 | } |
| 43 | |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 44 | static int mmc_resource_init(int sdc_no) |
| 45 | { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 46 | struct sunxi_mmc_priv *priv = &mmc_host[sdc_no]; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 47 | struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 48 | int cd_pin, ret = 0; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 49 | |
| 50 | debug("init mmc %d resource\n", sdc_no); |
| 51 | |
| 52 | switch (sdc_no) { |
| 53 | case 0: |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 54 | priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; |
| 55 | priv->mclkreg = &ccm->sd0_clk_cfg; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 56 | break; |
| 57 | case 1: |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 58 | priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; |
| 59 | priv->mclkreg = &ccm->sd1_clk_cfg; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 60 | break; |
| 61 | case 2: |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 62 | priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; |
| 63 | priv->mclkreg = &ccm->sd2_clk_cfg; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 64 | break; |
| 65 | case 3: |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 66 | priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; |
| 67 | priv->mclkreg = &ccm->sd3_clk_cfg; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 68 | break; |
| 69 | default: |
| 70 | printf("Wrong mmc number %d\n", sdc_no); |
| 71 | return -1; |
| 72 | } |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 73 | priv->mmc_no = sdc_no; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 74 | |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 75 | cd_pin = sunxi_mmc_getcd_gpio(sdc_no); |
Hans de Goede | 90641f8 | 2015-04-22 17:03:17 +0200 | [diff] [blame] | 76 | if (cd_pin >= 0) { |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 77 | ret = gpio_request(cd_pin, "mmc_cd"); |
Hans de Goede | 1c09fa3 | 2015-05-30 16:39:10 +0200 | [diff] [blame] | 78 | if (!ret) { |
| 79 | sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP); |
Axel Lin | b0c4ae1 | 2014-12-20 11:41:25 +0800 | [diff] [blame] | 80 | ret = gpio_direction_input(cd_pin); |
Hans de Goede | 1c09fa3 | 2015-05-30 16:39:10 +0200 | [diff] [blame] | 81 | } |
Axel Lin | b0c4ae1 | 2014-12-20 11:41:25 +0800 | [diff] [blame] | 82 | } |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 83 | |
| 84 | return ret; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 85 | } |
| 86 | |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 87 | static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 88 | { |
| 89 | unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; |
| 90 | |
| 91 | if (hz <= 24000000) { |
| 92 | pll = CCM_MMC_CTRL_OSCM24; |
| 93 | pll_hz = 24000000; |
| 94 | } else { |
Hans de Goede | daf2263 | 2015-01-14 19:05:03 +0100 | [diff] [blame] | 95 | #ifdef CONFIG_MACH_SUN9I |
| 96 | pll = CCM_MMC_CTRL_PLL_PERIPH0; |
| 97 | pll_hz = clock_get_pll4_periph0(); |
| 98 | #else |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 99 | pll = CCM_MMC_CTRL_PLL6; |
| 100 | pll_hz = clock_get_pll6(); |
Hans de Goede | daf2263 | 2015-01-14 19:05:03 +0100 | [diff] [blame] | 101 | #endif |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | div = pll_hz / hz; |
| 105 | if (pll_hz % hz) |
| 106 | div++; |
| 107 | |
| 108 | n = 0; |
| 109 | while (div > 16) { |
| 110 | n++; |
| 111 | div = (div + 1) / 2; |
| 112 | } |
| 113 | |
| 114 | if (n > 3) { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 115 | printf("mmc %u error cannot set clock to %u\n", priv->mmc_no, |
| 116 | hz); |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 117 | return -1; |
| 118 | } |
| 119 | |
| 120 | /* determine delays */ |
| 121 | if (hz <= 400000) { |
| 122 | oclk_dly = 0; |
Hans de Goede | be90974 | 2015-09-23 16:13:10 +0200 | [diff] [blame] | 123 | sclk_dly = 0; |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 124 | } else if (hz <= 25000000) { |
| 125 | oclk_dly = 0; |
| 126 | sclk_dly = 5; |
Hans de Goede | be90974 | 2015-09-23 16:13:10 +0200 | [diff] [blame] | 127 | #ifdef CONFIG_MACH_SUN9I |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 128 | } else if (hz <= 50000000) { |
Hans de Goede | be90974 | 2015-09-23 16:13:10 +0200 | [diff] [blame] | 129 | oclk_dly = 5; |
| 130 | sclk_dly = 4; |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 131 | } else { |
| 132 | /* hz > 50000000 */ |
| 133 | oclk_dly = 2; |
| 134 | sclk_dly = 4; |
Hans de Goede | be90974 | 2015-09-23 16:13:10 +0200 | [diff] [blame] | 135 | #else |
| 136 | } else if (hz <= 50000000) { |
| 137 | oclk_dly = 3; |
| 138 | sclk_dly = 4; |
| 139 | } else { |
| 140 | /* hz > 50000000 */ |
| 141 | oclk_dly = 1; |
| 142 | sclk_dly = 4; |
| 143 | #endif |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | |
| 147 | CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 148 | CCM_MMC_CTRL_M(div), priv->mclkreg); |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 149 | |
| 150 | debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 151 | priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div); |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 152 | |
| 153 | return 0; |
| 154 | } |
| 155 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 156 | static int mmc_update_clk(struct sunxi_mmc_priv *priv) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 157 | { |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 158 | unsigned int cmd; |
| 159 | unsigned timeout_msecs = 2000; |
| 160 | |
| 161 | cmd = SUNXI_MMC_CMD_START | |
| 162 | SUNXI_MMC_CMD_UPCLK_ONLY | |
| 163 | SUNXI_MMC_CMD_WAIT_PRE_OVER; |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 164 | writel(cmd, &priv->reg->cmd); |
| 165 | while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) { |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 166 | if (!timeout_msecs--) |
| 167 | return -1; |
| 168 | udelay(1000); |
| 169 | } |
| 170 | |
| 171 | /* clock update sets various irq status bits, clear these */ |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 172 | writel(readl(&priv->reg->rint), &priv->reg->rint); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 177 | static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 178 | { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 179 | unsigned rval = readl(&priv->reg->clkcr); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 180 | |
| 181 | /* Disable Clock */ |
| 182 | rval &= ~SUNXI_MMC_CLK_ENABLE; |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 183 | writel(rval, &priv->reg->clkcr); |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 184 | if (mmc_update_clk(priv)) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 185 | return -1; |
| 186 | |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 187 | /* Set mod_clk to new rate */ |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 188 | if (mmc_set_mod_clk(priv, mmc->clock)) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 189 | return -1; |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 190 | |
| 191 | /* Clear internal divider */ |
| 192 | rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 193 | writel(rval, &priv->reg->clkcr); |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 194 | |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 195 | /* Re-enable Clock */ |
| 196 | rval |= SUNXI_MMC_CLK_ENABLE; |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 197 | writel(rval, &priv->reg->clkcr); |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 198 | if (mmc_update_clk(priv)) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 199 | return -1; |
| 200 | |
| 201 | return 0; |
| 202 | } |
| 203 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 204 | static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv, |
| 205 | struct mmc *mmc) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 206 | { |
Hans de Goede | fc3a832 | 2014-12-07 20:55:10 +0100 | [diff] [blame] | 207 | debug("set ios: bus_width: %x, clock: %d\n", |
| 208 | mmc->bus_width, mmc->clock); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 209 | |
| 210 | /* Change clock first */ |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 211 | if (mmc->clock && mmc_config_clock(priv, mmc) != 0) { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 212 | priv->fatal_err = 1; |
Jaehoon Chung | 07b0b9c | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 213 | return -EINVAL; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | /* Change bus width */ |
| 217 | if (mmc->bus_width == 8) |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 218 | writel(0x2, &priv->reg->width); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 219 | else if (mmc->bus_width == 4) |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 220 | writel(0x1, &priv->reg->width); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 221 | else |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 222 | writel(0x0, &priv->reg->width); |
Jaehoon Chung | 07b0b9c | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 223 | |
| 224 | return 0; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 225 | } |
| 226 | |
Siarhei Siamashka | 5abdb15 | 2015-02-01 00:42:14 +0200 | [diff] [blame] | 227 | static int sunxi_mmc_core_init(struct mmc *mmc) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 228 | { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 229 | struct sunxi_mmc_priv *priv = mmc->priv; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 230 | |
| 231 | /* Reset controller */ |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 232 | writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); |
Hans de Goede | b6ae676 | 2014-06-09 11:36:55 +0200 | [diff] [blame] | 233 | udelay(1000); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 238 | static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc, |
| 239 | struct mmc_data *data) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 240 | { |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 241 | const int reading = !!(data->flags & MMC_DATA_READ); |
| 242 | const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : |
| 243 | SUNXI_MMC_STATUS_FIFO_FULL; |
| 244 | unsigned i; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 245 | unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); |
Yousong Zhou | 28f69b9 | 2015-08-29 21:26:11 +0800 | [diff] [blame] | 246 | unsigned byte_cnt = data->blocksize * data->blocks; |
Tobias Doerffel | 26c0c15 | 2016-07-08 12:40:14 +0200 | [diff] [blame] | 247 | unsigned timeout_usecs = (byte_cnt >> 8) * 1000; |
| 248 | if (timeout_usecs < 2000000) |
| 249 | timeout_usecs = 2000000; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 250 | |
Hans de Goede | b6ae676 | 2014-06-09 11:36:55 +0200 | [diff] [blame] | 251 | /* Always read / write data through the CPU */ |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 252 | setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); |
Hans de Goede | b6ae676 | 2014-06-09 11:36:55 +0200 | [diff] [blame] | 253 | |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 254 | for (i = 0; i < (byte_cnt >> 2); i++) { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 255 | while (readl(&priv->reg->status) & status_bit) { |
Tobias Doerffel | 26c0c15 | 2016-07-08 12:40:14 +0200 | [diff] [blame] | 256 | if (!timeout_usecs--) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 257 | return -1; |
Tobias Doerffel | 26c0c15 | 2016-07-08 12:40:14 +0200 | [diff] [blame] | 258 | udelay(1); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | if (reading) |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 262 | buff[i] = readl(&priv->reg->fifo); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 263 | else |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 264 | writel(buff[i], &priv->reg->fifo); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 270 | static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc, |
| 271 | uint timeout_msecs, uint done_bit, const char *what) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 272 | { |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 273 | unsigned int status; |
| 274 | |
| 275 | do { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 276 | status = readl(&priv->reg->rint); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 277 | if (!timeout_msecs-- || |
| 278 | (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { |
| 279 | debug("%s timeout %x\n", what, |
| 280 | status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 281 | return -ETIMEDOUT; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 282 | } |
| 283 | udelay(1000); |
| 284 | } while (!(status & done_bit)); |
| 285 | |
| 286 | return 0; |
| 287 | } |
| 288 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 289 | static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, |
| 290 | struct mmc *mmc, struct mmc_cmd *cmd, |
| 291 | struct mmc_data *data) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 292 | { |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 293 | unsigned int cmdval = SUNXI_MMC_CMD_START; |
| 294 | unsigned int timeout_msecs; |
| 295 | int error = 0; |
| 296 | unsigned int status = 0; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 297 | unsigned int bytecnt = 0; |
| 298 | |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 299 | if (priv->fatal_err) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 300 | return -1; |
| 301 | if (cmd->resp_type & MMC_RSP_BUSY) |
| 302 | debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); |
| 303 | if (cmd->cmdidx == 12) |
| 304 | return 0; |
| 305 | |
| 306 | if (!cmd->cmdidx) |
| 307 | cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; |
| 308 | if (cmd->resp_type & MMC_RSP_PRESENT) |
| 309 | cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; |
| 310 | if (cmd->resp_type & MMC_RSP_136) |
| 311 | cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; |
| 312 | if (cmd->resp_type & MMC_RSP_CRC) |
| 313 | cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; |
| 314 | |
| 315 | if (data) { |
Alexander Graf | 0ea5a04 | 2016-03-29 17:29:09 +0200 | [diff] [blame] | 316 | if ((u32)(long)data->dest & 0x3) { |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 317 | error = -1; |
| 318 | goto out; |
| 319 | } |
| 320 | |
| 321 | cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; |
| 322 | if (data->flags & MMC_DATA_WRITE) |
| 323 | cmdval |= SUNXI_MMC_CMD_WRITE; |
| 324 | if (data->blocks > 1) |
| 325 | cmdval |= SUNXI_MMC_CMD_AUTO_STOP; |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 326 | writel(data->blocksize, &priv->reg->blksz); |
| 327 | writel(data->blocks * data->blocksize, &priv->reg->bytecnt); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 328 | } |
| 329 | |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 330 | debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no, |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 331 | cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 332 | writel(cmd->cmdarg, &priv->reg->arg); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 333 | |
| 334 | if (!data) |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 335 | writel(cmdval | cmd->cmdidx, &priv->reg->cmd); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 336 | |
| 337 | /* |
| 338 | * transfer data and check status |
| 339 | * STATREG[2] : FIFO empty |
| 340 | * STATREG[3] : FIFO full |
| 341 | */ |
| 342 | if (data) { |
| 343 | int ret = 0; |
| 344 | |
| 345 | bytecnt = data->blocksize * data->blocks; |
| 346 | debug("trans data %d bytes\n", bytecnt); |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 347 | writel(cmdval | cmd->cmdidx, &priv->reg->cmd); |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 348 | ret = mmc_trans_data_by_cpu(priv, mmc, data); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 349 | if (ret) { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 350 | error = readl(&priv->reg->rint) & |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 351 | SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 352 | error = -ETIMEDOUT; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 353 | goto out; |
| 354 | } |
| 355 | } |
| 356 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 357 | error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, |
| 358 | "cmd"); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 359 | if (error) |
| 360 | goto out; |
| 361 | |
| 362 | if (data) { |
Hans de Goede | b6ae676 | 2014-06-09 11:36:55 +0200 | [diff] [blame] | 363 | timeout_msecs = 120; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 364 | debug("cacl timeout %x msec\n", timeout_msecs); |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 365 | error = mmc_rint_wait(priv, mmc, timeout_msecs, |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 366 | data->blocks > 1 ? |
| 367 | SUNXI_MMC_RINT_AUTO_COMMAND_DONE : |
| 368 | SUNXI_MMC_RINT_DATA_OVER, |
| 369 | "data"); |
| 370 | if (error) |
| 371 | goto out; |
| 372 | } |
| 373 | |
| 374 | if (cmd->resp_type & MMC_RSP_BUSY) { |
| 375 | timeout_msecs = 2000; |
| 376 | do { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 377 | status = readl(&priv->reg->status); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 378 | if (!timeout_msecs--) { |
| 379 | debug("busy timeout\n"); |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 380 | error = -ETIMEDOUT; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 381 | goto out; |
| 382 | } |
| 383 | udelay(1000); |
| 384 | } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); |
| 385 | } |
| 386 | |
| 387 | if (cmd->resp_type & MMC_RSP_136) { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 388 | cmd->response[0] = readl(&priv->reg->resp3); |
| 389 | cmd->response[1] = readl(&priv->reg->resp2); |
| 390 | cmd->response[2] = readl(&priv->reg->resp1); |
| 391 | cmd->response[3] = readl(&priv->reg->resp0); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 392 | debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 393 | cmd->response[3], cmd->response[2], |
| 394 | cmd->response[1], cmd->response[0]); |
| 395 | } else { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 396 | cmd->response[0] = readl(&priv->reg->resp0); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 397 | debug("mmc resp 0x%08x\n", cmd->response[0]); |
| 398 | } |
| 399 | out: |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 400 | if (error < 0) { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 401 | writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 402 | mmc_update_clk(priv); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 403 | } |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 404 | writel(0xffffffff, &priv->reg->rint); |
| 405 | writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, |
| 406 | &priv->reg->gctrl); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 407 | |
| 408 | return error; |
| 409 | } |
| 410 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 411 | static int sunxi_mmc_set_ios_legacy(struct mmc *mmc) |
| 412 | { |
| 413 | struct sunxi_mmc_priv *priv = mmc->priv; |
| 414 | |
| 415 | return sunxi_mmc_set_ios_common(priv, mmc); |
| 416 | } |
| 417 | |
| 418 | static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd, |
| 419 | struct mmc_data *data) |
| 420 | { |
| 421 | struct sunxi_mmc_priv *priv = mmc->priv; |
| 422 | |
| 423 | return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data); |
| 424 | } |
| 425 | |
| 426 | static int sunxi_mmc_getcd_legacy(struct mmc *mmc) |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 427 | { |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 428 | struct sunxi_mmc_priv *priv = mmc->priv; |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 429 | int cd_pin; |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 430 | |
Simon Glass | 3f5af12 | 2017-07-04 13:31:24 -0600 | [diff] [blame] | 431 | cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no); |
Hans de Goede | 90641f8 | 2015-04-22 17:03:17 +0200 | [diff] [blame] | 432 | if (cd_pin < 0) |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 433 | return 1; |
| 434 | |
Axel Lin | b0c4ae1 | 2014-12-20 11:41:25 +0800 | [diff] [blame] | 435 | return !gpio_get_value(cd_pin); |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 436 | } |
| 437 | |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 438 | static const struct mmc_ops sunxi_mmc_ops = { |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 439 | .send_cmd = sunxi_mmc_send_cmd_legacy, |
| 440 | .set_ios = sunxi_mmc_set_ios_legacy, |
Siarhei Siamashka | 5abdb15 | 2015-02-01 00:42:14 +0200 | [diff] [blame] | 441 | .init = sunxi_mmc_core_init, |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 442 | .getcd = sunxi_mmc_getcd_legacy, |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 443 | }; |
| 444 | |
Hans de Goede | e79c7c8 | 2014-10-02 21:13:54 +0200 | [diff] [blame] | 445 | struct mmc *sunxi_mmc_init(int sdc_no) |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 446 | { |
Simon Glass | ec73d96 | 2017-07-04 13:31:26 -0600 | [diff] [blame^] | 447 | struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 448 | struct sunxi_mmc_priv *priv = &mmc_host[sdc_no]; |
| 449 | struct mmc_config *cfg = &priv->cfg; |
Simon Glass | ec73d96 | 2017-07-04 13:31:26 -0600 | [diff] [blame^] | 450 | int ret; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 451 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 452 | memset(priv, '\0', sizeof(struct sunxi_mmc_priv)); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 453 | |
| 454 | cfg->name = "SUNXI SD/MMC"; |
| 455 | cfg->ops = &sunxi_mmc_ops; |
| 456 | |
| 457 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
| 458 | cfg->host_caps = MMC_MODE_4BIT; |
Maxime Ripard | fb01318 | 2016-11-04 16:18:09 +0100 | [diff] [blame] | 459 | #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) |
Siarhei Siamashka | d96ebc4 | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 460 | if (sdc_no == 2) |
| 461 | cfg->host_caps = MMC_MODE_8BIT; |
| 462 | #endif |
Rob Herring | 5a20397 | 2015-03-23 17:56:59 -0500 | [diff] [blame] | 463 | cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 464 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
| 465 | |
| 466 | cfg->f_min = 400000; |
| 467 | cfg->f_max = 52000000; |
| 468 | |
Hans de Goede | 967325f | 2014-10-31 16:55:02 +0100 | [diff] [blame] | 469 | if (mmc_resource_init(sdc_no) != 0) |
| 470 | return NULL; |
| 471 | |
Simon Glass | ec73d96 | 2017-07-04 13:31:26 -0600 | [diff] [blame^] | 472 | /* config ahb clock */ |
| 473 | debug("init mmc %d clock and io\n", sdc_no); |
| 474 | setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); |
| 475 | |
| 476 | #ifdef CONFIG_SUNXI_GEN_SUN6I |
| 477 | /* unassert reset */ |
| 478 | setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); |
| 479 | #endif |
| 480 | #if defined(CONFIG_MACH_SUN9I) |
| 481 | /* sun9i has a mmc-common module, also set the gate and reset there */ |
| 482 | writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET, |
| 483 | SUNXI_MMC_COMMON_BASE + 4 * sdc_no); |
| 484 | #endif |
| 485 | ret = mmc_set_mod_clk(priv, 24000000); |
| 486 | if (ret) |
| 487 | return NULL; |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 488 | |
Simon Glass | 034e226 | 2017-07-04 13:31:25 -0600 | [diff] [blame] | 489 | return mmc_create(cfg, mmc_host); |
Ian Campbell | e24ea55 | 2014-05-05 14:42:31 +0100 | [diff] [blame] | 490 | } |