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Kumar Gala129ba612008-08-12 11:13:08 -05001/*
Kumar Gala561e7102011-01-31 15:51:20 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala129ba612008-08-12 11:13:08 -05003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala129ba612008-08-12 11:13:08 -05005 */
6
7#include <common.h>
8#include <command.h>
9#include <pci.h>
10#include <asm/processor.h>
11#include <asm/mmu.h>
Kumar Gala7c0d4a72008-09-22 14:11:11 -050012#include <asm/cache.h>
Kumar Gala129ba612008-08-12 11:13:08 -050013#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050014#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070015#include <fsl_ddr_sdram.h>
Kumar Gala129ba612008-08-12 11:13:08 -050016#include <asm/io.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060017#include <asm/fsl_serdes.h>
Kumar Gala129ba612008-08-12 11:13:08 -050018#include <miiphy.h>
19#include <libfdt.h>
20#include <fdt_support.h>
Liu Yu7e183ca2008-10-10 11:40:59 +080021#include <tsec.h>
Andy Fleming063c1262011-04-08 02:10:54 -050022#include <fsl_mdio.h>
Kumar Galab560ab82009-08-08 10:42:30 -050023#include <netdev.h>
Kumar Gala129ba612008-08-12 11:13:08 -050024
Liu Yu7e183ca2008-10-10 11:40:59 +080025#include "../common/sgmii_riser.h"
Kumar Gala129ba612008-08-12 11:13:08 -050026
Kumar Gala129ba612008-08-12 11:13:08 -050027int checkboard (void)
28{
Kumar Gala6bb5b412009-07-14 22:42:01 -050029 u8 vboot;
30 u8 *pixis_base = (u8 *)PIXIS_BASE;
31
Timur Tabi5d065c32012-03-15 11:42:27 +000032 printf("Board: MPC8572DS Sys ID: 0x%02x, "
Kumar Gala6bb5b412009-07-14 22:42:01 -050033 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
34 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
35 in_8(pixis_base + PIXIS_PVER));
36
37 vboot = in_8(pixis_base + PIXIS_VBOOT);
38 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
39 case PIXIS_VBOOT_LBMAP_NOR0:
40 puts ("vBank: 0\n");
41 break;
42 case PIXIS_VBOOT_LBMAP_PJET:
43 puts ("Promjet\n");
44 break;
45 case PIXIS_VBOOT_LBMAP_NAND:
46 puts ("NAND\n");
47 break;
48 case PIXIS_VBOOT_LBMAP_NOR1:
49 puts ("vBank: 1\n");
50 break;
51 }
52
Kumar Gala129ba612008-08-12 11:13:08 -050053 return 0;
54}
55
Kumar Gala129ba612008-08-12 11:13:08 -050056
57#if !defined(CONFIG_SPD_EEPROM)
58/*
59 * Fixed sdram init -- doesn't use serial presence detect.
60 */
61
62phys_size_t fixed_sdram (void)
63{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
York Sun9a17eb52013-11-18 10:29:32 -080065 struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
Kumar Gala129ba612008-08-12 11:13:08 -050066 uint d_init;
67
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
69 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
Kumar Gala129ba612008-08-12 11:13:08 -050070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
72 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
73 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
74 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
75 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
76 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
77 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
78 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
79 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
80 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Kumar Gala129ba612008-08-12 11:13:08 -050081
82#if defined (CONFIG_DDR_ECC)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
84 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
85 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
Kumar Gala129ba612008-08-12 11:13:08 -050086#endif
87 asm("sync;isync");
88
89 udelay(500);
90
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Kumar Gala129ba612008-08-12 11:13:08 -050092
93#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
94 d_init = 1;
95 debug("DDR - 1st controller: memory initializing\n");
96 /*
97 * Poll until memory is initialized.
98 * 512 Meg at 400 might hit this 200 times or so.
99 */
100 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
101 udelay(1000);
102 }
103 debug("DDR: memory initialized\n\n");
104 asm("sync; isync");
105 udelay(500);
106#endif
107
108 return 512 * 1024 * 1024;
109}
110
111#endif
112
Kumar Gala129ba612008-08-12 11:13:08 -0500113#ifdef CONFIG_PCI
114void pci_init_board(void)
115{
Kumar Gala18ea5552010-12-17 06:53:52 -0600116 struct pci_controller *hose;
Kumar Galaf61dae72009-09-03 10:20:09 -0500117
Kumar Gala18ea5552010-12-17 06:53:52 -0600118 fsl_pcie_init_board(0);
Kumar Galaf61dae72009-09-03 10:20:09 -0500119
Kumar Gala18ea5552010-12-17 06:53:52 -0600120 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
Kumar Gala129ba612008-08-12 11:13:08 -0500121
Kumar Gala18ea5552010-12-17 06:53:52 -0600122 if (hose) {
123 u32 temp32;
124 u8 uli_busno = hose->first_busno + 2;
Kumar Gala129ba612008-08-12 11:13:08 -0500125
Kumar Galaf61dae72009-09-03 10:20:09 -0500126 /*
127 * Activate ULI1575 legacy chip by performing a fake
128 * memory access. Needed to make ULI RTC work.
129 * Device 1d has the first on-board memory BAR.
130 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600131 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
Kumar Galaf61dae72009-09-03 10:20:09 -0500132 PCI_BASE_ADDRESS_1, &temp32);
Kumar Gala18ea5552010-12-17 06:53:52 -0600133
Kumar Galaf61dae72009-09-03 10:20:09 -0500134 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
Kumar Gala18ea5552010-12-17 06:53:52 -0600135 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
Kumar Galaf61dae72009-09-03 10:20:09 -0500136 temp32, 4, 0);
137 debug(" uli1572 read to %p\n", p);
138 in_be32(p);
Kumar Gala129ba612008-08-12 11:13:08 -0500139 }
Kumar Gala129ba612008-08-12 11:13:08 -0500140 }
Kumar Gala129ba612008-08-12 11:13:08 -0500141}
142#endif
143
144int board_early_init_r(void)
145{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
Kumar Gala5fb6ea32009-11-13 09:25:07 -0600147 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
Kumar Gala129ba612008-08-12 11:13:08 -0500148
149 /*
150 * Remap Boot flash + PROMJET region to caching-inhibited
151 * so that flash can be erased properly.
152 */
153
Kumar Gala7c0d4a72008-09-22 14:11:11 -0500154 /* Flush d-cache and invalidate i-cache of any FLASH data */
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100155 flush_dcache();
156 invalidate_icache();
Kumar Gala129ba612008-08-12 11:13:08 -0500157
158 /* invalidate existing TLB entry for flash + promjet */
159 disable_tlb(flash_esel);
160
Kumar Galac953ddf2008-12-02 14:19:34 -0600161 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
Kumar Gala129ba612008-08-12 11:13:08 -0500162 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
163 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
164
165 return 0;
166}
167
Liu Yu7e183ca2008-10-10 11:40:59 +0800168#ifdef CONFIG_TSEC_ENET
169int board_eth_init(bd_t *bis)
170{
Andy Fleming063c1262011-04-08 02:10:54 -0500171 struct fsl_pq_mdio_info mdio_info;
Liu Yu7e183ca2008-10-10 11:40:59 +0800172 struct tsec_info_struct tsec_info[4];
Liu Yu7e183ca2008-10-10 11:40:59 +0800173 int num = 0;
174
175#ifdef CONFIG_TSEC1
176 SET_STD_TSEC_INFO(tsec_info[num], 1);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600177 if (is_serdes_configured(SGMII_TSEC1)) {
178 puts("eTSEC1 is in sgmii mode.\n");
Liu Yu7e183ca2008-10-10 11:40:59 +0800179 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600180 }
Liu Yu7e183ca2008-10-10 11:40:59 +0800181 num++;
182#endif
183#ifdef CONFIG_TSEC2
184 SET_STD_TSEC_INFO(tsec_info[num], 2);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600185 if (is_serdes_configured(SGMII_TSEC2)) {
186 puts("eTSEC2 is in sgmii mode.\n");
Liu Yu7e183ca2008-10-10 11:40:59 +0800187 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600188 }
Liu Yu7e183ca2008-10-10 11:40:59 +0800189 num++;
190#endif
191#ifdef CONFIG_TSEC3
192 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600193 if (is_serdes_configured(SGMII_TSEC3)) {
194 puts("eTSEC3 is in sgmii mode.\n");
Liu Yu7e183ca2008-10-10 11:40:59 +0800195 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600196 }
Liu Yu7e183ca2008-10-10 11:40:59 +0800197 num++;
198#endif
199#ifdef CONFIG_TSEC4
200 SET_STD_TSEC_INFO(tsec_info[num], 4);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600201 if (is_serdes_configured(SGMII_TSEC4)) {
202 puts("eTSEC4 is in sgmii mode.\n");
Liu Yu7e183ca2008-10-10 11:40:59 +0800203 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600204 }
Liu Yu7e183ca2008-10-10 11:40:59 +0800205 num++;
206#endif
207
208 if (!num) {
209 printf("No TSECs initialized\n");
210
211 return 0;
212 }
213
Andy Flemingfeede8b2008-12-05 20:10:22 -0600214#ifdef CONFIG_FSL_SGMII_RISER
Liu Yu7e183ca2008-10-10 11:40:59 +0800215 fsl_sgmii_riser_init(tsec_info, num);
Andy Flemingfeede8b2008-12-05 20:10:22 -0600216#endif
Liu Yu7e183ca2008-10-10 11:40:59 +0800217
Andy Fleming063c1262011-04-08 02:10:54 -0500218 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
219 mdio_info.name = DEFAULT_MII_NAME;
220 fsl_pq_mdio_init(bis, &mdio_info);
221
Liu Yu7e183ca2008-10-10 11:40:59 +0800222 tsec_eth_init(bis, tsec_info, num);
223
Kumar Galab560ab82009-08-08 10:42:30 -0500224 return pci_eth_init(bis);
Liu Yu7e183ca2008-10-10 11:40:59 +0800225}
226#endif
227
Kumar Gala129ba612008-08-12 11:13:08 -0500228#if defined(CONFIG_OF_BOARD_SETUP)
229void ft_board_setup(void *blob, bd_t *bd)
230{
Kumar Galab6730512009-02-09 22:03:04 -0600231 phys_addr_t base;
232 phys_size_t size;
Kumar Gala129ba612008-08-12 11:13:08 -0500233
234 ft_cpu_setup(blob, bd);
235
236 base = getenv_bootm_low();
237 size = getenv_bootm_size();
238
239 fdt_fixup_memory(blob, (u64)base, (u64)size);
240
Kumar Gala6525d512010-07-08 22:37:44 -0500241 FT_FSL_PCI_SETUP;
242
Andy Flemingfeede8b2008-12-05 20:10:22 -0600243#ifdef CONFIG_FSL_SGMII_RISER
244 fsl_sgmii_riser_fdt_fixup(blob);
245#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500246}
247#endif