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Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi2ad6b512006-10-31 18:44:42 -06003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Timur Tabi2ad6b512006-10-31 18:44:42 -06005 */
6
7/*
Timur Tabi7a78f142007-01-31 15:54:29 -06008 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi2ad6b512006-10-31 18:44:42 -06009
10 Memory map:
11
12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi7a78f142007-01-31 15:54:29 -060018 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060019 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi7a78f142007-01-31 15:54:29 -060020 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060023
24 I2C address list:
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010025 Align. Board
26 Bus Addr Part No. Description Length Location
Timur Tabi2ad6b512006-10-31 18:44:42 -060027 ----------------------------------------------------------------
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010028 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi2ad6b512006-10-31 18:44:42 -060029
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010030 I2C1 0x20 PCF8574 I2C Expander 0 U8
31 I2C1 0x21 PCF8574 I2C Expander 0 U10
32 I2C1 0x38 PCF8574A I2C Expander 0 U8
33 I2C1 0x39 PCF8574A I2C Expander 0 U10
34 I2C1 0x51 (DDR) DDR EEPROM 1 U1
35 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi2ad6b512006-10-31 18:44:42 -060036
37 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
38*/
39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
Wolfgang Denk14d0a022010-10-07 21:51:12 +020043#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_LOWBOOT
Timur Tabi7a78f142007-01-31 15:54:29 -060045#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060046
47/*
48 * High Level Configuration Options
49 */
Peter Tyser2c7920a2009-05-22 17:23:25 -050050#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
Timur Tabi2ad6b512006-10-31 18:44:42 -060051#define CONFIG_MPC8349 /* MPC8349 specific */
52
Wolfgang Denk2ae18242010-10-06 09:05:45 +020053#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFEF00000
55#endif
56
Joe Hershberger396abba2011-10-11 23:57:15 -050057#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
Timur Tabi2ad6b512006-10-31 18:44:42 -060058
Timur Tabi89c77842008-02-08 13:15:55 -060059#define CONFIG_MISC_INIT_F
60#define CONFIG_MISC_INIT_R
Timur Tabi7a78f142007-01-31 15:54:29 -060061
Timur Tabi89c77842008-02-08 13:15:55 -060062/*
63 * On-board devices
64 */
Timur Tabi7a78f142007-01-31 15:54:29 -060065
66#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -050067/* The CF card interface on the back of the board */
68#define CONFIG_COMPACT_FLASH
Timur Tabi89c77842008-02-08 13:15:55 -060069#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +020070#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +030071#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
Timur Tabi7a78f142007-01-31 15:54:29 -060072#endif
73
74#define CONFIG_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -060075#define CONFIG_RTC_DS1337
Heiko Schocher00f792e2012-10-24 13:48:22 +020076#define CONFIG_SYS_I2C
Timur Tabi7a78f142007-01-31 15:54:29 -060077#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
78
79/*
80 * Device configurations
81 */
Timur Tabi2ad6b512006-10-31 18:44:42 -060082
83/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020084#ifdef CONFIG_SYS_I2C
85#define CONFIG_SYS_I2C_FSL
86#define CONFIG_SYS_FSL_I2C_SPEED 400000
87#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
88#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
89#define CONFIG_SYS_FSL_I2C2_SPEED 400000
90#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
91#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabi2ad6b512006-10-31 18:44:42 -060092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +020094#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi2ad6b512006-10-31 18:44:42 -060095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
97#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
98#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
99#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
100#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
Joe Hershberger396abba2011-10-11 23:57:15 -0500101#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
102#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600103
Timur Tabi2ad6b512006-10-31 18:44:42 -0600104/* Don't probe these addresses: */
Joe Hershberger396abba2011-10-11 23:57:15 -0500105#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
107 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
Joe Hershberger396abba2011-10-11 23:57:15 -0500108 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
Timur Tabi2ad6b512006-10-31 18:44:42 -0600109/* Bit definitions for the 8574[A] I2C expander */
Joe Hershberger396abba2011-10-11 23:57:15 -0500110 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
111#define I2C_8574_REVISION 0x03
Timur Tabi2ad6b512006-10-31 18:44:42 -0600112#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
113#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
114#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
115#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
116
Timur Tabi2ad6b512006-10-31 18:44:42 -0600117#endif
118
Timur Tabi7a78f142007-01-31 15:54:29 -0600119/* Compact Flash */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600120#ifdef CONFIG_COMPACT_FLASH
121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_IDE_MAXBUS 1
123#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
126#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
127#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
128#define CONFIG_SYS_ATA_REG_OFFSET 0
129#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
130#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600131
Joe Hershberger396abba2011-10-11 23:57:15 -0500132/* If a CF card is not inserted, time out quickly */
133#define ATA_RESET_TIME 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600134
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200135#endif
136
137/*
138 * SATA
139 */
140#ifdef CONFIG_SATA_SIL3114
141
142#define CONFIG_SYS_SATA_MAX_DEVICE 4
143#define CONFIG_LIBATA
144#define CONFIG_LBA48
Timur Tabi2ad6b512006-10-31 18:44:42 -0600145
Timur Tabi7a78f142007-01-31 15:54:29 -0600146#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600147
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300148#ifdef CONFIG_SYS_USB_HOST
149/*
150 * Support USB
151 */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300152#define CONFIG_USB_EHCI
153#define CONFIG_USB_EHCI_FSL
154
155/* Current USB implementation supports the only USB controller,
156 * so we have to choose between the MPH or the DR ones */
157#if 1
158#define CONFIG_HAS_FSL_MPH_USB
159#else
160#define CONFIG_HAS_FSL_DR_USB
161#endif
162
163#endif
164
Timur Tabi7a78f142007-01-31 15:54:29 -0600165/*
166 * DDR Setup
167 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500168#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
170#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
171#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger396abba2011-10-11 23:57:15 -0500172#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi7a78f142007-01-31 15:54:29 -0600174
Joe Hershberger396abba2011-10-11 23:57:15 -0500175#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
176 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabif64702b2007-04-30 13:59:50 -0500177
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200178#define CONFIG_VERY_BIG_RAM
179#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
180
Heiko Schocher00f792e2012-10-24 13:48:22 +0200181#ifdef CONFIG_SYS_I2C
Timur Tabi7a78f142007-01-31 15:54:29 -0600182#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
183#endif
184
Joe Hershberger396abba2011-10-11 23:57:15 -0500185/* No SPD? Then manually set up DDR parameters */
186#ifndef CONFIG_SPD_EEPROM
187 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
Joe Hershberger2e651b22011-10-11 23:57:31 -0500188 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger396abba2011-10-11 23:57:15 -0500189 | CSCONFIG_ROW_BIT_13 \
190 | CSCONFIG_COL_BIT_10)
Timur Tabi7a78f142007-01-31 15:54:29 -0600191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
193 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi7a78f142007-01-31 15:54:29 -0600194#endif
195
196/*
197 *Flash on the Local Bus
198 */
199
Joe Hershberger396abba2011-10-11 23:57:15 -0500200#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
201#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
203#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hershberger396abba2011-10-11 23:57:15 -0500204/* 127 64KB sectors + 8 8KB sectors per device */
205#define CONFIG_SYS_MAX_FLASH_SECT 135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
207#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
208#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi7a78f142007-01-31 15:54:29 -0600209
210/* The ITX has two flash chips, but the ITX-GP has only one. To support both
211boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_QUIET_TEST
Joe Hershberger396abba2011-10-11 23:57:15 -0500213#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
214#define CONFIG_SYS_FLASH_BANKS_LIST \
215 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
216#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
Joe Hershberger396abba2011-10-11 23:57:15 -0500217#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Timur Tabi7a78f142007-01-31 15:54:29 -0600218
Timur Tabi89c77842008-02-08 13:15:55 -0600219/* Vitesse 7385 */
220
221#ifdef CONFIG_VSC7385_ENET
222
223#define CONFIG_TSEC2
224
225/* The flash address and size of the VSC7385 firmware image */
226#define CONFIG_VSC7385_IMAGE 0xFEFFE000
227#define CONFIG_VSC7385_IMAGE_SIZE 8192
228
229#endif
230
Timur Tabi7a78f142007-01-31 15:54:29 -0600231/*
232 * BRx, ORx, LBLAWBARx, and LBLAWARx
233 */
234
235/* Flash */
236
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500237#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
238 | BR_PS_16 \
239 | BR_MS_GPCM \
240 | BR_V)
241#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger396abba2011-10-11 23:57:15 -0500242 | OR_UPM_XAM \
243 | OR_GPCM_CSNT \
244 | OR_GPCM_ACS_DIV2 \
245 | OR_GPCM_XACS \
246 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500247 | OR_GPCM_TRLX_SET \
248 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500249 | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500251#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600252
253/* Vitesse 7385 */
254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600256
Timur Tabi89c77842008-02-08 13:15:55 -0600257#ifdef CONFIG_VSC7385_ENET
258
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500259#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
260 | BR_PS_8 \
261 | BR_MS_GPCM \
262 | BR_V)
Joe Hershberger396abba2011-10-11 23:57:15 -0500263#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
264 | OR_GPCM_CSNT \
265 | OR_GPCM_XACS \
266 | OR_GPCM_SCY_15 \
267 | OR_GPCM_SETA \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500268 | OR_GPCM_TRLX_SET \
269 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500270 | OR_GPCM_EAD)
Timur Tabi7a78f142007-01-31 15:54:29 -0600271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
273#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600274
275#endif
276
277/* LED */
278
Joe Hershberger396abba2011-10-11 23:57:15 -0500279#define CONFIG_SYS_LED_BASE 0xF9000000
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500280#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
281 | BR_PS_8 \
282 | BR_MS_GPCM \
283 | BR_V)
Joe Hershberger396abba2011-10-11 23:57:15 -0500284#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
285 | OR_GPCM_CSNT \
286 | OR_GPCM_ACS_DIV2 \
287 | OR_GPCM_XACS \
288 | OR_GPCM_SCY_9 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500289 | OR_GPCM_TRLX_SET \
290 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500291 | OR_GPCM_EAD)
Timur Tabi7a78f142007-01-31 15:54:29 -0600292
293/* Compact Flash */
294
295#ifdef CONFIG_COMPACT_FLASH
296
Joe Hershberger396abba2011-10-11 23:57:15 -0500297#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600298
Joe Hershberger396abba2011-10-11 23:57:15 -0500299#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
300 | BR_PS_16 \
301 | BR_MS_UPMA \
302 | BR_V)
303#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
Timur Tabi7a78f142007-01-31 15:54:29 -0600304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
306#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600307
308#endif
309
310/*
311 * U-Boot memory configuration
312 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200313#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
316#define CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600317#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#undef CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600319#endif
320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_INIT_RAM_LOCK
Joe Hershberger396abba2011-10-11 23:57:15 -0500322#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
323#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600324
Joe Hershberger396abba2011-10-11 23:57:15 -0500325#define CONFIG_SYS_GBL_DATA_OFFSET \
326 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi2ad6b512006-10-31 18:44:42 -0600328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao16c8c172016-07-08 11:25:14 +0800330#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500331#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600332
333/*
334 * Local Bus LCRR and LBCR regs
335 * LCRR: DLL bypass, Clock divider is 4
336 * External Local Bus rate is
337 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
338 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500339#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
340#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_LBC_LBCR 0x00000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600342
Joe Hershberger396abba2011-10-11 23:57:15 -0500343 /* LB sdram refresh timer, about 6us */
344#define CONFIG_SYS_LBC_LSRT 0x32000000
345 /* LB refresh timer prescal, 266MHz/32*/
346#define CONFIG_SYS_LBC_MRTPR 0x20000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600347
348/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600349 * Serial Port
350 */
351#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_NS16550_SERIAL
353#define CONFIG_SYS_NS16550_REG_SIZE 1
354#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger396abba2011-10-11 23:57:15 -0500357 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Timur Tabi7a78f142007-01-31 15:54:29 -0600358
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400359#define CONFIG_CONSOLE ttyS0
Timur Tabi7a78f142007-01-31 15:54:29 -0600360#define CONFIG_BAUDRATE 115200
Timur Tabi2ad6b512006-10-31 18:44:42 -0600361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
363#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600364
Timur Tabi7a78f142007-01-31 15:54:29 -0600365/*
366 * PCI
367 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600368#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000369#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600370
371#define CONFIG_MPC83XX_PCI2
372
373/*
374 * General PCI
375 * Addresses are mapped 1-1.
376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
378#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
379#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500380#define CONFIG_SYS_PCI1_MMIO_BASE \
381 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
383#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500384#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
385#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
386#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600387
388#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger396abba2011-10-11 23:57:15 -0500389#define CONFIG_SYS_PCI2_MEM_BASE \
390 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
392#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500393#define CONFIG_SYS_PCI2_MMIO_BASE \
394 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
396#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500397#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
398#define CONFIG_SYS_PCI2_IO_PHYS \
399 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
400#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600401#endif
402
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100403#define CONFIG_PCI_PNP /* do pci plug-and-play */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600404
Timur Tabi2ad6b512006-10-31 18:44:42 -0600405#ifndef CONFIG_PCI_PNP
406 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600408 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
409#endif
410
411#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
412
413#endif
414
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200415#define CONFIG_PCI_66M
416#ifdef CONFIG_PCI_66M
Timur Tabi7a78f142007-01-31 15:54:29 -0600417#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
418#else
419#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
420#endif
421
Timur Tabi2ad6b512006-10-31 18:44:42 -0600422/* TSEC */
423
424#ifdef CONFIG_TSEC_ENET
425
Timur Tabi2ad6b512006-10-31 18:44:42 -0600426#define CONFIG_MII
Jon Loeliger659e2f62007-07-10 09:10:49 -0500427#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600428
Kim Phillips255a35772007-05-16 16:52:19 -0500429#define CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600430
Kim Phillips255a35772007-05-16 16:52:19 -0500431#ifdef CONFIG_TSEC1
Andy Fleming10327dc2007-08-16 16:35:02 -0500432#define CONFIG_HAS_ETH0
Kim Phillips255a35772007-05-16 16:52:19 -0500433#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100435#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600436#define TSEC1_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500437#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600438#endif
439
Kim Phillips255a35772007-05-16 16:52:19 -0500440#ifdef CONFIG_TSEC2
Timur Tabi7a78f142007-01-31 15:54:29 -0600441#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500442#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600444
Timur Tabi2ad6b512006-10-31 18:44:42 -0600445#define TSEC2_PHY_ADDR 4
446#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500447#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600448#endif
449
450#define CONFIG_ETHPRIME "Freescale TSEC"
451
452#endif
453
Timur Tabi2ad6b512006-10-31 18:44:42 -0600454/*
455 * Environment
456 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600457#define CONFIG_ENV_OVERWRITE
458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200460 #define CONFIG_ENV_IS_IN_FLASH
Joe Hershberger396abba2011-10-11 23:57:15 -0500461 #define CONFIG_ENV_ADDR \
462 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200463 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
Joe Hershberger396abba2011-10-11 23:57:15 -0500464 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600465#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500466 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200467 #undef CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200468 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Joe Hershberger396abba2011-10-11 23:57:15 -0500469 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
470 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600471#endif
472
473#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600475
Jon Loeliger8ea54992007-07-04 22:30:06 -0500476/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500477 * BOOTP options
478 */
479#define CONFIG_BOOTP_BOOTFILESIZE
480#define CONFIG_BOOTP_BOOTPATH
481#define CONFIG_BOOTP_GATEWAY
482#define CONFIG_BOOTP_HOSTNAME
483
Jon Loeliger659e2f62007-07-10 09:10:49 -0500484/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500485 * Command line configuration.
486 */
Jon Loeliger8ea54992007-07-04 22:30:06 -0500487#define CONFIG_CMD_DATE
488#define CONFIG_CMD_IRQ
Jon Loeliger8ea54992007-07-04 22:30:06 -0500489#define CONFIG_CMD_SDRAM
Timur Tabi2ad6b512006-10-31 18:44:42 -0600490
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300491#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
Joe Hershberger396abba2011-10-11 23:57:15 -0500492 || defined(CONFIG_USB_STORAGE)
493 #define CONFIG_DOS_PARTITION
Joe Hershberger396abba2011-10-11 23:57:15 -0500494 #define CONFIG_SUPPORT_VFAT
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200495#endif
496
Timur Tabi2ad6b512006-10-31 18:44:42 -0600497#ifdef CONFIG_COMPACT_FLASH
Joe Hershberger396abba2011-10-11 23:57:15 -0500498 #define CONFIG_CMD_IDE
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200499#endif
500
501#ifdef CONFIG_SATA_SIL3114
Joe Hershberger396abba2011-10-11 23:57:15 -0500502 #define CONFIG_CMD_SATA
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300503#endif
504
505#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600506#endif
507
508#ifdef CONFIG_PCI
Joe Hershberger396abba2011-10-11 23:57:15 -0500509 #define CONFIG_CMD_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600510#endif
511
Timur Tabi2ad6b512006-10-31 18:44:42 -0600512/* Watchdog */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600513#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600514
515/*
516 * Miscellaneous configurable options
517 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500518#define CONFIG_SYS_LONGHELP /* undef to save memory */
519#define CONFIG_CMDLINE_EDITING /* Command-line editing */
520#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabi7a78f142007-01-31 15:54:29 -0600521
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips05f91a62009-08-26 21:27:37 -0500523#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Timur Tabi7a78f142007-01-31 15:54:29 -0600524
Jon Loeliger8ea54992007-07-04 22:30:06 -0500525#if defined(CONFIG_CMD_KGDB)
Joe Hershberger396abba2011-10-11 23:57:15 -0500526 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600527#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500528 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600529#endif
530
Joe Hershberger396abba2011-10-11 23:57:15 -0500531 /* Print Buffer Size */
532#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
533#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
534 /* Boot Argument Buffer Size */
535#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600536
537/*
538 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700539 * have to be in the first 256 MB of memory, since this is
Timur Tabi2ad6b512006-10-31 18:44:42 -0600540 * the maximum mapped by the Linux kernel during initialization.
541 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500542 /* Initial Memory map for Linux*/
543#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao63865272016-07-08 11:25:15 +0800544#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600545
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#define CONFIG_SYS_HRCW_LOW (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600547 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
548 HRCWL_DDR_TO_SCB_CLK_1X1 |\
549 HRCWL_CSB_TO_CLKIN_4X1 |\
550 HRCWL_VCO_1X2 |\
551 HRCWL_CORE_TO_CSB_2X1)
552
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#ifdef CONFIG_SYS_LOWBOOT
554#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600555 HRCWH_PCI_HOST |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600556 HRCWH_32_BIT_PCI |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600557 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600558 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600559 HRCWH_CORE_ENABLE |\
560 HRCWH_FROM_0X00000100 |\
561 HRCWH_BOOTSEQ_DISABLE |\
562 HRCWH_SW_WATCHDOG_DISABLE |\
563 HRCWH_ROM_LOC_LOCAL_16BIT |\
564 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger396abba2011-10-11 23:57:15 -0500565 HRCWH_TSEC2M_IN_GMII)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600566#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600568 HRCWH_PCI_HOST |\
569 HRCWH_32_BIT_PCI |\
570 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600571 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600572 HRCWH_CORE_ENABLE |\
573 HRCWH_FROM_0XFFF00100 |\
574 HRCWH_BOOTSEQ_DISABLE |\
575 HRCWH_SW_WATCHDOG_DISABLE |\
576 HRCWH_ROM_LOC_LOCAL_16BIT |\
577 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger396abba2011-10-11 23:57:15 -0500578 HRCWH_TSEC2M_IN_GMII)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600579#endif
580
Timur Tabi7a78f142007-01-31 15:54:29 -0600581/*
582 * System performance
583 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger396abba2011-10-11 23:57:15 -0500585#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
587#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
588#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
589#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300590#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
591#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600592
Timur Tabi7a78f142007-01-31 15:54:29 -0600593/*
594 * System IO Config
595 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500596/* Needed for gigabit to work on TSEC 1 */
597#define CONFIG_SYS_SICRH SICRH_TSOBI1
598 /* USB DR as device + USB MPH as host */
599#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600600
Kim Phillips1a2e2032010-04-20 19:37:54 -0500601#define CONFIG_SYS_HID0_INIT 0x00000000
602#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600603
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500605#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600606
Timur Tabi7a78f142007-01-31 15:54:29 -0600607/* DDR */
Joe Hershberger396abba2011-10-11 23:57:15 -0500608#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500609 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500610 | BATL_MEMCOHERENCE)
611#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
612 | BATU_BL_256M \
613 | BATU_VS \
614 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600615
Timur Tabi7a78f142007-01-31 15:54:29 -0600616/* PCI */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600617#ifdef CONFIG_PCI
Joe Hershberger396abba2011-10-11 23:57:15 -0500618#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500619 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500620 | BATL_MEMCOHERENCE)
621#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
622 | BATU_BL_256M \
623 | BATU_VS \
624 | BATU_VP)
625#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500626 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500627 | BATL_CACHEINHIBIT \
628 | BATL_GUARDEDSTORAGE)
629#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
630 | BATU_BL_256M \
631 | BATU_VS \
632 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600633#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200634#define CONFIG_SYS_IBAT1L 0
635#define CONFIG_SYS_IBAT1U 0
636#define CONFIG_SYS_IBAT2L 0
637#define CONFIG_SYS_IBAT2U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600638#endif
639
640#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger396abba2011-10-11 23:57:15 -0500641#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500642 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500643 | BATL_MEMCOHERENCE)
644#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
645 | BATU_BL_256M \
646 | BATU_VS \
647 | BATU_VP)
648#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500649 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500650 | BATL_CACHEINHIBIT \
651 | BATL_GUARDEDSTORAGE)
652#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
653 | BATU_BL_256M \
654 | BATU_VS \
655 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600656#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200657#define CONFIG_SYS_IBAT3L 0
658#define CONFIG_SYS_IBAT3U 0
659#define CONFIG_SYS_IBAT4L 0
660#define CONFIG_SYS_IBAT4U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600661#endif
662
663/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500664#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500665 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500666 | BATL_CACHEINHIBIT \
667 | BATL_GUARDEDSTORAGE)
668#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
669 | BATU_BL_256M \
670 | BATU_VS \
671 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600672
673/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500674#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500675 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500676 | BATL_MEMCOHERENCE \
677 | BATL_GUARDEDSTORAGE)
678#define CONFIG_SYS_IBAT6U (0xF0000000 \
679 | BATU_BL_256M \
680 | BATU_VS \
681 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600682
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200683#define CONFIG_SYS_IBAT7L 0
684#define CONFIG_SYS_IBAT7U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600685
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200686#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
687#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
688#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
689#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
690#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
691#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
692#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
693#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
694#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
695#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
696#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
697#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
698#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
699#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
700#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
701#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Timur Tabi2ad6b512006-10-31 18:44:42 -0600702
Jon Loeliger8ea54992007-07-04 22:30:06 -0500703#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600704#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600705#endif
706
Timur Tabi2ad6b512006-10-31 18:44:42 -0600707/*
708 * Environment Configuration
709 */
710#define CONFIG_ENV_OVERWRITE
711
Joe Hershberger396abba2011-10-11 23:57:15 -0500712#define CONFIG_NETDEV "eth0"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600713
Timur Tabi7a78f142007-01-31 15:54:29 -0600714#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500715#define CONFIG_HOSTNAME "mpc8349emitx"
Timur Tabi7a78f142007-01-31 15:54:29 -0600716#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500717#define CONFIG_HOSTNAME "mpc8349emitxgp"
Timur Tabi7a78f142007-01-31 15:54:29 -0600718#endif
719
720/* Default path and filenames */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000721#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000722#define CONFIG_BOOTFILE "uImage"
Joe Hershberger396abba2011-10-11 23:57:15 -0500723 /* U-Boot image on TFTP server */
724#define CONFIG_UBOOTPATH "u-boot.bin"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600725
Timur Tabi7a78f142007-01-31 15:54:29 -0600726#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500727#define CONFIG_FDTFILE "mpc8349emitx.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600728#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500729#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600730#endif
731
Timur Tabi7a78f142007-01-31 15:54:29 -0600732
Timur Tabi98883332006-10-31 19:14:41 -0600733#define CONFIG_BOOTARGS \
734 "root=/dev/nfs rw" \
Marek Vasut5368c552012-09-23 17:41:24 +0200735 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
736 " ip=" __stringify(CONFIG_IPADDR) ":" \
737 __stringify(CONFIG_SERVERIP) ":" \
738 __stringify(CONFIG_GATEWAYIP) ":" \
739 __stringify(CONFIG_NETMASK) ":" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500740 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
Marek Vasut5368c552012-09-23 17:41:24 +0200741 " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
Timur Tabi98883332006-10-31 19:14:41 -0600742
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100743#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200744 "console=" __stringify(CONFIG_CONSOLE) "\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500745 "netdev=" CONFIG_NETDEV "\0" \
746 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200747 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200748 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
749 " +$filesize; " \
750 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
751 " +$filesize; " \
752 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
753 " $filesize; " \
754 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
755 " +$filesize; " \
756 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
757 " $filesize\0" \
Kim Phillips05f91a62009-08-26 21:27:37 -0500758 "fdtaddr=780000\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500759 "fdtfile=" CONFIG_FDTFILE "\0"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600760
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100761#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600762 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500763 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
Timur Tabi7a78f142007-01-31 15:54:29 -0600764 " console=$console,$baudrate $othbootargs; " \
765 "tftp $loadaddr $bootfile;" \
766 "tftp $fdtaddr $fdtfile;" \
767 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600768
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100769#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600770 "setenv bootargs root=/dev/ram rw" \
771 " console=$console,$baudrate $othbootargs; " \
772 "tftp $ramdiskaddr $ramdiskfile;" \
773 "tftp $loadaddr $bootfile;" \
774 "tftp $fdtaddr $fdtfile;" \
775 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600776
Timur Tabi2ad6b512006-10-31 18:44:42 -0600777#endif