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Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi2ad6b512006-10-31 18:44:42 -06003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
Timur Tabi7a78f142007-01-31 15:54:29 -060024 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi2ad6b512006-10-31 18:44:42 -060025
26 Memory map:
27
28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi7a78f142007-01-31 15:54:29 -060034 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060035 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi7a78f142007-01-31 15:54:29 -060036 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060039
40 I2C address list:
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010041 Align. Board
42 Bus Addr Part No. Description Length Location
Timur Tabi2ad6b512006-10-31 18:44:42 -060043 ----------------------------------------------------------------
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010044 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi2ad6b512006-10-31 18:44:42 -060045
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010046 I2C1 0x20 PCF8574 I2C Expander 0 U8
47 I2C1 0x21 PCF8574 I2C Expander 0 U10
48 I2C1 0x38 PCF8574A I2C Expander 0 U8
49 I2C1 0x39 PCF8574A I2C Expander 0 U10
50 I2C1 0x51 (DDR) DDR EEPROM 1 U1
51 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi2ad6b512006-10-31 18:44:42 -060052
53 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
54*/
55
56#ifndef __CONFIG_H
57#define __CONFIG_H
58
Timur Tabi7a78f142007-01-31 15:54:29 -060059#if (TEXT_BASE == 0xFE000000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_LOWBOOT
Timur Tabi7a78f142007-01-31 15:54:29 -060061#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060062
63/*
64 * High Level Configuration Options
65 */
Peter Tyser2c7920a2009-05-22 17:23:25 -050066#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
Timur Tabi2ad6b512006-10-31 18:44:42 -060067#define CONFIG_MPC8349 /* MPC8349 specific */
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
Timur Tabi2ad6b512006-10-31 18:44:42 -060070
Timur Tabi89c77842008-02-08 13:15:55 -060071#define CONFIG_MISC_INIT_F
72#define CONFIG_MISC_INIT_R
Timur Tabi7a78f142007-01-31 15:54:29 -060073
Timur Tabi89c77842008-02-08 13:15:55 -060074/*
75 * On-board devices
76 */
Timur Tabi7a78f142007-01-31 15:54:29 -060077
78#ifdef CONFIG_MPC8349ITX
Timur Tabi2ad6b512006-10-31 18:44:42 -060079#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
Timur Tabi89c77842008-02-08 13:15:55 -060080#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +020081#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +030082#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
Timur Tabi7a78f142007-01-31 15:54:29 -060083#endif
84
85#define CONFIG_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -060086#define CONFIG_RTC_DS1337
Timur Tabi7a78f142007-01-31 15:54:29 -060087#define CONFIG_HARD_I2C
88#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
89
90/*
91 * Device configurations
92 */
Timur Tabi2ad6b512006-10-31 18:44:42 -060093
94/* I2C */
Timur Tabi2ad6b512006-10-31 18:44:42 -060095#ifdef CONFIG_HARD_I2C
96
Timur Tabibe5e6182006-11-03 19:15:00 -060097#define CONFIG_FSL_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -060098#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_I2C_OFFSET 0x3000
100#define CONFIG_SYS_I2C2_OFFSET 0x3100
101#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200102#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
105#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
106#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
107#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
108#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
109#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
Timur Tabibe5e6182006-11-03 19:15:00 -0600110#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
113#define CONFIG_SYS_I2C_SLAVE 0x7F
Timur Tabi2ad6b512006-10-31 18:44:42 -0600114
115/* Don't probe these addresses: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \
117 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
118 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
119 {1, CONFIG_SYS_I2C_8574A_ADDR2}}
Timur Tabi2ad6b512006-10-31 18:44:42 -0600120/* Bit definitions for the 8574[A] I2C expander */
121#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
122#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
123#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
124#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
125#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
126
127#undef CONFIG_SOFT_I2C
128
129#endif
130
Timur Tabi7a78f142007-01-31 15:54:29 -0600131/* Compact Flash */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600132#ifdef CONFIG_COMPACT_FLASH
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_IDE_MAXBUS 1
135#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
138#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
139#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
140#define CONFIG_SYS_ATA_REG_OFFSET 0
141#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
142#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600143
144#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
145
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200146#endif
147
148/*
149 * SATA
150 */
151#ifdef CONFIG_SATA_SIL3114
152
153#define CONFIG_SYS_SATA_MAX_DEVICE 4
154#define CONFIG_LIBATA
155#define CONFIG_LBA48
Timur Tabi2ad6b512006-10-31 18:44:42 -0600156
Timur Tabi7a78f142007-01-31 15:54:29 -0600157#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600158
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300159#ifdef CONFIG_SYS_USB_HOST
160/*
161 * Support USB
162 */
163#define CONFIG_CMD_USB
164#define CONFIG_USB_STORAGE
165#define CONFIG_USB_EHCI
166#define CONFIG_USB_EHCI_FSL
167
168/* Current USB implementation supports the only USB controller,
169 * so we have to choose between the MPH or the DR ones */
170#if 1
171#define CONFIG_HAS_FSL_MPH_USB
172#else
173#define CONFIG_HAS_FSL_DR_USB
174#endif
175
176#endif
177
Timur Tabi7a78f142007-01-31 15:54:29 -0600178/*
179 * DDR Setup
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
182#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
183#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
184#define CONFIG_SYS_83XX_DDR_USES_CS0
185#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
186#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi7a78f142007-01-31 15:54:29 -0600187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Joe D'Abbraccio507e2d72008-03-24 13:00:59 -0400189 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabif64702b2007-04-30 13:59:50 -0500190
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200191#define CONFIG_VERY_BIG_RAM
192#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
193
Timur Tabi7a78f142007-01-31 15:54:29 -0600194#ifdef CONFIG_HARD_I2C
195#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
196#endif
197
198#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
200 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
Timur Tabi7a78f142007-01-31 15:54:29 -0600201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
203 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi7a78f142007-01-31 15:54:29 -0600204#endif
205
206/*
207 *Flash on the Local Bus
208 */
209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200211#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
213#define CONFIG_SYS_FLASH_EMPTY_INFO
214#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
215#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
216#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
217#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi7a78f142007-01-31 15:54:29 -0600218
219/* The ITX has two flash chips, but the ITX-GP has only one. To support both
220boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_QUIET_TEST
222#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
223#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
224#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
225#define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
226#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Timur Tabi7a78f142007-01-31 15:54:29 -0600227
Timur Tabi89c77842008-02-08 13:15:55 -0600228/* Vitesse 7385 */
229
230#ifdef CONFIG_VSC7385_ENET
231
232#define CONFIG_TSEC2
233
234/* The flash address and size of the VSC7385 firmware image */
235#define CONFIG_VSC7385_IMAGE 0xFEFFE000
236#define CONFIG_VSC7385_IMAGE_SIZE 8192
237
238#endif
239
Timur Tabi7a78f142007-01-31 15:54:29 -0600240/*
241 * BRx, ORx, LBLAWBARx, and LBLAWARx
242 */
243
244/* Flash */
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
247#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400248 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
Timur Tabi7a78f142007-01-31 15:54:29 -0600249 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
251#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
Timur Tabi7a78f142007-01-31 15:54:29 -0600252
253/* Vitesse 7385 */
254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600256
Timur Tabi89c77842008-02-08 13:15:55 -0600257#ifdef CONFIG_VSC7385_ENET
258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
260#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
Timur Tabi7a78f142007-01-31 15:54:29 -0600261 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
262 OR_GPCM_EHTR | OR_GPCM_EAD)
263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
265#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600266
267#endif
268
269/* LED */
270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_LED_BASE 0xF9000000
272#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
273#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
Timur Tabi7a78f142007-01-31 15:54:29 -0600274 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
275 OR_GPCM_EHTR | OR_GPCM_EAD)
276
277/* Compact Flash */
278
279#ifdef CONFIG_COMPACT_FLASH
280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
284#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
Timur Tabi7a78f142007-01-31 15:54:29 -0600285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
287#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600288
289#endif
290
291/*
292 * U-Boot memory configuration
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
297#define CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600298#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#undef CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600300#endif
301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_INIT_RAM_LOCK
303#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
304#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
307#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
308#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi2ad6b512006-10-31 18:44:42 -0600309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kim Phillips4a9932a2009-07-07 18:04:21 -0500311#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600313
314/*
315 * Local Bus LCRR and LBCR regs
316 * LCRR: DLL bypass, Clock divider is 4
317 * External Local Bus rate is
318 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
321#define CONFIG_SYS_LBC_LBCR 0x00000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
324#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600325
326/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600327 * Serial Port
328 */
329#define CONFIG_CONS_INDEX 1
330#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_NS16550
332#define CONFIG_SYS_NS16550_SERIAL
333#define CONFIG_SYS_NS16550_REG_SIZE 1
334#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_BAUDRATE_TABLE \
Timur Tabi7a78f142007-01-31 15:54:29 -0600337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
338
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400339#define CONFIG_CONSOLE ttyS0
Timur Tabi7a78f142007-01-31 15:54:29 -0600340#define CONFIG_BAUDRATE 115200
Timur Tabi2ad6b512006-10-31 18:44:42 -0600341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
343#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600344
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600345/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500346#define CONFIG_OF_LIBFDT 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600347#define CONFIG_OF_BOARD_SETUP 1
348#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600349
Timur Tabi7a78f142007-01-31 15:54:29 -0600350/*
351 * PCI
352 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600353#ifdef CONFIG_PCI
354
355#define CONFIG_MPC83XX_PCI2
356
357/*
358 * General PCI
359 * Addresses are mapped 1-1.
360 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
362#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
363#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
364#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
365#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
366#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
367#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
368#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
369#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600370
371#ifdef CONFIG_MPC83XX_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
373#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
374#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
375#define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
376#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
377#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
378#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
379#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
380#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600381#endif
382
Timur Tabi2ad6b512006-10-31 18:44:42 -0600383#define CONFIG_NET_MULTI
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100384#define CONFIG_PCI_PNP /* do pci plug-and-play */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600385
Timur Tabi2ad6b512006-10-31 18:44:42 -0600386#ifndef CONFIG_PCI_PNP
387 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600389 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
390#endif
391
392#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
393
394#endif
395
Timur Tabi7a78f142007-01-31 15:54:29 -0600396#define PCI_66M
397#ifdef PCI_66M
398#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
399#else
400#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
401#endif
402
Timur Tabi2ad6b512006-10-31 18:44:42 -0600403/* TSEC */
404
405#ifdef CONFIG_TSEC_ENET
406
Timur Tabi2ad6b512006-10-31 18:44:42 -0600407#define CONFIG_NET_MULTI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600408#define CONFIG_MII
Jon Loeliger659e2f62007-07-10 09:10:49 -0500409#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600410
Kim Phillips255a35772007-05-16 16:52:19 -0500411#define CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600412
Kim Phillips255a35772007-05-16 16:52:19 -0500413#ifdef CONFIG_TSEC1
Andy Fleming10327dc2007-08-16 16:35:02 -0500414#define CONFIG_HAS_ETH0
Kim Phillips255a35772007-05-16 16:52:19 -0500415#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100417#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600418#define TSEC1_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500419#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600420#endif
421
Kim Phillips255a35772007-05-16 16:52:19 -0500422#ifdef CONFIG_TSEC2
Timur Tabi7a78f142007-01-31 15:54:29 -0600423#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500424#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600426
Timur Tabi2ad6b512006-10-31 18:44:42 -0600427#define TSEC2_PHY_ADDR 4
428#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500429#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600430#endif
431
432#define CONFIG_ETHPRIME "Freescale TSEC"
433
434#endif
435
Timur Tabi2ad6b512006-10-31 18:44:42 -0600436/*
437 * Environment
438 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600439#define CONFIG_ENV_OVERWRITE
440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200442 #define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200444 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
445 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600446#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200448 #undef CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200449 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200451 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600452#endif
453
454#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600456
Jon Loeliger8ea54992007-07-04 22:30:06 -0500457/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500458 * BOOTP options
459 */
460#define CONFIG_BOOTP_BOOTFILESIZE
461#define CONFIG_BOOTP_BOOTPATH
462#define CONFIG_BOOTP_GATEWAY
463#define CONFIG_BOOTP_HOSTNAME
464
465
466/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500467 * Command line configuration.
468 */
469#include <config_cmd_default.h>
470
471#define CONFIG_CMD_CACHE
472#define CONFIG_CMD_DATE
473#define CONFIG_CMD_IRQ
474#define CONFIG_CMD_NET
475#define CONFIG_CMD_PING
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200476#define CONFIG_CMD_DHCP
Jon Loeliger8ea54992007-07-04 22:30:06 -0500477#define CONFIG_CMD_SDRAM
Timur Tabi2ad6b512006-10-31 18:44:42 -0600478
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300479#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
480 || defined(CONFIG_USB_STORAGE)
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200481 #define CONFIG_DOS_PARTITION
482 #define CONFIG_CMD_FAT
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300483 #define CONFIG_SUPPORT_VFAT
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200484#endif
485
Timur Tabi2ad6b512006-10-31 18:44:42 -0600486#ifdef CONFIG_COMPACT_FLASH
Jon Loeliger8ea54992007-07-04 22:30:06 -0500487 #define CONFIG_CMD_IDE
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200488#endif
489
490#ifdef CONFIG_SATA_SIL3114
491 #define CONFIG_CMD_SATA
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300492#endif
493
494#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200495 #define CONFIG_CMD_EXT2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600496#endif
497
498#ifdef CONFIG_PCI
Jon Loeliger8ea54992007-07-04 22:30:06 -0500499 #define CONFIG_CMD_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600500#endif
501
502#ifdef CONFIG_HARD_I2C
Jon Loeliger8ea54992007-07-04 22:30:06 -0500503 #define CONFIG_CMD_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -0600504#endif
505
Timur Tabi2ad6b512006-10-31 18:44:42 -0600506/* Watchdog */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600507#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600508
509/*
510 * Miscellaneous configurable options
511 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_LONGHELP /* undef to save memory */
Timur Tabi7a78f142007-01-31 15:54:29 -0600513#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
515#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Timur Tabi7a78f142007-01-31 15:54:29 -0600516
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips05f91a62009-08-26 21:27:37 -0500518#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Timur Tabi7a78f142007-01-31 15:54:29 -0600519
520#ifdef CONFIG_MPC8349ITX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600522#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600524#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600525
Jon Loeliger8ea54992007-07-04 22:30:06 -0500526#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600528#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600530#endif
531
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
533#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
534#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
535#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600536
537/*
538 * For booting Linux, the board info and command line data
539 * have to be in the first 8 MB of memory, since this is
540 * the maximum mapped by the Linux kernel during initialization.
541 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600543
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_HRCW_LOW (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600545 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
546 HRCWL_DDR_TO_SCB_CLK_1X1 |\
547 HRCWL_CSB_TO_CLKIN_4X1 |\
548 HRCWL_VCO_1X2 |\
549 HRCWL_CORE_TO_CSB_2X1)
550
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200551#ifdef CONFIG_SYS_LOWBOOT
552#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600553 HRCWH_PCI_HOST |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600554 HRCWH_32_BIT_PCI |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600555 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600556 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600557 HRCWH_CORE_ENABLE |\
558 HRCWH_FROM_0X00000100 |\
559 HRCWH_BOOTSEQ_DISABLE |\
560 HRCWH_SW_WATCHDOG_DISABLE |\
561 HRCWH_ROM_LOC_LOCAL_16BIT |\
562 HRCWH_TSEC1M_IN_GMII |\
563 HRCWH_TSEC2M_IN_GMII )
564#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600566 HRCWH_PCI_HOST |\
567 HRCWH_32_BIT_PCI |\
568 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600569 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600570 HRCWH_CORE_ENABLE |\
571 HRCWH_FROM_0XFFF00100 |\
572 HRCWH_BOOTSEQ_DISABLE |\
573 HRCWH_SW_WATCHDOG_DISABLE |\
574 HRCWH_ROM_LOC_LOCAL_16BIT |\
575 HRCWH_TSEC1M_IN_GMII |\
576 HRCWH_TSEC2M_IN_GMII )
577#endif
578
Timur Tabi7a78f142007-01-31 15:54:29 -0600579/*
580 * System performance
581 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200582#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
583#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
584#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
585#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
586#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
587#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300588#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
589#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600590
Timur Tabi7a78f142007-01-31 15:54:29 -0600591/*
592 * System IO Config
593 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200594#define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300595#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600596
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#define CONFIG_SYS_HID0_INIT 0x000000000
598#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600599
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500601#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600602
Timur Tabi7a78f142007-01-31 15:54:29 -0600603/* DDR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
605#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600606
Timur Tabi7a78f142007-01-31 15:54:29 -0600607/* PCI */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600608#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
610#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
611#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
612#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600613#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_IBAT1L 0
615#define CONFIG_SYS_IBAT1U 0
616#define CONFIG_SYS_IBAT2L 0
617#define CONFIG_SYS_IBAT2U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600618#endif
619
620#ifdef CONFIG_MPC83XX_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200621#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
622#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
623#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
624#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600625#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_IBAT3L 0
627#define CONFIG_SYS_IBAT3U 0
628#define CONFIG_SYS_IBAT4L 0
629#define CONFIG_SYS_IBAT4U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600630#endif
631
632/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
634#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600635
636/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Scott Woodc1230982009-03-31 17:49:36 -0500637#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
638 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200639#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600640
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200641#define CONFIG_SYS_IBAT7L 0
642#define CONFIG_SYS_IBAT7U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600643
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200644#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
645#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
646#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
647#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
648#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
649#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
650#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
651#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
652#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
653#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
654#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
655#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
656#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
657#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
658#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
659#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Timur Tabi2ad6b512006-10-31 18:44:42 -0600660
661/*
662 * Internal Definitions
663 *
664 * Boot Flags
665 */
666#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
667#define BOOTFLAG_WARM 0x02 /* Software reboot */
668
Jon Loeliger8ea54992007-07-04 22:30:06 -0500669#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600670#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
671#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
672#endif
673
674
675/*
676 * Environment Configuration
677 */
678#define CONFIG_ENV_OVERWRITE
679
Timur Tabi89c77842008-02-08 13:15:55 -0600680#ifdef CONFIG_HAS_ETH0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600681#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
682#endif
683
Timur Tabi89c77842008-02-08 13:15:55 -0600684#ifdef CONFIG_HAS_ETH1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600685#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
686#endif
687
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600688#define CONFIG_IPADDR 192.168.1.253
689#define CONFIG_SERVERIP 192.168.1.1
690#define CONFIG_GATEWAYIP 192.168.1.1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600691#define CONFIG_NETMASK 255.255.252.0
Timur Tabi98883332006-10-31 19:14:41 -0600692#define CONFIG_NETDEV eth0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600693
Timur Tabi7a78f142007-01-31 15:54:29 -0600694#ifdef CONFIG_MPC8349ITX
Timur Tabi2ad6b512006-10-31 18:44:42 -0600695#define CONFIG_HOSTNAME mpc8349emitx
Timur Tabi7a78f142007-01-31 15:54:29 -0600696#else
697#define CONFIG_HOSTNAME mpc8349emitxgp
698#endif
699
700/* Default path and filenames */
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600701#define CONFIG_ROOTPATH /nfsroot/rootfs
702#define CONFIG_BOOTFILE uImage
Timur Tabi7a78f142007-01-31 15:54:29 -0600703#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600704
Timur Tabi7a78f142007-01-31 15:54:29 -0600705#ifdef CONFIG_MPC8349ITX
706#define CONFIG_FDTFILE mpc8349emitx.dtb
Timur Tabi2ad6b512006-10-31 18:44:42 -0600707#else
Timur Tabi7a78f142007-01-31 15:54:29 -0600708#define CONFIG_FDTFILE mpc8349emitxgp.dtb
Timur Tabi2ad6b512006-10-31 18:44:42 -0600709#endif
710
Kim Phillips05f91a62009-08-26 21:27:37 -0500711#define CONFIG_BOOTDELAY 6
Timur Tabi7a78f142007-01-31 15:54:29 -0600712
Timur Tabi2ad6b512006-10-31 18:44:42 -0600713#define XMK_STR(x) #x
714#define MK_STR(x) XMK_STR(x)
715
Timur Tabi98883332006-10-31 19:14:41 -0600716#define CONFIG_BOOTARGS \
717 "root=/dev/nfs rw" \
718 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200719 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
Timur Tabi98883332006-10-31 19:14:41 -0600720 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
721 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400722 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
Timur Tabi98883332006-10-31 19:14:41 -0600723
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100724#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200725 "console=" MK_STR(CONFIG_CONSOLE) "\0" \
726 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
727 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
728 "tftpflash=tftpboot $loadaddr $uboot; " \
729 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
730 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
731 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
732 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
733 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
Kim Phillips05f91a62009-08-26 21:27:37 -0500734 "fdtaddr=780000\0" \
Timur Tabi7a78f142007-01-31 15:54:29 -0600735 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600736
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100737#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600738 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
739 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
740 " console=$console,$baudrate $othbootargs; " \
741 "tftp $loadaddr $bootfile;" \
742 "tftp $fdtaddr $fdtfile;" \
743 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600744
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100745#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600746 "setenv bootargs root=/dev/ram rw" \
747 " console=$console,$baudrate $othbootargs; " \
748 "tftp $ramdiskaddr $ramdiskfile;" \
749 "tftp $loadaddr $bootfile;" \
750 "tftp $fdtaddr $fdtfile;" \
751 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600752
753#undef MK_STR
754#undef XMK_STR
755
756#endif