Timur Tabi | 2ad6b51 | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | MPC8349E-mITX board configuration file |
| 25 | |
| 26 | Memory map: |
| 27 | |
| 28 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) |
| 29 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) |
| 30 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) |
| 31 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) |
| 32 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) |
| 33 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) |
| 34 | 0xF000_0000-0xF000_FFFF Compact Flash |
| 35 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
| 36 | 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 |
| 37 | 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) |
| 38 | 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) |
| 39 | |
| 40 | I2C address list: |
| 41 | Align. Board |
| 42 | Bus Addr Part No. Description Length Location |
| 43 | ---------------------------------------------------------------- |
| 44 | I2C1 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
| 45 | |
| 46 | I2C2 0x20 PCF8574 I2C Expander 0 U8 |
| 47 | I2C2 0x21 PCF8574 I2C Expander 0 U10 |
| 48 | I2C2 0x38 PCF8574A I2C Expander 0 U8 |
| 49 | I2C2 0x39 PCF8574A I2C Expander 0 U10 |
| 50 | I2C2 0x51 (DDR) DDR EEPROM 1 U1 |
| 51 | I2C2 0x68 DS1339 RTC 1 U68 |
| 52 | |
| 53 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. |
| 54 | */ |
| 55 | |
| 56 | #ifndef __CONFIG_H |
| 57 | #define __CONFIG_H |
| 58 | |
| 59 | #undef DEBUG |
| 60 | |
| 61 | /* |
| 62 | * High Level Configuration Options |
| 63 | */ |
| 64 | #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ |
| 65 | #define CONFIG_MPC8349 /* MPC8349 specific */ |
| 66 | |
| 67 | #define CONFIG_PCI |
| 68 | |
| 69 | #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ |
| 70 | #define CONFIG_RTC_DS1337 |
| 71 | |
| 72 | /* I2C */ |
| 73 | #define CONFIG_HARD_I2C |
| 74 | |
| 75 | #ifdef CONFIG_HARD_I2C |
| 76 | |
| 77 | #define CONFIG_MISC_INIT_F |
| 78 | #define CONFIG_MISC_INIT_R |
| 79 | |
| 80 | #define CONFIG_I2C_MULTI_BUS |
| 81 | #define CONFIG_I2C_CMD_TREE |
| 82 | #define CFG_I2C_OFFSET 0x3000 |
| 83 | #define CFG_I2C2_OFFSET 0x3100 |
| 84 | #define CFG_SPD_BUS_NUM I2C_2 |
| 85 | |
| 86 | #define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */ |
| 87 | #define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */ |
| 88 | #define CFG_I2C_8574A_ADDR1 0x38 /* I2C2, PCF8574A */ |
| 89 | #define CFG_I2C_8574A_ADDR2 0x39 /* I2C2, PCF8574A */ |
| 90 | #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C1, Board EEPROM */ |
| 91 | #define CFG_I2C_RTC_ADDR 0x68 /* I2C2, DS1339 RTC*/ |
| 92 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C2, DDR */ |
| 93 | |
| 94 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 95 | #define CFG_I2C_SLAVE 0x7F |
| 96 | |
| 97 | /* Don't probe these addresses: */ |
| 98 | #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ |
| 99 | {1, CFG_I2C_8574_ADDR2}, \ |
| 100 | {1, CFG_I2C_8574A_ADDR1}, \ |
| 101 | {1, CFG_I2C_8574A_ADDR2}} |
| 102 | /* Bit definitions for the 8574[A] I2C expander */ |
| 103 | #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
| 104 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
| 105 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ |
| 106 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ |
| 107 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ |
| 108 | |
| 109 | #undef CONFIG_SOFT_I2C |
| 110 | |
| 111 | #endif |
| 112 | |
| 113 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 114 | #define CONFIG_ENV_OVERWRITE |
| 115 | |
| 116 | #define PCI_66M |
| 117 | #ifdef PCI_66M |
| 118 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
| 119 | #else |
| 120 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
| 121 | #endif |
| 122 | |
| 123 | #ifndef CONFIG_SYS_CLK_FREQ |
| 124 | #ifdef PCI_66M |
| 125 | #define CONFIG_SYS_CLK_FREQ 66666666 |
| 126 | #else |
| 127 | #define CONFIG_SYS_CLK_FREQ 33333333 |
| 128 | #endif |
| 129 | #endif |
| 130 | |
| 131 | #define CFG_IMMRBAR 0xE0000000 /* The IMMR is relocated to here */ |
| 132 | |
| 133 | #undef CFG_DRAM_TEST /* memory test, takes time */ |
| 134 | #define CFG_MEMTEST_START 0x00003000 /* memtest region */ |
| 135 | #define CFG_MEMTEST_END 0x07100000 /* only has 128M */ |
| 136 | |
| 137 | /* |
| 138 | * DDR Setup |
| 139 | */ |
| 140 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 141 | #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
| 142 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
| 143 | |
| 144 | /* |
| 145 | * 32-bit data path mode. |
| 146 | * |
| 147 | * Please note that using this mode for devices with the real density of 64-bit |
| 148 | * effectively reduces the amount of available memory due to the effect of |
| 149 | * wrapping around while translating address to row/columns, for example in the |
| 150 | * 256MB module the upper 128MB get aliased with contents of the lower |
| 151 | * 128MB); normally this define should be used for devices with real 32-bit |
| 152 | * data path. |
| 153 | */ |
| 154 | #undef CONFIG_DDR_32BIT |
| 155 | |
| 156 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 157 | #define CFG_SDRAM_BASE CFG_DDR_BASE |
| 158 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
| 159 | #undef CONFIG_DDR_2T_TIMING |
| 160 | #define CFG_83XX_DDR_USES_CS0 |
| 161 | |
| 162 | #ifndef CONFIG_SPD_EEPROM |
| 163 | /* |
| 164 | * Manually set up DDR parameters |
| 165 | */ |
| 166 | #define CFG_DDR_SIZE 256 /* Mb */ |
| 167 | #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
| 168 | |
| 169 | #define CFG_DDR_TIMING_1 0x26242321 |
| 170 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ |
| 171 | #endif |
| 172 | |
| 173 | /* FLASH on the Local Bus */ |
| 174 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ |
| 175 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| 176 | #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ |
| 177 | #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ |
| 178 | |
| 179 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) |
| 180 | #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
| 181 | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ |
| 182 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
| 183 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
| 184 | #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ |
| 185 | |
| 186 | /* VSC7385 on the Local Bus */ |
| 187 | #define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ |
| 188 | |
| 189 | #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) |
| 190 | #define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ |
| 191 | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ |
| 192 | OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
| 193 | |
| 194 | #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ |
| 195 | #define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ |
| 196 | |
| 197 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ |
| 198 | #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ |
| 199 | |
| 200 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} |
| 201 | |
| 202 | #undef CFG_FLASH_CHECKSUM |
| 203 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 204 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 205 | |
| 206 | #define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ |
| 207 | #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) |
| 208 | #define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ |
| 209 | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ |
| 210 | OR_GPCM_SCY_9 | \ |
| 211 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
| 212 | |
| 213 | #ifdef CONFIG_COMPACT_FLASH |
| 214 | |
| 215 | #define CFG_CF_BASE 0xF0000000 |
| 216 | |
| 217 | #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) |
| 218 | #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) |
| 219 | |
| 220 | #define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ |
| 221 | #define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ |
| 222 | |
| 223 | #undef CONFIG_IDE_RESET |
| 224 | #undef CONFIG_IDE_PREINIT |
| 225 | |
| 226 | #define CFG_IDE_MAXBUS 1 |
| 227 | #define CFG_IDE_MAXDEVICE 1 |
| 228 | |
| 229 | #define CFG_ATA_IDE0_OFFSET 0x0000 |
| 230 | #define CFG_ATA_BASE_ADDR CFG_CF_BASE |
| 231 | #define CFG_ATA_DATA_OFFSET 0x0000 |
| 232 | #define CFG_ATA_REG_OFFSET 0 |
| 233 | #define CFG_ATA_ALT_OFFSET 0x0200 |
| 234 | #define CFG_ATA_STRIDE 2 |
| 235 | |
| 236 | #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ |
| 237 | |
| 238 | #endif |
| 239 | |
| 240 | #define CONFIG_DOS_PARTITION |
| 241 | |
| 242 | #define CFG_MID_FLASH_JUMP 0x7F000000 |
| 243 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 244 | |
| 245 | |
| 246 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 247 | #define CFG_RAMBOOT |
| 248 | #else |
| 249 | #undef CFG_RAMBOOT |
| 250 | #endif |
| 251 | |
| 252 | #define CONFIG_L1_INIT_RAM |
| 253 | #define CFG_INIT_RAM_LOCK |
| 254 | #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
| 255 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
| 256 | |
| 257 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
| 258 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 259 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 260 | |
| 261 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 262 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
| 263 | |
| 264 | /* |
| 265 | * Local Bus LCRR and LBCR regs |
| 266 | * LCRR: DLL bypass, Clock divider is 4 |
| 267 | * External Local Bus rate is |
| 268 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
| 269 | */ |
| 270 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
| 271 | #define CFG_LBC_LBCR 0x00000000 |
| 272 | |
| 273 | #undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ |
| 274 | |
| 275 | #ifdef CFG_LB_SDRAM |
| 276 | /*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ |
| 277 | /* |
| 278 | * Base Register 2 and Option Register 2 configure SDRAM. |
| 279 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
| 280 | * |
| 281 | * For BR2, need: |
| 282 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 283 | * port-size = 32-bits = BR2[19:20] = 11 |
| 284 | * no parity checking = BR2[21:22] = 00 |
| 285 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 286 | * Valid = BR[31] = 1 |
| 287 | * |
| 288 | * 0 4 8 12 16 20 24 28 |
| 289 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 |
| 290 | */ |
| 291 | |
| 292 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| 293 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
| 294 | |
| 295 | #define CFG_LBLAWBAR2_PRELIM 0xF0000000 |
| 296 | #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ |
| 297 | |
| 298 | #define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) |
| 299 | #define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ |
| 300 | OR_SDRAM_XAM | \ |
| 301 | ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ |
| 302 | ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ |
| 303 | OR_SDRAM_EAD) |
| 304 | |
| 305 | #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
| 306 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ |
| 307 | |
| 308 | /* |
| 309 | * LSDMR masks |
| 310 | */ |
| 311 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
| 312 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
| 313 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
| 314 | #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) |
| 315 | #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) |
| 316 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
| 317 | #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) |
| 318 | #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) |
| 319 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
| 320 | #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) |
| 321 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
| 322 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
| 323 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
| 324 | #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) |
| 325 | #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) |
| 326 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
| 327 | #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) |
| 328 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
| 329 | |
| 330 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
| 331 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
| 332 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
| 333 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
| 334 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
| 335 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
| 336 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
| 337 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
| 338 | |
| 339 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ |
| 340 | | CFG_LBC_LSDMR_BSMA1516 \ |
| 341 | | CFG_LBC_LSDMR_RFCR8 \ |
| 342 | | CFG_LBC_LSDMR_PRETOACT6 \ |
| 343 | | CFG_LBC_LSDMR_ACTTORW3 \ |
| 344 | | CFG_LBC_LSDMR_BL8 \ |
| 345 | | CFG_LBC_LSDMR_WRC3 \ |
| 346 | | CFG_LBC_LSDMR_CL3 \ |
| 347 | ) |
| 348 | |
| 349 | /* |
| 350 | * SDRAM Controller configuration sequence. |
| 351 | */ |
| 352 | #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
| 353 | | CFG_LBC_LSDMR_OP_PCHALL) |
| 354 | #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
| 355 | | CFG_LBC_LSDMR_OP_ARFRSH) |
| 356 | #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
| 357 | | CFG_LBC_LSDMR_OP_ARFRSH) |
| 358 | #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
| 359 | | CFG_LBC_LSDMR_OP_MRW) |
| 360 | #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
| 361 | | CFG_LBC_LSDMR_OP_NORMAL) |
| 362 | #endif |
| 363 | |
| 364 | /* |
| 365 | * Serial Port |
| 366 | */ |
| 367 | #define CONFIG_CONS_INDEX 1 |
| 368 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 369 | #define CFG_NS16550 |
| 370 | #define CFG_NS16550_SERIAL |
| 371 | #define CFG_NS16550_REG_SIZE 1 |
| 372 | #define CFG_NS16550_CLK get_bus_freq(0) |
| 373 | |
| 374 | #define CFG_BAUDRATE_TABLE \ |
| 375 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 376 | |
| 377 | #define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) |
| 378 | #define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) |
| 379 | |
| 380 | /* Use the HUSH parser */ |
| 381 | #define CFG_HUSH_PARSER |
| 382 | #ifdef CFG_HUSH_PARSER |
| 383 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 384 | #endif |
| 385 | |
| 386 | |
| 387 | #ifdef CONFIG_PCI |
| 388 | |
| 389 | #define CONFIG_MPC83XX_PCI2 |
| 390 | |
| 391 | /* |
| 392 | * General PCI |
| 393 | * Addresses are mapped 1-1. |
| 394 | */ |
| 395 | #define CFG_PCI1_MEM_BASE 0x80000000 |
| 396 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
| 397 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
| 398 | #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) |
| 399 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE |
| 400 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
| 401 | #define CFG_PCI1_IO_BASE 0x00000000 |
| 402 | #define CFG_PCI1_IO_PHYS 0xE2000000 |
| 403 | #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ |
| 404 | |
| 405 | #ifdef CONFIG_MPC83XX_PCI2 |
| 406 | #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) |
| 407 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
| 408 | #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
| 409 | #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) |
| 410 | #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE |
| 411 | #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ |
| 412 | #define CFG_PCI2_IO_BASE 0x00000000 |
| 413 | #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) |
| 414 | #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ |
| 415 | #endif |
| 416 | |
| 417 | #define _IO_BASE 0x00000000 /* points to PCI I/O space */ |
| 418 | |
| 419 | #define CONFIG_NET_MULTI |
| 420 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 421 | |
| 422 | #ifdef CONFIG_RTL8139 |
| 423 | /* This macro is used by RTL8139 but not defined in PPC architecture */ |
| 424 | #define KSEG1ADDR(x) (x) |
| 425 | #endif |
| 426 | |
| 427 | #ifndef CONFIG_PCI_PNP |
| 428 | #define PCI_ENET0_IOADDR 0x00000000 |
| 429 | #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE |
| 430 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
| 431 | #endif |
| 432 | |
| 433 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 434 | |
| 435 | #endif |
| 436 | |
| 437 | /* TSEC */ |
| 438 | |
| 439 | #ifdef CONFIG_TSEC_ENET |
| 440 | |
| 441 | #ifndef CONFIG_NET_MULTI |
| 442 | #define CONFIG_NET_MULTI |
| 443 | #endif |
| 444 | |
| 445 | #define CONFIG_MII |
| 446 | #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ |
| 447 | |
| 448 | #define CONFIG_MPC83XX_TSEC1 |
| 449 | |
| 450 | #ifdef CONFIG_MPC83XX_TSEC1 |
| 451 | #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" |
| 452 | #define CFG_TSEC1_OFFSET 0x24000 |
| 453 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
| 454 | #define TSEC1_PHYIDX 0 |
| 455 | #endif |
| 456 | |
| 457 | #ifdef CONFIG_MPC83XX_TSEC2 |
| 458 | #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
| 459 | #define CFG_TSEC2_OFFSET 0x25000 |
| 460 | #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ |
| 461 | #define TSEC2_PHY_ADDR 4 |
| 462 | #define TSEC2_PHYIDX 0 |
| 463 | #endif |
| 464 | |
| 465 | #define CONFIG_ETHPRIME "Freescale TSEC" |
| 466 | |
| 467 | #endif |
| 468 | |
| 469 | |
| 470 | /* |
| 471 | * Environment |
| 472 | */ |
| 473 | #ifndef CFG_RAMBOOT |
| 474 | #define CFG_ENV_IS_IN_FLASH |
| 475 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
| 476 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 477 | #define CFG_ENV_SIZE 0x2000 |
| 478 | #else |
| 479 | #define CFG_NO_FLASH /* Flash is not usable now */ |
| 480 | #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
| 481 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
| 482 | #define CFG_ENV_SIZE 0x2000 |
| 483 | #endif |
| 484 | |
| 485 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 486 | #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 487 | |
| 488 | /* CONFIG_COMMANDS */ |
| 489 | |
| 490 | #ifdef CONFIG_COMPACT_FLASH |
| 491 | #define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) |
| 492 | #else |
| 493 | #define CONFIG_COMMANDS_CF 0 |
| 494 | #endif |
| 495 | |
| 496 | #ifdef CONFIG_PCI |
| 497 | #define CONFIG_COMMANDS_PCI CFG_CMD_PCI |
| 498 | #else |
| 499 | #define CONFIG_COMMANDS_PCI 0 |
| 500 | #endif |
| 501 | |
| 502 | #ifdef CONFIG_HARD_I2C |
| 503 | #define CONFIG_COMMANDS_I2C CFG_CMD_I2C |
| 504 | #else |
| 505 | #define CONFIG_COMMANDS_I2C 0 |
| 506 | #endif |
| 507 | |
| 508 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
| 509 | CONFIG_COMMANDS_CF | \ |
| 510 | CFG_CMD_NET | \ |
| 511 | CFG_CMD_PING | \ |
| 512 | CONFIG_COMMANDS_I2C | \ |
| 513 | CONFIG_COMMANDS_PCI | \ |
| 514 | CFG_CMD_SDRAM | \ |
| 515 | CFG_CMD_DATE | \ |
| 516 | CFG_CMD_CACHE | \ |
| 517 | CFG_CMD_IRQ) |
| 518 | #include <cmd_confdefs.h> |
| 519 | |
| 520 | /* Watchdog */ |
| 521 | |
| 522 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 523 | #ifdef CONFIG_WATCHDOG |
| 524 | #define CFG_WATCHDOG_VALUE 0xFFFFFFC3 |
| 525 | #endif |
| 526 | |
| 527 | /* |
| 528 | * Miscellaneous configurable options |
| 529 | */ |
| 530 | #define CFG_LONGHELP /* undef to save memory */ |
| 531 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
| 532 | #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ |
| 533 | |
| 534 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 535 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 536 | #else |
| 537 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 538 | #endif |
| 539 | |
| 540 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ |
| 541 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 542 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 543 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 544 | |
| 545 | /* |
| 546 | * For booting Linux, the board info and command line data |
| 547 | * have to be in the first 8 MB of memory, since this is |
| 548 | * the maximum mapped by the Linux kernel during initialization. |
| 549 | */ |
| 550 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 551 | |
| 552 | /* Cache Configuration */ |
| 553 | #define CFG_DCACHE_SIZE 32768 |
| 554 | #define CFG_CACHELINE_SIZE 32 |
| 555 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 556 | #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ |
| 557 | #endif |
| 558 | |
| 559 | #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
| 560 | |
| 561 | #define CFG_HRCW_LOW (\ |
| 562 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 563 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ |
| 564 | HRCWL_CSB_TO_CLKIN_4X1 |\ |
| 565 | HRCWL_VCO_1X2 |\ |
| 566 | HRCWL_CORE_TO_CSB_2X1) |
| 567 | |
| 568 | #ifdef PCI_64BIT |
| 569 | #define CFG_HRCW_HIGH (\ |
| 570 | HRCWH_PCI_HOST |\ |
| 571 | HRCWH_64_BIT_PCI |\ |
| 572 | HRCWH_PCI1_ARBITER_ENABLE |\ |
| 573 | HRCWH_PCI2_ARBITER_DISABLE |\ |
| 574 | HRCWH_CORE_ENABLE |\ |
| 575 | HRCWH_FROM_0X00000100 |\ |
| 576 | HRCWH_BOOTSEQ_DISABLE |\ |
| 577 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 578 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 579 | HRCWH_TSEC1M_IN_GMII |\ |
| 580 | HRCWH_TSEC2M_IN_GMII ) |
| 581 | #else |
| 582 | #define CFG_HRCW_HIGH (\ |
| 583 | HRCWH_PCI_HOST |\ |
| 584 | HRCWH_32_BIT_PCI |\ |
| 585 | HRCWH_PCI1_ARBITER_ENABLE |\ |
| 586 | HRCWH_PCI2_ARBITER_DISABLE |\ |
| 587 | HRCWH_CORE_ENABLE |\ |
| 588 | HRCWH_FROM_0XFFF00100 |\ |
| 589 | HRCWH_BOOTSEQ_DISABLE |\ |
| 590 | HRCWH_SW_WATCHDOG_DISABLE |\ |
| 591 | HRCWH_ROM_LOC_LOCAL_16BIT |\ |
| 592 | HRCWH_TSEC1M_IN_GMII |\ |
| 593 | HRCWH_TSEC2M_IN_GMII ) |
| 594 | #endif |
| 595 | |
| 596 | /* System performance */ |
| 597 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
| 598 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
| 599 | #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
| 600 | #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ |
| 601 | #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ |
| 602 | #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C1 clock mode (0-3) */ |
| 603 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ |
| 604 | |
| 605 | /* System IO Config */ |
| 606 | #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ |
Timur Tabi | 9888333 | 2006-10-31 19:14:41 -0600 | [diff] [blame^] | 607 | #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) |
Timur Tabi | 2ad6b51 | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 608 | |
| 609 | #define CFG_HID0_INIT 0x000000000 |
| 610 | |
| 611 | #define CFG_HID0_FINAL CFG_HID0_INIT |
| 612 | |
| 613 | #define CFG_HID2 HID2_HBE |
| 614 | |
| 615 | /* DDR @ 0x00000000 */ |
| 616 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 617 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 618 | |
| 619 | /* PCI @ 0x80000000 */ |
| 620 | #ifdef CONFIG_PCI |
| 621 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 622 | #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 623 | #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 624 | #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 625 | #else |
| 626 | #define CFG_IBAT1L 0 |
| 627 | #define CFG_IBAT1U 0 |
| 628 | #define CFG_IBAT2L 0 |
| 629 | #define CFG_IBAT2U 0 |
| 630 | #endif |
| 631 | |
| 632 | #ifdef CONFIG_MPC83XX_PCI2 |
| 633 | #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 634 | #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 635 | #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 636 | #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 637 | #else |
| 638 | #define CFG_IBAT3L 0 |
| 639 | #define CFG_IBAT3U 0 |
| 640 | #define CFG_IBAT4L 0 |
| 641 | #define CFG_IBAT4U 0 |
| 642 | #endif |
| 643 | |
| 644 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
| 645 | #define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 646 | #define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) |
| 647 | |
| 648 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
| 649 | #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 650 | #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 651 | |
| 652 | #define CFG_IBAT7L 0 |
| 653 | #define CFG_IBAT7U 0 |
| 654 | |
| 655 | #define CFG_DBAT0L CFG_IBAT0L |
| 656 | #define CFG_DBAT0U CFG_IBAT0U |
| 657 | #define CFG_DBAT1L CFG_IBAT1L |
| 658 | #define CFG_DBAT1U CFG_IBAT1U |
| 659 | #define CFG_DBAT2L CFG_IBAT2L |
| 660 | #define CFG_DBAT2U CFG_IBAT2U |
| 661 | #define CFG_DBAT3L CFG_IBAT3L |
| 662 | #define CFG_DBAT3U CFG_IBAT3U |
| 663 | #define CFG_DBAT4L CFG_IBAT4L |
| 664 | #define CFG_DBAT4U CFG_IBAT4U |
| 665 | #define CFG_DBAT5L CFG_IBAT5L |
| 666 | #define CFG_DBAT5U CFG_IBAT5U |
| 667 | #define CFG_DBAT6L CFG_IBAT6L |
| 668 | #define CFG_DBAT6U CFG_IBAT6U |
| 669 | #define CFG_DBAT7L CFG_IBAT7L |
| 670 | #define CFG_DBAT7U CFG_IBAT7U |
| 671 | |
| 672 | /* |
| 673 | * Internal Definitions |
| 674 | * |
| 675 | * Boot Flags |
| 676 | */ |
| 677 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 678 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 679 | |
| 680 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 681 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 682 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 683 | #endif |
| 684 | |
| 685 | |
| 686 | /* |
| 687 | * Environment Configuration |
| 688 | */ |
| 689 | #define CONFIG_ENV_OVERWRITE |
| 690 | |
| 691 | #ifdef CONFIG_MPC83XX_TSEC1 |
| 692 | #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 |
| 693 | #endif |
| 694 | |
| 695 | #ifdef CONFIG_MPC83XX_TSEC2 |
| 696 | #define CONFIG_HAS_ETH1 |
| 697 | #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 |
| 698 | #endif |
| 699 | |
| 700 | #define CONFIG_IPADDR 10.82.19.159 |
| 701 | #define CONFIG_SERVERIP 10.82.48.106 |
| 702 | #define CONFIG_GATEWAYIP 10.82.19.254 |
| 703 | #define CONFIG_NETMASK 255.255.252.0 |
Timur Tabi | 9888333 | 2006-10-31 19:14:41 -0600 | [diff] [blame^] | 704 | #define CONFIG_NETDEV eth0 |
Timur Tabi | 2ad6b51 | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 705 | |
| 706 | #define CONFIG_HOSTNAME mpc8349emitx |
| 707 | #define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs |
| 708 | #define CONFIG_BOOTFILE timur/uImage |
| 709 | |
| 710 | #define CONFIG_UBOOTPATH timur/u-boot.bin |
| 711 | #define CONFIG_UBOOTSTART fe700000 |
| 712 | #define CONFIG_UBOOTEND fe77ffff |
| 713 | |
| 714 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
| 715 | |
| 716 | #define CONFIG_BAUDRATE 115200 |
| 717 | |
| 718 | #undef CONFIG_BOOTCOMMAND |
| 719 | #ifdef CONFIG_BOOTCOMMAND |
| 720 | #define CONFIG_BOOTDELAY 6 |
| 721 | #else |
| 722 | #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
| 723 | #endif |
| 724 | |
Timur Tabi | 2ad6b51 | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 725 | #define XMK_STR(x) #x |
| 726 | #define MK_STR(x) XMK_STR(x) |
| 727 | |
Timur Tabi | 9888333 | 2006-10-31 19:14:41 -0600 | [diff] [blame^] | 728 | #define CONFIG_BOOTARGS \ |
| 729 | "root=/dev/nfs rw" \ |
| 730 | " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ |
| 731 | " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ |
| 732 | MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ |
| 733 | MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ |
| 734 | " console=ttyS0," MK_STR(CONFIG_BAUDRATE) |
| 735 | |
Timur Tabi | 2ad6b51 | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 736 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Timur Tabi | 9888333 | 2006-10-31 19:14:41 -0600 | [diff] [blame^] | 737 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ |
Timur Tabi | 2ad6b51 | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 738 | "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ |
| 739 | "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ |
| 740 | "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ |
| 741 | "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ |
| 742 | "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ |
| 743 | "protect off FEF00000 FEF7FFFF; " \ |
| 744 | "erase FEF00000 FEF7FFFF; " \ |
| 745 | "cp.b $loadaddr FEF00000 $filesize; " \ |
| 746 | "protect on FEF00000 FEF7FFFF; " \ |
| 747 | "cmp.b $loadaddr FEF00000 $filesize\0" \ |
| 748 | "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ |
| 749 | "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ |
| 750 | "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" |
| 751 | |
| 752 | |
| 753 | #undef MK_STR |
| 754 | #undef XMK_STR |
| 755 | |
| 756 | #endif |