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wdenk71f95112003-06-15 22:40:42 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenk71f95112003-06-15 22:40:42 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk71f95112003-06-15 22:40:42 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1
21#define CONFIG_MPC860T 1
22#define CONFIG_MPC862 1
23
24#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0x40000000
27
wdenk71f95112003-06-15 22:40:42 +000028#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020029#define CONFIG_SYS_SMC_RXBUFLEN 128
30#define CONFIG_SYS_MAXIDLE 10
wdenk71f95112003-06-15 22:40:42 +000031
wdenkae3af052003-08-07 22:18:11 +000032#define CONFIG_BOOTCOUNT_LIMIT
wdenk71f95112003-06-15 22:40:42 +000033
wdenk71f95112003-06-15 22:40:42 +000034
35#define CONFIG_BOARD_TYPES 1 /* support board types */
36
37#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010038 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk71f95112003-06-15 22:40:42 +000039 "echo"
40
41#undef CONFIG_BOOTARGS
42
43#define CONFIG_EXTRA_ENV_SETTINGS \
44 "netdev=eth0\0" \
45 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010046 "nfsroot=${serverip}:${rootpath}\0" \
wdenk71f95112003-06-15 22:40:42 +000047 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010048 "addip=setenv bootargs ${bootargs} " \
49 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
50 ":${hostname}:${netdev}:off panic=1\0" \
wdenk71f95112003-06-15 22:40:42 +000051 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "bootm ${kernel_addr}\0" \
wdenk71f95112003-06-15 22:40:42 +000053 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010054 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
55 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk71f95112003-06-15 22:40:42 +000056 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020057 "hostname=TQM862M\0" \
58 "bootfile=TQM862M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020059 "fdt_addr=40080000\0" \
60 "kernel_addr=400A0000\0" \
61 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020062 "u-boot=TQM862M/u-image.bin\0" \
63 "load=tftp 200000 ${u-boot}\0" \
64 "update=prot off 40000000 +${filesize};" \
65 "era 40000000 +${filesize};" \
66 "cp.b 200000 40000000 ${filesize};" \
67 "sete filesize;save\0" \
wdenk71f95112003-06-15 22:40:42 +000068 ""
69#define CONFIG_BOOTCOMMAND "run flash_self"
70
71#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk71f95112003-06-15 22:40:42 +000073
74#undef CONFIG_WATCHDOG /* watchdog disabled */
75
wdenk71f95112003-06-15 22:40:42 +000076#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
77
Jon Loeliger37d4bb72007-07-09 21:38:02 -050078/*
79 * BOOTP options
80 */
81#define CONFIG_BOOTP_SUBNETMASK
82#define CONFIG_BOOTP_GATEWAY
83#define CONFIG_BOOTP_HOSTNAME
84#define CONFIG_BOOTP_BOOTPATH
85#define CONFIG_BOOTP_BOOTFILESIZE
86
wdenk71f95112003-06-15 22:40:42 +000087#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
88
Jon Loeliger26946902007-07-04 22:30:50 -050089/*
90 * Command line configuration.
91 */
Jon Loeliger26946902007-07-04 22:30:50 -050092#define CONFIG_CMD_DATE
Jon Loeliger26946902007-07-04 22:30:50 -050093#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +020094#define CONFIG_CMD_JFFS2
wdenk71f95112003-06-15 22:40:42 +000095
Wolfgang Denk29f8f582008-08-09 23:17:32 +020096#define CONFIG_NETCONSOLE
97
wdenk71f95112003-06-15 22:40:42 +000098/*
99 * Miscellaneous configurable options
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk71f95112003-06-15 22:40:42 +0000102
Wolfgang Denk2751a952006-10-28 02:29:14 +0200103#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenk71f95112003-06-15 22:40:42 +0000104
Jon Loeliger26946902007-07-04 22:30:50 -0500105#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000107#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000109#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
111#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
115#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk71f95112003-06-15 22:40:42 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk71f95112003-06-15 22:40:42 +0000118
wdenk71f95112003-06-15 22:40:42 +0000119/*
120 * Low Level Configuration Settings
121 * (address mappings, register initial values, etc.)
122 * You should know what you are doing if you make changes here.
123 */
124/*-----------------------------------------------------------------------
125 * Internal Memory Mapped Register
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_IMMR 0xFFF00000
wdenk71f95112003-06-15 22:40:42 +0000128
129/*-----------------------------------------------------------------------
130 * Definitions for initial stack pointer and data area (in DPRAM)
131 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200133#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200134#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk71f95112003-06-15 22:40:42 +0000136
137/*-----------------------------------------------------------------------
138 * Start addresses for the final memory configuration
139 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk71f95112003-06-15 22:40:42 +0000141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_SDRAM_BASE 0x00000000
143#define CONFIG_SYS_FLASH_BASE 0x40000000
144#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
145#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
146#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk71f95112003-06-15 22:40:42 +0000147
148/*
149 * For booting Linux, the board info and command line data
150 * have to be in the first 8 MB of memory, since this is
151 * the maximum mapped by the Linux kernel during initialization.
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk71f95112003-06-15 22:40:42 +0000154
155/*-----------------------------------------------------------------------
156 * FLASH organization
157 */
wdenk71f95112003-06-15 22:40:42 +0000158
Martin Krausee318d9e2007-09-27 11:10:08 +0200159/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200161#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
163#define CONFIG_SYS_FLASH_EMPTY_INFO
164#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
165#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
166#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk71f95112003-06-15 22:40:42 +0000167
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200168#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200169#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
170#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
171#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenk71f95112003-06-15 22:40:42 +0000172
173/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200174#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
175#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk71f95112003-06-15 22:40:42 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200178
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200179#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
180
wdenk71f95112003-06-15 22:40:42 +0000181/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200182 * Dynamic MTD partition support
183 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100184#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200185#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
186#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200187#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
188
189#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
190 "128k(dtb)," \
191 "1920k(kernel)," \
192 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200193 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200194
195/*-----------------------------------------------------------------------
wdenk71f95112003-06-15 22:40:42 +0000196 * Hardware Information Block
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
199#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
200#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenk71f95112003-06-15 22:40:42 +0000201
202/*-----------------------------------------------------------------------
203 * Cache Configuration
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500206#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk71f95112003-06-15 22:40:42 +0000208#endif
209
210/*-----------------------------------------------------------------------
211 * SYPCR - System Protection Control 11-9
212 * SYPCR can only be written once after reset!
213 *-----------------------------------------------------------------------
214 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
215 */
216#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk71f95112003-06-15 22:40:42 +0000218 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
219#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk71f95112003-06-15 22:40:42 +0000221#endif
222
223/*-----------------------------------------------------------------------
224 * SIUMCR - SIU Module Configuration 11-6
225 *-----------------------------------------------------------------------
226 * PCMCIA config., multi-function pin tri-state
227 */
228#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk71f95112003-06-15 22:40:42 +0000230#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk71f95112003-06-15 22:40:42 +0000232#endif /* CONFIG_CAN_DRIVER */
233
234/*-----------------------------------------------------------------------
235 * TBSCR - Time Base Status and Control 11-26
236 *-----------------------------------------------------------------------
237 * Clear Reference Interrupt Status, Timebase freezing enabled
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk71f95112003-06-15 22:40:42 +0000240
241/*-----------------------------------------------------------------------
242 * RTCSC - Real-Time Clock Status and Control Register 11-27
243 *-----------------------------------------------------------------------
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk71f95112003-06-15 22:40:42 +0000246
247/*-----------------------------------------------------------------------
248 * PISCR - Periodic Interrupt Status and Control 11-31
249 *-----------------------------------------------------------------------
250 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk71f95112003-06-15 22:40:42 +0000253
254/*-----------------------------------------------------------------------
255 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
256 *-----------------------------------------------------------------------
257 * Reset PLL lock status sticky bit, timer expired status bit and timer
258 * interrupt status bit
wdenk71f95112003-06-15 22:40:42 +0000259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk71f95112003-06-15 22:40:42 +0000261
262/*-----------------------------------------------------------------------
263 * SCCR - System Clock and reset Control Register 15-27
264 *-----------------------------------------------------------------------
265 * Set clock output, timebase and RTC source and divider,
266 * power management and some other internal clocks
267 */
268#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenk71f95112003-06-15 22:40:42 +0000270 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
271 SCCR_DFALCD00)
wdenk71f95112003-06-15 22:40:42 +0000272
273/*-----------------------------------------------------------------------
274 * PCMCIA stuff
275 *-----------------------------------------------------------------------
276 *
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
279#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
280#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
281#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
282#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
283#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
284#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
285#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk71f95112003-06-15 22:40:42 +0000286
287/*-----------------------------------------------------------------------
288 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
289 *-----------------------------------------------------------------------
290 */
291
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000292#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenk71f95112003-06-15 22:40:42 +0000293#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
294
295#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
296#undef CONFIG_IDE_LED /* LED for ide not supported */
297#undef CONFIG_IDE_RESET /* reset for ide not supported */
298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
300#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk71f95112003-06-15 22:40:42 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk71f95112003-06-15 22:40:42 +0000303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk71f95112003-06-15 22:40:42 +0000305
306/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk71f95112003-06-15 22:40:42 +0000308
309/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk71f95112003-06-15 22:40:42 +0000311
312/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk71f95112003-06-15 22:40:42 +0000314
315/*-----------------------------------------------------------------------
316 *
317 *-----------------------------------------------------------------------
318 *
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_DER 0
wdenk71f95112003-06-15 22:40:42 +0000321
322/*
323 * Init Memory Controller:
324 *
325 * BR0/1 and OR0/1 (FLASH)
326 */
327
328#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
329#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
330
331/* used to re-map FLASH both when starting from SRAM or FLASH:
332 * restrict access enough to keep SRAM working (if any)
333 * but not too much to meddle with FLASH accesses
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
336#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk71f95112003-06-15 22:40:42 +0000337
338/*
339 * FLASH timing:
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk71f95112003-06-15 22:40:42 +0000342 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenk71f95112003-06-15 22:40:42 +0000343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
345#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
346#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
349#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
350#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000351
352/*
353 * BR2/3 and OR2/3 (SDRAM)
354 *
355 */
356#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
357#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
358#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
359
360/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk71f95112003-06-15 22:40:42 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
364#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000365
366#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
368#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000369#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
371#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
372#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
373#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenk71f95112003-06-15 22:40:42 +0000374 BR_PS_8 | BR_MS_UPMB | BR_V )
375#endif /* CONFIG_CAN_DRIVER */
376
377/*
378 * Memory Periodic Timer Prescaler
379 *
380 * The Divider for PTA (refresh timer) configuration is based on an
381 * example SDRAM configuration (64 MBit, one bank). The adjustment to
382 * the number of chip selects (NCS) and the actually needed refresh
383 * rate is done by setting MPTPR.
384 *
385 * PTA is calculated from
386 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
387 *
388 * gclk CPU clock (not bus clock!)
389 * Trefresh Refresh cycle * 4 (four word bursts used)
390 *
391 * 4096 Rows from SDRAM example configuration
392 * 1000 factor s -> ms
393 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
394 * 4 Number of refresh cycles per period
395 * 64 Refresh cycle in ms per number of rows
396 * --------------------------------------------
397 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
398 *
399 * 50 MHz => 50.000.000 / Divider = 98
400 * 66 Mhz => 66.000.000 / Divider = 129
401 * 80 Mhz => 80.000.000 / Divider = 156
402 * 100 Mhz => 100.000.000 / Divider = 195
403 */
wdenke9132ea2004-04-24 23:23:30 +0000404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
406#define CONFIG_SYS_MAMR_PTA 98
wdenk71f95112003-06-15 22:40:42 +0000407
408/*
409 * For 16 MBit, refresh rates could be 31.3 us
410 * (= 64 ms / 2K = 125 / quad bursts).
411 * For a simpler initialization, 15.6 us is used instead.
412 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
414 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk71f95112003-06-15 22:40:42 +0000415 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
417#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk71f95112003-06-15 22:40:42 +0000418
419/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
421#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk71f95112003-06-15 22:40:42 +0000422
423/*
424 * MAMR settings for SDRAM
425 */
426
427/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk71f95112003-06-15 22:40:42 +0000429 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
430 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
431/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk71f95112003-06-15 22:40:42 +0000433 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
434 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
435
wdenk71f95112003-06-15 22:40:42 +0000436#define CONFIG_SCC1_ENET
437#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200438#define CONFIG_ETHPRIME "SCC"
wdenk71f95112003-06-15 22:40:42 +0000439
Heiko Schocher7026ead2010-02-09 15:50:27 +0100440#define CONFIG_HWCONFIG 1
441
wdenk71f95112003-06-15 22:40:42 +0000442#endif /* __CONFIG_H */