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Wang Huand60a2092014-09-05 13:52:34 +08001/*
2 * Copyright 2014, Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _ASM_ARMV7_LS102XA_CONFIG_
8#define _ASM_ARMV7_LS102XA_CONFIG_
9
10#define CONFIG_SYS_CACHELINE_SIZE 64
11
12#define OCRAM_BASE_ADDR 0x10000000
13#define OCRAM_SIZE 0x00020000
Xiubo Li1a2826f2014-11-21 17:40:57 +080014#define OCRAM_BASE_S_ADDR 0x10010000
15#define OCRAM_S_SIZE 0x00010000
Wang Huand60a2092014-09-05 13:52:34 +080016
17#define CONFIG_SYS_IMMR 0x01000000
chenhui zhao306fa012014-10-22 18:20:22 +080018#define CONFIG_SYS_DCSRBAR 0x20000000
Wang Huand60a2092014-09-05 13:52:34 +080019
Alison Wang8ab967b2014-12-09 17:38:14 +080020#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
21
Wang Huand60a2092014-09-05 13:52:34 +080022#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
23#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
Xiubo Lie87f3b32014-11-21 17:40:58 +080024#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
Wang Huand60a2092014-09-05 13:52:34 +080025#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
26#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
27#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053028#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
29#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
Wang Huand60a2092014-09-05 13:52:34 +080030#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
31#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
32#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
33#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
34#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
Wang Huan327def52014-09-05 13:52:48 +080035#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
Nikhil Badola3f041f02014-10-17 11:35:46 +053036#define CONFIG_SYS_LS102XA_USB1_ADDR \
37 (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
Wang Huand60a2092014-09-05 13:52:34 +080038
Alison Wang81335742015-01-16 17:21:34 +080039#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
Nikhil Badola3f041f02014-10-17 11:35:46 +053040#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
Wang Huand60a2092014-09-05 13:52:34 +080041#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
42#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
43#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
44#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
45
46#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
47#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
48
49#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
50
51#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
52#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
53#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
54
55#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
56
57#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
58#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
59
60#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
61
Minghuan Lianda419022014-10-31 13:43:44 +080062#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
63#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
64
Minghuan Lian636ef952015-01-21 17:29:17 +080065#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
66#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
67#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
68#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
69#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
70/*
71 * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
72 * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
73 */
74#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
75 CONFIG_SYS_PCIE1_VIRT_ADDR)
76#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
77 CONFIG_SYS_PCIE2_VIRT_ADDR)
78
Wang Huand60a2092014-09-05 13:52:34 +080079#ifdef CONFIG_DDR_SPD
80#define CONFIG_SYS_FSL_DDR_BE
81#define CONFIG_VERY_BIG_RAM
York Sunc7eae7f2014-09-11 13:32:07 -070082#ifdef CONFIG_SYS_FSL_DDR4
83#define CONFIG_SYS_FSL_DDRC_GEN4
84#else
Wang Huand60a2092014-09-05 13:52:34 +080085#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
York Sunc7eae7f2014-09-11 13:32:07 -070086#endif
Wang Huand60a2092014-09-05 13:52:34 +080087#define CONFIG_SYS_FSL_DDR
88#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
89#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
90#endif
91
92#define CONFIG_SYS_FSL_IFC_BE
93#define CONFIG_SYS_FSL_ESDHC_BE
94#define CONFIG_SYS_FSL_WDOG_BE
95#define CONFIG_SYS_FSL_DSPI_BE
96#define CONFIG_SYS_FSL_QSPI_BE
Wang Huan327def52014-09-05 13:52:48 +080097#define CONFIG_SYS_FSL_DCU_BE
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053098#define CONFIG_SYS_FSL_SEC_LE
Wang Huan327def52014-09-05 13:52:48 +080099
100#define DCU_LAYER_MAX_NUM 16
Wang Huand60a2092014-09-05 13:52:34 +0800101
Zhao Qiang93d33202014-09-25 13:52:25 +0800102#define QE_MURAM_SIZE 0x6000UL
103#define MAX_QE_RISC 1
104#define QE_NUM_OF_SNUM 28
105
Wang Huand60a2092014-09-05 13:52:34 +0800106#define CONFIG_SYS_FSL_SRDS_1
107
108#ifdef CONFIG_LS102XA
109#define CONFIG_MAX_CPUS 2
110#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
111#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sunc7eae7f2014-09-11 13:32:07 -0700112#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530113#define CONFIG_SYS_FSL_SEC_COMPAT 5
Nikhil Badola3f041f02014-10-17 11:35:46 +0530114#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sundda3b612014-12-08 15:30:55 -0800115#define CONFIG_SYS_FSL_ERRATUM_A008378
Wang Huand60a2092014-09-05 13:52:34 +0800116#else
117#error SoC not defined
118#endif
119
Alison Wang33d2e462014-12-26 13:14:01 +0800120#define FSL_IFC_COMPAT "fsl,ifc"
121#define FSL_QSPI_COMPAT "fsl,ls1-qspi"
122#define FSL_DSPI_COMPAT "fsl,vf610-dspi"
123
Wang Huand60a2092014-09-05 13:52:34 +0800124#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */