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Wang Huand60a2092014-09-05 13:52:34 +08001/*
2 * Copyright 2014, Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _ASM_ARMV7_LS102XA_CONFIG_
8#define _ASM_ARMV7_LS102XA_CONFIG_
9
10#define CONFIG_SYS_CACHELINE_SIZE 64
11
12#define OCRAM_BASE_ADDR 0x10000000
13#define OCRAM_SIZE 0x00020000
14
15#define CONFIG_SYS_IMMR 0x01000000
chenhui zhao306fa012014-10-22 18:20:22 +080016#define CONFIG_SYS_DCSRBAR 0x20000000
Wang Huand60a2092014-09-05 13:52:34 +080017
18#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
19#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
20#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
21#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
22#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053023#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
24#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
Wang Huand60a2092014-09-05 13:52:34 +080025#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
26#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
27#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
28#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
29#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
Wang Huan327def52014-09-05 13:52:48 +080030#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
Nikhil Badola3f041f02014-10-17 11:35:46 +053031#define CONFIG_SYS_LS102XA_USB1_ADDR \
32 (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
Wang Huand60a2092014-09-05 13:52:34 +080033
Nikhil Badola3f041f02014-10-17 11:35:46 +053034#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
Wang Huand60a2092014-09-05 13:52:34 +080035#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
36#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
37#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
38#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
39
40#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
41#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
42
43#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
44
45#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
46#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
47#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
48
49#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
50
51#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
52#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
53
54#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
55
Minghuan Lianda419022014-10-31 13:43:44 +080056#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
57#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
58
Wang Huand60a2092014-09-05 13:52:34 +080059#ifdef CONFIG_DDR_SPD
60#define CONFIG_SYS_FSL_DDR_BE
61#define CONFIG_VERY_BIG_RAM
York Sunc7eae7f2014-09-11 13:32:07 -070062#ifdef CONFIG_SYS_FSL_DDR4
63#define CONFIG_SYS_FSL_DDRC_GEN4
64#else
Wang Huand60a2092014-09-05 13:52:34 +080065#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
York Sunc7eae7f2014-09-11 13:32:07 -070066#endif
Wang Huand60a2092014-09-05 13:52:34 +080067#define CONFIG_SYS_FSL_DDR
68#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
69#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
70#endif
71
72#define CONFIG_SYS_FSL_IFC_BE
73#define CONFIG_SYS_FSL_ESDHC_BE
74#define CONFIG_SYS_FSL_WDOG_BE
75#define CONFIG_SYS_FSL_DSPI_BE
76#define CONFIG_SYS_FSL_QSPI_BE
Wang Huan327def52014-09-05 13:52:48 +080077#define CONFIG_SYS_FSL_DCU_BE
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053078#define CONFIG_SYS_FSL_SEC_LE
Wang Huan327def52014-09-05 13:52:48 +080079
80#define DCU_LAYER_MAX_NUM 16
Wang Huand60a2092014-09-05 13:52:34 +080081
Zhao Qiang93d33202014-09-25 13:52:25 +080082#define QE_MURAM_SIZE 0x6000UL
83#define MAX_QE_RISC 1
84#define QE_NUM_OF_SNUM 28
85
Wang Huand60a2092014-09-05 13:52:34 +080086#define CONFIG_SYS_FSL_SRDS_1
87
88#ifdef CONFIG_LS102XA
89#define CONFIG_MAX_CPUS 2
90#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
91#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sunc7eae7f2014-09-11 13:32:07 -070092#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053093#define CONFIG_SYS_FSL_SEC_COMPAT 5
Nikhil Badola3f041f02014-10-17 11:35:46 +053094#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Wang Huand60a2092014-09-05 13:52:34 +080095#else
96#error SoC not defined
97#endif
98
99#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */