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wdenk935ecca2002-08-06 20:46:37 +00001#ifndef __ASM_PPC_PROCESSOR_H
2#define __ASM_PPC_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <linux/config.h>
11
12#include <asm/ptrace.h>
13#include <asm/types.h>
14
15/* Machine State Register (MSR) Fields */
16
17#ifdef CONFIG_PPC64BRIDGE
18#define MSR_SF (1<<63)
19#define MSR_ISF (1<<61)
20#endif /* CONFIG_PPC64BRIDGE */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070021#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
wdenk42d1f032003-10-15 23:53:47 +000022#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070023#define MSR_SPE (1<<25) /* Enable SPE(e500) */
wdenk935ecca2002-08-06 20:46:37 +000024#define MSR_POW (1<<18) /* Enable Power Management */
25#define MSR_WE (1<<18) /* Wait State Enable */
26#define MSR_TGPR (1<<17) /* TLB Update registers in use */
27#define MSR_CE (1<<17) /* Critical Interrupt Enable */
28#define MSR_ILE (1<<16) /* Interrupt Little Endian */
29#define MSR_EE (1<<15) /* External Interrupt Enable */
30#define MSR_PR (1<<14) /* Problem State / Privilege Level */
31#define MSR_FP (1<<13) /* Floating Point enable */
32#define MSR_ME (1<<12) /* Machine Check Enable */
33#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
34#define MSR_SE (1<<10) /* Single Step */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070035#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
36#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
wdenk935ecca2002-08-06 20:46:37 +000037#define MSR_BE (1<<9) /* Branch Trace */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +020038#define MSR_DE (1<<9) /* Debug Exception Enable */
wdenk935ecca2002-08-06 20:46:37 +000039#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
40#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +020041#define MSR_IR (1<<5) /* Instruction Relocate */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070042#define MSR_IS (1<<5) /* Book E Instruction space */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +020043#define MSR_DR (1<<4) /* Data Relocate */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070044#define MSR_DS (1<<4) /* Book E Data space */
wdenk935ecca2002-08-06 20:46:37 +000045#define MSR_PE (1<<3) /* Protection Enable */
46#define MSR_PX (1<<2) /* Protection Exclusive Mode */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070047#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
wdenk935ecca2002-08-06 20:46:37 +000048#define MSR_RI (1<<1) /* Recoverable Exception */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +020049#define MSR_LE (1<<0) /* Little Endian */
wdenk935ecca2002-08-06 20:46:37 +000050
51#ifdef CONFIG_APUS_FAST_EXCEPT
52#define MSR_ MSR_ME|MSR_IP|MSR_RI
53#else
54#define MSR_ MSR_ME|MSR_RI
55#endif
wdenk42d1f032003-10-15 23:53:47 +000056#ifndef CONFIG_E500
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070057#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
wdenk42d1f032003-10-15 23:53:47 +000058#else
59#define MSR_KERNEL MSR_ME
60#endif
wdenk935ecca2002-08-06 20:46:37 +000061
62/* Floating Point Status and Control Register (FPSCR) Fields */
63
64#define FPSCR_FX 0x80000000 /* FPU exception summary */
65#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
66#define FPSCR_VX 0x20000000 /* Invalid operation summary */
67#define FPSCR_OX 0x10000000 /* Overflow exception summary */
68#define FPSCR_UX 0x08000000 /* Underflow exception summary */
69#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70#define FPSCR_XX 0x02000000 /* Inexact exception summary */
71#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
72#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
73#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
74#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
75#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
76#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
77#define FPSCR_FR 0x00040000 /* Fraction rounded */
78#define FPSCR_FI 0x00020000 /* Fraction inexact */
79#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
80#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
81#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
82#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
83#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
84#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
85#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
86#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
87#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
88#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
89#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
90#define FPSCR_RN 0x00000003 /* FPU rounding control */
91
92/* Special Purpose Registers (SPRNs)*/
93
Eugene O'Brienf6ba9b52007-10-18 17:29:04 +020094/* PPC440 Architecture is BOOK-E */
95#ifdef CONFIG_440
96#define CONFIG_BOOKE
97#endif
98
wdenk3c74e322004-02-22 23:46:08 +000099#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
100#define SPRN_CTR 0x009 /* Count Register */
101#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
wdenk42d1f032003-10-15 23:53:47 +0000102#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000103#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
104#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
wdenk42d1f032003-10-15 23:53:47 +0000105#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700106#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
107#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
108#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000109#define SPRN_DAR 0x013 /* Data Address Register */
110#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
111#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
112#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
113#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
114#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
115#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
116#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
117#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700118#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
119#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
120#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
121#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
122#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
123#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
124#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
125#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
wdenk3c74e322004-02-22 23:46:08 +0000126#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
127#define DBCR_EDM 0x80000000
128#define DBCR_IDM 0x40000000
129#define DBCR_RST(x) (((x) & 0x3) << 28)
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200130#define DBCR_RST_NONE 0
131#define DBCR_RST_CORE 1
132#define DBCR_RST_CHIP 2
wdenk3c74e322004-02-22 23:46:08 +0000133#define DBCR_RST_SYSTEM 3
134#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
135#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
136#define DBCR_EDE 0x02000000 /* Exception Debug Event */
137#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
138#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
139#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
140#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
141#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
142#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
143#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
144#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
145#define DAC_BYTE 0
146#define DAC_HALF 1
147#define DAC_WORD 2
148#define DAC_QUAD 3
149#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
150#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
151#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
152#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
153#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
154#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
155#define DBCR_SIA 0x00000008 /* Second IAC Enable */
156#define DBCR_SDA 0x00000004 /* Second DAC Enable */
157#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
158#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
wdenk42d1f032003-10-15 23:53:47 +0000159#ifndef CONFIG_BOOKE
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700160#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
wdenk42d1f032003-10-15 23:53:47 +0000161#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700162#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
wdenk42d1f032003-10-15 23:53:47 +0000163#endif /* CONFIG_BOOKE */
164#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000165#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
166#define SPRN_DBSR 0x3F0 /* Debug Status Register */
wdenk42d1f032003-10-15 23:53:47 +0000167#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700168#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
169#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
170#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
171#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
wdenk42d1f032003-10-15 23:53:47 +0000172#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000173#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
174#define DCCR_NOCACHE 0 /* Noncacheable */
175#define DCCR_CACHE 1 /* Cacheable */
176#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
177#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
178#define DCWR_COPY 0 /* Copy-back */
179#define DCWR_WRITE 1 /* Write-through */
wdenk42d1f032003-10-15 23:53:47 +0000180#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000181#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
wdenk42d1f032003-10-15 23:53:47 +0000182#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700183#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
wdenk42d1f032003-10-15 23:53:47 +0000184#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000185#define SPRN_DEC 0x016 /* Decrement Register */
186#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
187#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
188#define SPRN_EAR 0x11A /* External Address Register */
wdenk42d1f032003-10-15 23:53:47 +0000189#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000190#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
wdenk42d1f032003-10-15 23:53:47 +0000191#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700192#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
wdenk42d1f032003-10-15 23:53:47 +0000193#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000194#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
195#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
196#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
197#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
198#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
199#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
200#define ESR_PTR 0x02000000 /* Program Exception - Trap */
201#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
202#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
203#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
204#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
205#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
206#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500207
208#define HID0_ICE_SHIFT 15
209#define HID0_DCE_SHIFT 14
210#define HID0_DLOCK_SHIFT 12
211
wdenk3c74e322004-02-22 23:46:08 +0000212#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
213#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
214#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
215#define HID0_SBCLK (1<<27)
216#define HID0_EICE (1<<26)
217#define HID0_ECLK (1<<25)
218#define HID0_PAR (1<<24)
219#define HID0_DOZE (1<<23)
220#define HID0_NAP (1<<22)
221#define HID0_SLEEP (1<<21)
222#define HID0_DPM (1<<20)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500223#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
224#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
Andy Fleming61a21e92007-08-14 01:34:21 -0500225#define HID0_TBEN (1<<14) /* Time Base Enable */
wdenk3c74e322004-02-22 23:46:08 +0000226#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500227#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
wdenk3c74e322004-02-22 23:46:08 +0000228#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
229#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
230#define HID0_DCI HID0_DCFI
wdenk935ecca2002-08-06 20:46:37 +0000231#define HID0_SPD (1<<9) /* Speculative disable */
Andy Fleming61a21e92007-08-14 01:34:21 -0500232#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
wdenk935ecca2002-08-06 20:46:37 +0000233#define HID0_SGE (1<<7) /* Store Gathering Enable */
wdenk3c74e322004-02-22 23:46:08 +0000234#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
wdenk935ecca2002-08-06 20:46:37 +0000235#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
236#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
237#define HID0_ABE (1<<3) /* Address Broadcast Enable */
wdenk3c74e322004-02-22 23:46:08 +0000238#define HID0_BHTE (1<<2) /* Branch History Table Enable */
239#define HID0_BTCD (1<<1) /* Branch target cache disable */
240#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
Andy Fleming81f481c2007-04-23 02:24:28 -0500241#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
242#define HID1_ASTME (1<<13) /* Address bus streaming mode */
243#define HID1_ABE (1<<12) /* Address broadcast enable */
wdenk3c74e322004-02-22 23:46:08 +0000244#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
wdenk42d1f032003-10-15 23:53:47 +0000245#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000246#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
247#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
wdenk42d1f032003-10-15 23:53:47 +0000248#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700249#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
250#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
wdenk42d1f032003-10-15 23:53:47 +0000251#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000252#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
253#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
254#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
255#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
256#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
257#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
258#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
259#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700260#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
261#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
262#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
263#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
264#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
265#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
266#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
267#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
wdenk3c74e322004-02-22 23:46:08 +0000268#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
269#define ICCR_NOCACHE 0 /* Noncacheable */
270#define ICCR_CACHE 1 /* Cacheable */
271#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
272#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
273#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
274#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200275#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700276#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
wdenk3c74e322004-02-22 23:46:08 +0000277#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
278#define SPRN_LR 0x008 /* Link Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700279#define SPRN_MBAR 0x137 /* System memory base address */
wdenk3c74e322004-02-22 23:46:08 +0000280#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
281#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
282#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
283#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
284#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
285#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
wdenk42d1f032003-10-15 23:53:47 +0000286#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000287#define SPRN_PID 0x3B1 /* Process ID */
288#define SPRN_PIR 0x3FF /* Processor Identification Register */
wdenk42d1f032003-10-15 23:53:47 +0000289#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700290#define SPRN_PID 0x030 /* Book E Process ID */
291#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
wdenk42d1f032003-10-15 23:53:47 +0000292#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000293#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
294#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
295#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
296#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
297#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
298#define SPRN_PVR 0x11F /* Processor Version Register */
299#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
300#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
301#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
302#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
303#define SGR_NORMAL 0
304#define SGR_GUARDED 1
305#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
306#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
307#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
308#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
309#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
Stefan Roesee01bd212007-03-21 13:38:59 +0100310#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
311#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
312#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
313#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
wdenk3c74e322004-02-22 23:46:08 +0000314#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
315#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
316#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200317#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000318#ifdef CONFIG_BOOKE
319#define SPRN_SVR 0x3FF /* System Version Register */
320#else
321#define SPRN_SVR 0x11E /* System Version Register */
322#endif
wdenk3c74e322004-02-22 23:46:08 +0000323#define SPRN_TBHI 0x3DC /* Time Base High */
324#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
325#define SPRN_TBLO 0x3DD /* Time Base Low */
326#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
Stefan Roese182e1062005-11-07 09:57:57 +0100327#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
328#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
329#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
330#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
wdenk42d1f032003-10-15 23:53:47 +0000331#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000332#define SPRN_TCR 0x3DA /* Timer Control Register */
wdenk42d1f032003-10-15 23:53:47 +0000333#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700334#define SPRN_TCR 0x154 /* Book E Timer Control Register */
wdenk42d1f032003-10-15 23:53:47 +0000335#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000336#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
337#define WP_2_17 0 /* 2^17 clocks */
338#define WP_2_21 1 /* 2^21 clocks */
339#define WP_2_25 2 /* 2^25 clocks */
340#define WP_2_29 3 /* 2^29 clocks */
341#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
342#define WRC_NONE 0 /* No reset will occur */
343#define WRC_CORE 1 /* Core reset will occur */
344#define WRC_CHIP 2 /* Chip reset will occur */
345#define WRC_SYSTEM 3 /* System reset will occur */
346#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
347#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
348#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
349#define FP_2_9 0 /* 2^9 clocks */
350#define FP_2_13 1 /* 2^13 clocks */
351#define FP_2_17 2 /* 2^17 clocks */
352#define FP_2_21 3 /* 2^21 clocks */
353#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
354#define TCR_ARE 0x00400000 /* Auto Reload Enable */
355#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
356#define THRM1_TIN (1<<0)
357#define THRM1_TIV (1<<1)
358#define THRM1_THRES (0x7f<<2)
359#define THRM1_TID (1<<29)
360#define THRM1_TIE (1<<30)
361#define THRM1_V (1<<31)
362#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
363#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
364#define THRM3_E (1<<31)
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700365#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
wdenk42d1f032003-10-15 23:53:47 +0000366#ifndef CONFIG_BOOKE
wdenk3c74e322004-02-22 23:46:08 +0000367#define SPRN_TSR 0x3D8 /* Timer Status Register */
wdenk42d1f032003-10-15 23:53:47 +0000368#else
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700369#define SPRN_TSR 0x150 /* Book E Timer Status Register */
wdenk42d1f032003-10-15 23:53:47 +0000370#endif /* CONFIG_BOOKE */
wdenk3c74e322004-02-22 23:46:08 +0000371#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
372#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
373#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
374#define WRS_NONE 0 /* No WDT reset occurred */
375#define WRS_CORE 1 /* WDT forced core reset */
376#define WRS_CHIP 2 /* WDT forced chip reset */
377#define WRS_SYSTEM 3 /* WDT forced system reset */
378#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
379#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
380#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
381#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
382#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
383#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
384#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
385#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
386#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
387#define SPRN_XER 0x001 /* Fixed Point Exception Register */
388#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
wdenk935ecca2002-08-06 20:46:37 +0000389
wdenk42d1f032003-10-15 23:53:47 +0000390/* Book E definitions */
391#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
392#define SPRN_CSRR0 0x03A /* Critical SRR0 */
393#define SPRN_CSRR1 0x03B /* Critical SRR0 */
wdenk3c74e322004-02-22 23:46:08 +0000394#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
wdenk42d1f032003-10-15 23:53:47 +0000395#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
wdenk3c74e322004-02-22 23:46:08 +0000396#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
397#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
398#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
399#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
400#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
401#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
402#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
403#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
wdenk42d1f032003-10-15 23:53:47 +0000404#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
wdenk3c74e322004-02-22 23:46:08 +0000405#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
406#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
wdenk42d1f032003-10-15 23:53:47 +0000407#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
408#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
409#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
410#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
411#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
412#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
413#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
414#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
415#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
416#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
417#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
418#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
419#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
420#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
421#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
422#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
423#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
424#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
425
426/* e500 definitions */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700427#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
428#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
Kumar Gala7f9f4342008-07-14 14:07:02 -0500429#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700430#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
431#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
432#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
433#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
434#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
435#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
436#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
437#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
Kumar Gala7f9f4342008-07-14 14:07:02 -0500438#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
439#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
440#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
441#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
442#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
443#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
444#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
445#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
446#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
447#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
448#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
449#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
450#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
451#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
452#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
wdenk42d1f032003-10-15 23:53:47 +0000453
wdenk3c74e322004-02-22 23:46:08 +0000454#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700455#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
456#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
457#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
458#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
459#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
460#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
461#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500462#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
wdenk42d1f032003-10-15 23:53:47 +0000463
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700464#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
465#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
466#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
467#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
468#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
wdenk42d1f032003-10-15 23:53:47 +0000469
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700470#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
471#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
wdenk42d1f032003-10-15 23:53:47 +0000472#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700473#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
474#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
475#define SPRN_PID1 0x279 /* Process ID Register 1 */
476#define SPRN_PID2 0x27a /* Process ID Register 2 */
wdenk42d1f032003-10-15 23:53:47 +0000477#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
Andy Fleming61a21e92007-08-14 01:34:21 -0500478#define SPRN_MCAR 0x23d /* Machine Check Address register */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200479#define MCSR_MCS 0x80000000 /* Machine Check Summary */
480#define MCSR_IB 0x40000000 /* Instruction PLB Error */
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700481#if defined(CONFIG_440)
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200482#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
483#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700484#else
485#define MCSR_DB 0x20000000 /* Data PLB Error */
486#endif /* defined(CONFIG_440) */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200487#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
488#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
489#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
490#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
491#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700492#define ESR_ST 0x00800000 /* Store Operation */
wdenk42d1f032003-10-15 23:53:47 +0000493
Jon Loeligerdebb7352006-04-26 17:58:56 -0500494#if defined(CONFIG_MPC86xx)
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500495#define SPRN_MSSCR0 0x3f6
496#define SPRN_MSSSR0 0x3f7
Jon Loeligerdebb7352006-04-26 17:58:56 -0500497#endif
498
wdenk935ecca2002-08-06 20:46:37 +0000499/* Short-hand versions for a number of the above SPRNs */
500
wdenk3c74e322004-02-22 23:46:08 +0000501#define CTR SPRN_CTR /* Counter Register */
502#define DAR SPRN_DAR /* Data Address Register */
503#define DABR SPRN_DABR /* Data Address Breakpoint Register */
504#define DAC1 SPRN_DAC1 /* Data Address Register 1 */
505#define DAC2 SPRN_DAC2 /* Data Address Register 2 */
506#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
507#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
508#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
509#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
510#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
511#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
512#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
513#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700514#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
515#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
516#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
517#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
518#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
519#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
520#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
521#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
wdenk3c74e322004-02-22 23:46:08 +0000522#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
523#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
524#define DBSR SPRN_DBSR /* Debug Status Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200525#define DCMP SPRN_DCMP /* Data TLB Compare Register */
526#define DEC SPRN_DEC /* Decrement Register */
527#define DMISS SPRN_DMISS /* Data TLB Miss Register */
wdenk3c74e322004-02-22 23:46:08 +0000528#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200529#define EAR SPRN_EAR /* External Address Register */
wdenk3c74e322004-02-22 23:46:08 +0000530#define ESR SPRN_ESR /* Exception Syndrome Register */
531#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
532#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
533#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
534#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200535#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
wdenk3c74e322004-02-22 23:46:08 +0000536#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
537#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
538#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
539#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
540#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
541#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
542#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
543#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
544#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
545#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
546#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
547#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
548#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
549#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
550#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
551#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200552#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
wdenk3c74e322004-02-22 23:46:08 +0000553#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
554#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
555#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200556#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700557#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200558#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
wdenk3c74e322004-02-22 23:46:08 +0000559#define LR SPRN_LR
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700560#define MBAR SPRN_MBAR /* System memory base address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500561#if defined(CONFIG_MPC86xx)
Ed Swarthout2e4d94f2007-07-27 01:50:45 -0500562#define MSSCR0 SPRN_MSSCR0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500563#endif
564#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
wdenk42d1f032003-10-15 23:53:47 +0000565#define PIR SPRN_PIR
566#endif
wdenk36c72872004-06-09 17:45:32 +0000567#define SVR SPRN_SVR /* System-On-Chip Version Register */
wdenk3c74e322004-02-22 23:46:08 +0000568#define PVR SPRN_PVR /* Processor Version */
569#define RPA SPRN_RPA /* Required Physical Address Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200570#define SDR1 SPRN_SDR1 /* MMU hash base register */
wdenk3c74e322004-02-22 23:46:08 +0000571#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
572#define SPR1 SPRN_SPRG1
573#define SPR2 SPRN_SPRG2
574#define SPR3 SPRN_SPRG3
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700575#define SPRG0 SPRN_SPRG0
576#define SPRG1 SPRN_SPRG1
577#define SPRG2 SPRN_SPRG2
578#define SPRG3 SPRN_SPRG3
579#define SPRG4 SPRN_SPRG4
580#define SPRG5 SPRN_SPRG5
581#define SPRG6 SPRN_SPRG6
582#define SPRG7 SPRN_SPRG7
wdenk3c74e322004-02-22 23:46:08 +0000583#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
584#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200585#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
586#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000587#define SVR SPRN_SVR /* System Version Register */
wdenk3c74e322004-02-22 23:46:08 +0000588#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
589#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
590#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
591#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
592#define TCR SPRN_TCR /* Timer Control Register */
593#define TSR SPRN_TSR /* Timer Status Register */
wdenk935ecca2002-08-06 20:46:37 +0000594#define ICTC 1019
wdenk3c74e322004-02-22 23:46:08 +0000595#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
596#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
597#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
598#define XER SPRN_XER
wdenk935ecca2002-08-06 20:46:37 +0000599
wdenk3c74e322004-02-22 23:46:08 +0000600#define DECAR SPRN_DECAR
601#define CSRR0 SPRN_CSRR0
602#define CSRR1 SPRN_CSRR1
603#define IVPR SPRN_IVPR
Jon Loeligerae624162006-08-22 18:07:00 -0500604#define USPRG0 SPRN_USPRG
wdenk3c74e322004-02-22 23:46:08 +0000605#define SPRG4R SPRN_SPRG4R
606#define SPRG5R SPRN_SPRG5R
607#define SPRG6R SPRN_SPRG6R
608#define SPRG7R SPRN_SPRG7R
609#define SPRG4W SPRN_SPRG4W
610#define SPRG5W SPRN_SPRG5W
611#define SPRG6W SPRN_SPRG6W
612#define SPRG7W SPRN_SPRG7W
wdenk42d1f032003-10-15 23:53:47 +0000613#define DEAR SPRN_DEAR
wdenk3c74e322004-02-22 23:46:08 +0000614#define DBCR2 SPRN_DBCR2
615#define IAC3 SPRN_IAC3
616#define IAC4 SPRN_IAC4
617#define DVC1 SPRN_DVC1
618#define DVC2 SPRN_DVC2
619#define IVOR0 SPRN_IVOR0
620#define IVOR1 SPRN_IVOR1
621#define IVOR2 SPRN_IVOR2
622#define IVOR3 SPRN_IVOR3
623#define IVOR4 SPRN_IVOR4
624#define IVOR5 SPRN_IVOR5
625#define IVOR6 SPRN_IVOR6
626#define IVOR7 SPRN_IVOR7
627#define IVOR8 SPRN_IVOR8
628#define IVOR9 SPRN_IVOR9
629#define IVOR10 SPRN_IVOR10
630#define IVOR11 SPRN_IVOR11
631#define IVOR12 SPRN_IVOR12
632#define IVOR13 SPRN_IVOR13
633#define IVOR14 SPRN_IVOR14
634#define IVOR15 SPRN_IVOR15
wdenk42d1f032003-10-15 23:53:47 +0000635#define IVOR32 SPRN_IVOR32
636#define IVOR33 SPRN_IVOR33
637#define IVOR34 SPRN_IVOR34
638#define IVOR35 SPRN_IVOR35
639#define MCSRR0 SPRN_MCSRR0
640#define MCSRR1 SPRN_MCSRR1
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200641#define L1CSR0 SPRN_L1CSR0
wdenk42d1f032003-10-15 23:53:47 +0000642#define L1CSR1 SPRN_L1CSR1
Kumar Gala7f9f4342008-07-14 14:07:02 -0500643#define L1CSR2 SPRN_L1CSR2
Kumar Galab009f3e2008-01-08 01:22:21 -0600644#define L1CFG0 SPRN_L1CFG0
645#define L1CFG1 SPRN_L1CFG1
Kumar Gala7f9f4342008-07-14 14:07:02 -0500646#define L2CFG0 SPRN_L2CFG0
647#define L2CSR0 SPRN_L2CSR0
648#define L2CSR1 SPRN_L2CSR1
wdenk42d1f032003-10-15 23:53:47 +0000649#define MCSR SPRN_MCSR
650#define MMUCSR0 SPRN_MMUCSR0
651#define BUCSR SPRN_BUCSR
652#define PID0 SPRN_PID
653#define PID1 SPRN_PID1
654#define PID2 SPRN_PID2
655#define MAS0 SPRN_MAS0
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200656#define MAS1 SPRN_MAS1
wdenk42d1f032003-10-15 23:53:47 +0000657#define MAS2 SPRN_MAS2
658#define MAS3 SPRN_MAS3
659#define MAS4 SPRN_MAS4
660#define MAS5 SPRN_MAS5
661#define MAS6 SPRN_MAS6
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500662#define MAS7 SPRN_MAS7
wdenk935ecca2002-08-06 20:46:37 +0000663
Rafal Jaworowskicc3023b2007-07-19 17:12:28 +0200664#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
665#define DAR_DEAR DEAR
666#else
667#define DAR_DEAR DAR
668#endif
669
wdenk935ecca2002-08-06 20:46:37 +0000670/* Device Control Registers */
671
wdenk3c74e322004-02-22 23:46:08 +0000672#define DCRN_BEAR 0x090 /* Bus Error Address Register */
673#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200674#define BESR_DSES 0x80000000 /* Data-Side Error Status */
wdenk3c74e322004-02-22 23:46:08 +0000675#define BESR_DMES 0x40000000 /* DMA Error Status */
676#define BESR_RWS 0x20000000 /* Read/Write Status */
677#define BESR_ETMASK 0x1C000000 /* Error Type */
678#define ET_PROT 0
679#define ET_PARITY 1
680#define ET_NCFG 2
681#define ET_BUSERR 4
682#define ET_BUSTO 6
683#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
684#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
685#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700686#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
687#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
688#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
689#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
690#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
691#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
692#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
693#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
694#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
695#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
696#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
697#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
698#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
699#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
700#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
701#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
702#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
703#define DCRN_DMASR 0x0E0 /* DMA Status Register */
704#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
wdenk3c74e322004-02-22 23:46:08 +0000705#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
706#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
707#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
708#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
709#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
710#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
711#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
712#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
713#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
714#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
715#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
716#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
717#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
718#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700719#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
720#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
wdenk3c74e322004-02-22 23:46:08 +0000721#define IOCR_E0TE 0x80000000
722#define IOCR_E0LP 0x40000000
723#define IOCR_E1TE 0x20000000
724#define IOCR_E1LP 0x10000000
725#define IOCR_E2TE 0x08000000
726#define IOCR_E2LP 0x04000000
727#define IOCR_E3TE 0x02000000
728#define IOCR_E3LP 0x01000000
729#define IOCR_E4TE 0x00800000
730#define IOCR_E4LP 0x00400000
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200731#define IOCR_EDT 0x00080000
732#define IOCR_SOR 0x00040000
wdenk3c74e322004-02-22 23:46:08 +0000733#define IOCR_EDO 0x00008000
734#define IOCR_2XC 0x00004000
735#define IOCR_ATC 0x00002000
736#define IOCR_SPD 0x00001000
737#define IOCR_BEM 0x00000800
738#define IOCR_PTD 0x00000400
739#define IOCR_ARE 0x00000080
740#define IOCR_DRC 0x00000020
741#define IOCR_RDM(x) (((x) & 0x3) << 3)
742#define IOCR_TCS 0x00000004
743#define IOCR_SCS 0x00000002
744#define IOCR_SPC 0x00000001
wdenk935ecca2002-08-06 20:46:37 +0000745
wdenk36c72872004-06-09 17:45:32 +0000746/* System-On-Chip Version Register */
747
748/* System-On-Chip Version Register (SVR) field extraction */
749
750#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
751#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
752
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700753#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
754#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
755#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
756#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
757#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
758#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
759#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
wdenk935ecca2002-08-06 20:46:37 +0000760
761/* Processor Version Register */
762
763/* Processor Version Register (PVR) field extraction */
764
wdenk3c74e322004-02-22 23:46:08 +0000765#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
766#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
wdenk935ecca2002-08-06 20:46:37 +0000767
768/*
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200769 * AMCC has further subdivided the standard PowerPC 16-bit version and
wdenk935ecca2002-08-06 20:46:37 +0000770 * revision subfields of the PVR for the PowerPC 403s into the following:
771 */
772
wdenk3c74e322004-02-22 23:46:08 +0000773#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
774#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
775#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
776#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
777#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
778#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
wdenk935ecca2002-08-06 20:46:37 +0000779
780/* Processor Version Numbers */
781
wdenk3c74e322004-02-22 23:46:08 +0000782#define PVR_403GA 0x00200000
783#define PVR_403GB 0x00200100
784#define PVR_403GC 0x00200200
785#define PVR_403GCX 0x00201400
786#define PVR_405GP 0x40110000
787#define PVR_405GP_RB 0x40110040
788#define PVR_405GP_RC 0x40110082
789#define PVR_405GP_RD 0x401100C4
790#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
791#define PVR_405CR_RA 0x40110041
792#define PVR_405CR_RB 0x401100C5
793#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
794#define PVR_405EP_RA 0x51210950
795#define PVR_405GPR_RB 0x50910951
Stefan Roesee01bd212007-03-21 13:38:59 +0100796#define PVR_405EZ_RA 0x41511460
Stefan Roese70fab192008-05-13 20:22:01 +0200797#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */
798#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
799#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
800#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */
801#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
802#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
803#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
804#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
wdenk3c74e322004-02-22 23:46:08 +0000805#define PVR_440GP_RB 0x40120440
806#define PVR_440GP_RC 0x40120481
Stefan Roesec157d8e2005-08-01 16:41:48 +0200807#define PVR_440EP_RA 0x42221850
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200808#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
Stefan Roese512f8d52006-05-10 14:10:41 +0200809#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200810#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
Stefan Roese512f8d52006-05-10 14:10:41 +0200811#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700812#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
813#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
814#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
815#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
wdenk3c74e322004-02-22 23:46:08 +0000816#define PVR_440GX_RA 0x51B21850
817#define PVR_440GX_RB 0x51B21851
stroese0a7c5392005-04-07 05:33:41 +0000818#define PVR_440GX_RC 0x51B21892
Stefan Roese57275b62005-11-01 10:08:03 +0100819#define PVR_440GX_RF 0x51B21894
wdenk3c74e322004-02-22 23:46:08 +0000820#define PVR_405EP_RB 0x51210950
Stefan Roese95981772007-01-13 08:01:03 +0100821#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
822#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
823#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
824#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
825#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
826#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
827#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
828#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700829#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
Stefan Roese999ecd52008-03-11 15:07:10 +0100830#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700831#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
Stefan Roese999ecd52008-03-11 15:07:10 +0100832#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
wdenk3c74e322004-02-22 23:46:08 +0000833#define PVR_601 0x00010000
834#define PVR_602 0x00050000
835#define PVR_603 0x00030000
836#define PVR_603e 0x00060000
837#define PVR_603ev 0x00070000
838#define PVR_603r 0x00071000
839#define PVR_604 0x00040000
840#define PVR_604e 0x00090000
841#define PVR_604r 0x000A0000
842#define PVR_620 0x00140000
843#define PVR_740 0x00080000
844#define PVR_750 PVR_740
845#define PVR_740P 0x10080000
846#define PVR_750P PVR_740P
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700847#define PVR_7400 0x000C0000
848#define PVR_7410 0x800C0000
849#define PVR_7450 0x80000000
wdenk0ac6f8b2004-07-09 23:27:13 +0000850
851#define PVR_85xx 0x80200000
852#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
853#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
854
Jon Loeligerdebb7352006-04-26 17:58:56 -0500855#define PVR_86xx 0x80040000
856#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
wdenk42d1f032003-10-15 23:53:47 +0000857
wdenk935ecca2002-08-06 20:46:37 +0000858/*
859 * For the 8xx processors, all of them report the same PVR family for
860 * the PowerPC core. The various versions of these processors must be
861 * differentiated by the version number in the Communication Processor
862 * Module (CPM).
863 */
wdenk3c74e322004-02-22 23:46:08 +0000864#define PVR_821 0x00500000
865#define PVR_823 PVR_821
866#define PVR_850 PVR_821
867#define PVR_860 PVR_821
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200868#define PVR_7400 0x000C0000
wdenk3c74e322004-02-22 23:46:08 +0000869#define PVR_8240 0x00810100
wdenk935ecca2002-08-06 20:46:37 +0000870
wdenk8564acf2003-07-14 22:13:32 +0000871/*
872 * PowerQUICC II family processors report different PVR values depending
873 * on silicon process (HiP3, HiP4, HiP7, etc.)
874 */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700875#define PVR_8260 PVR_8240
876#define PVR_8260_HIP3 0x00810101
877#define PVR_8260_HIP4 0x80811014
878#define PVR_8260_HIP7 0x80822011
wdenk5779d8d2003-12-06 23:55:10 +0000879#define PVR_8260_HIP7R1 0x80822013
wdenke1599e82004-10-10 23:27:33 +0000880#define PVR_8260_HIP7RA 0x80822014
wdenk935ecca2002-08-06 20:46:37 +0000881
Grzegorz Wianeckia9d87e22007-04-29 14:01:54 +0200882/*
883 * MPC 52xx
884 */
885#define PVR_5200 0x80822011
886#define PVR_5200B 0x80822014
887
wdenk0ac6f8b2004-07-09 23:27:13 +0000888/*
889 * System Version Register
890 */
891
892/* System Version Register (SVR) field extraction */
893
894#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
895#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
896
Jon Loeligerd14ba6a2006-09-14 08:40:36 -0500897#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
898
wdenk0ac6f8b2004-07-09 23:27:13 +0000899#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
900#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
901
902#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
903#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
904
Andy Fleming1ced1212008-02-06 01:19:40 -0600905/* Some parts define SVR[0:23] as the SOC version */
906#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
907
Kim Phillips6b70ffb2008-06-16 15:55:53 -0500908/* whether MPC8xxxE (i.e. has SEC) */
909#if defined(CONFIG_MPC85xx)
910#define IS_E_PROCESSOR(svr) (svr & 0x80000)
911#else
912#if defined(CONFIG_MPC83XX)
913#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
914#endif
915#endif
916
wdenk0ac6f8b2004-07-09 23:27:13 +0000917/*
Andy Fleming1ced1212008-02-06 01:19:40 -0600918 * SVR_SOC_VER() Version Values
wdenk0ac6f8b2004-07-09 23:27:13 +0000919 */
920
Andy Fleming1ced1212008-02-06 01:19:40 -0600921#define SVR_8533 0x803400
922#define SVR_8533_E 0x803C00
923#define SVR_8540 0x803000
924#define SVR_8541 0x807200
925#define SVR_8541_E 0x807A00
926#define SVR_8543 0x803200
927#define SVR_8543_E 0x803A00
928#define SVR_8544 0x803401
929#define SVR_8544_E 0x803C01
930#define SVR_8545 0x803102
931#define SVR_8545_E 0x803902
932#define SVR_8547_E 0x803901
933#define SVR_8548 0x803100
934#define SVR_8548_E 0x803900
935#define SVR_8555 0x807100
936#define SVR_8555_E 0x807900
937#define SVR_8560 0x807000
938#define SVR_8567 0x807600
939#define SVR_8567_E 0x807E00
940#define SVR_8568 0x807500
941#define SVR_8568_E 0x807D00
942#define SVR_8572 0x80E000
943#define SVR_8572_E 0x80E800
944
945#define SVR_8610 0x80A000
946#define SVR_8641 0x809000
947#define SVR_8641D 0x809001
948
wdenk935ecca2002-08-06 20:46:37 +0000949#define _GLOBAL(n)\
950 .globl n;\
951n:
952
953/* Macros for setting and retrieving special purpose registers */
954
955#define stringify(s) tostring(s)
956#define tostring(s) #s
957
958#define mfdcr(rn) ({unsigned int rval; \
959 asm volatile("mfdcr %0," stringify(rn) \
960 : "=r" (rval)); rval;})
961#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
962
963#define mfmsr() ({unsigned int rval; \
964 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
965#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
966
967#define mfspr(rn) ({unsigned int rval; \
968 asm volatile("mfspr %0," stringify(rn) \
969 : "=r" (rval)); rval;})
970#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
971
972#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
973
974/* Segment Registers */
975
976#define SR0 0
977#define SR1 1
978#define SR2 2
979#define SR3 3
980#define SR4 4
981#define SR5 5
982#define SR6 6
983#define SR7 7
984#define SR8 8
985#define SR9 9
986#define SR10 10
987#define SR11 11
988#define SR12 12
989#define SR13 13
990#define SR14 14
991#define SR15 15
992
993#ifndef __ASSEMBLY__
Kumar Gala4dbdb762008-06-10 16:53:46 -0500994
995struct cpu_type {
996 char name[15];
997 u32 soc_ver;
998};
999
Anatolij Gustschin96026d42008-06-12 12:40:11 +02001000struct cpu_type *identify_cpu(u32 ver);
Kumar Gala4dbdb762008-06-10 16:53:46 -05001001
Kim Phillips48902462008-06-17 17:45:27 -05001002#if defined(CONFIG_MPC85xx)
Kumar Gala4dbdb762008-06-10 16:53:46 -05001003#define CPU_TYPE_ENTRY(n, v) \
1004 { .name = #n, .soc_ver = SVR_##v, }
Kim Phillips48902462008-06-17 17:45:27 -05001005#else
1006#if defined(CONFIG_MPC83XX)
1007#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
1008#endif
1009#endif
1010
Kumar Gala4dbdb762008-06-10 16:53:46 -05001011
wdenk935ecca2002-08-06 20:46:37 +00001012#ifndef CONFIG_MACH_SPECIFIC
1013extern int _machine;
1014extern int have_of;
1015#endif /* CONFIG_MACH_SPECIFIC */
1016
1017/* what kind of prep workstation we are */
1018extern int _prep_type;
1019/*
1020 * This is used to identify the board type from a given PReP board
1021 * vendor. Board revision is also made available.
1022 */
1023extern unsigned char ucSystemType;
1024extern unsigned char ucBoardRev;
1025extern unsigned char ucBoardRevMaj, ucBoardRevMin;
1026
1027struct task_struct;
1028void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
1029void release_thread(struct task_struct *);
1030
1031/*
1032 * Create a new kernel thread.
1033 */
1034extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
1035
1036/*
1037 * Bus types
1038 */
1039#define EISA_bus 0
1040#define EISA_bus__is_a_macro /* for versions in ksyms.c */
1041#define MCA_bus 0
1042#define MCA_bus__is_a_macro /* for versions in ksyms.c */
1043
1044/* Lazy FPU handling on uni-processor */
1045extern struct task_struct *last_task_used_math;
1046extern struct task_struct *last_task_used_altivec;
1047
1048/*
1049 * this is the minimum allowable io space due to the location
1050 * of the io areas on prep (first one at 0x80000000) but
1051 * as soon as I get around to remapping the io areas with the BATs
1052 * to match the mac we can raise this. -- Cort
1053 */
1054#define TASK_SIZE (0x80000000UL)
1055
1056/* This decides where the kernel will search for a free chunk of vm
1057 * space during mmap's.
1058 */
1059#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
1060
1061typedef struct {
1062 unsigned long seg;
1063} mm_segment_t;
1064
1065struct thread_struct {
1066 unsigned long ksp; /* Kernel stack pointer */
1067 unsigned long wchan; /* Event task is sleeping on */
1068 struct pt_regs *regs; /* Pointer to saved register state */
1069 mm_segment_t fs; /* for get_fs() validation */
1070 void *pgdir; /* root of page-table tree */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07001071 signed long last_syscall;
wdenk935ecca2002-08-06 20:46:37 +00001072 double fpr[32]; /* Complete floating point set */
1073 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
1074 unsigned long fpscr; /* Floating point status */
1075#ifdef CONFIG_ALTIVEC
1076 vector128 vr[32]; /* Complete AltiVec set */
1077 vector128 vscr; /* AltiVec status */
1078 unsigned long vrsave;
1079#endif /* CONFIG_ALTIVEC */
1080};
1081
1082#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
1083
1084#define INIT_THREAD { \
1085 INIT_SP, /* ksp */ \
1086 0, /* wchan */ \
1087 (struct pt_regs *)INIT_SP - 1, /* regs */ \
1088 KERNEL_DS, /*fs*/ \
1089 swapper_pg_dir, /* pgdir */ \
1090 0, /* last_syscall */ \
1091 {0}, 0, 0 \
1092}
1093
1094/*
1095 * Note: the vm_start and vm_end fields here should *not*
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07001096 * be in kernel space. (Could vm_end == vm_start perhaps?)
wdenk935ecca2002-08-06 20:46:37 +00001097 */
1098#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
1099 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
1100 1, NULL, NULL }
1101
1102/*
1103 * Return saved PC of a blocked thread. For now, this is the "user" PC
1104 */
1105static inline unsigned long thread_saved_pc(struct thread_struct *t)
1106{
1107 return (t->regs) ? t->regs->nip : 0;
1108}
1109
1110#define copy_segments(tsk, mm) do { } while (0)
1111#define release_segments(mm) do { } while (0)
1112#define forget_segments() do { } while (0)
1113
1114unsigned long get_wchan(struct task_struct *p);
1115
1116#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1117#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1118
1119/*
1120 * NOTE! The task struct and the stack go together
1121 */
1122#define THREAD_SIZE (2*PAGE_SIZE)
1123#define alloc_task_struct() \
1124 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1125#define free_task_struct(p) free_pages((unsigned long)(p),1)
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07001126#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
wdenk935ecca2002-08-06 20:46:37 +00001127
1128/* in process.c - for early bootup debug -- Cort */
1129int ll_printk(const char *, ...);
1130void ll_puts(const char *);
1131
1132#define init_task (init_task_union.task)
1133#define init_stack (init_task_union.stack)
1134
1135/* In misc.c */
1136void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1137
1138#endif /* ndef ASSEMBLY*/
1139
1140#ifdef CONFIG_MACH_SPECIFIC
1141#if defined(CONFIG_8xx)
1142#define _machine _MACH_8xx
1143#define have_of 0
1144#elif defined(CONFIG_OAK)
1145#define _machine _MACH_oak
1146#define have_of 0
1147#elif defined(CONFIG_WALNUT)
1148#define _machine _MACH_walnut
1149#define have_of 0
1150#elif defined(CONFIG_APUS)
1151#define _machine _MACH_apus
1152#define have_of 0
1153#elif defined(CONFIG_GEMINI)
1154#define _machine _MACH_gemini
1155#define have_of 0
1156#elif defined(CONFIG_8260)
1157#define _machine _MACH_8260
1158#define have_of 0
1159#elif defined(CONFIG_SANDPOINT)
1160#define _machine _MACH_sandpoint
wdenk756f5862005-04-03 15:51:42 +00001161#elif defined(CONFIG_HIDDEN_DRAGON)
1162#define _machine _MACH_hidden_dragon
wdenk935ecca2002-08-06 20:46:37 +00001163#define have_of 0
1164#else
1165#error "Machine not defined correctly"
1166#endif
1167#endif /* CONFIG_MACH_SPECIFIC */
1168
1169#endif /* __ASM_PPC_PROCESSOR_H */