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wdenk935ecca2002-08-06 20:46:37 +00001#ifndef __ASM_PPC_PROCESSOR_H
2#define __ASM_PPC_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <linux/config.h>
11
12#include <asm/ptrace.h>
13#include <asm/types.h>
14
15/* Machine State Register (MSR) Fields */
16
17#ifdef CONFIG_PPC64BRIDGE
18#define MSR_SF (1<<63)
19#define MSR_ISF (1<<61)
20#endif /* CONFIG_PPC64BRIDGE */
21#define MSR_VEC (1<<25) /* Enable AltiVec */
22#define MSR_POW (1<<18) /* Enable Power Management */
23#define MSR_WE (1<<18) /* Wait State Enable */
24#define MSR_TGPR (1<<17) /* TLB Update registers in use */
25#define MSR_CE (1<<17) /* Critical Interrupt Enable */
26#define MSR_ILE (1<<16) /* Interrupt Little Endian */
27#define MSR_EE (1<<15) /* External Interrupt Enable */
28#define MSR_PR (1<<14) /* Problem State / Privilege Level */
29#define MSR_FP (1<<13) /* Floating Point enable */
30#define MSR_ME (1<<12) /* Machine Check Enable */
31#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
32#define MSR_SE (1<<10) /* Single Step */
33#define MSR_BE (1<<9) /* Branch Trace */
34#define MSR_DE (1<<9) /* Debug Exception Enable */
35#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
36#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
37#define MSR_IR (1<<5) /* Instruction Relocate */
38#define MSR_DR (1<<4) /* Data Relocate */
39#define MSR_PE (1<<3) /* Protection Enable */
40#define MSR_PX (1<<2) /* Protection Exclusive Mode */
41#define MSR_RI (1<<1) /* Recoverable Exception */
42#define MSR_LE (1<<0) /* Little Endian */
43
44#ifdef CONFIG_APUS_FAST_EXCEPT
45#define MSR_ MSR_ME|MSR_IP|MSR_RI
46#else
47#define MSR_ MSR_ME|MSR_RI
48#endif
49#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
50#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
51
52/* Floating Point Status and Control Register (FPSCR) Fields */
53
54#define FPSCR_FX 0x80000000 /* FPU exception summary */
55#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
56#define FPSCR_VX 0x20000000 /* Invalid operation summary */
57#define FPSCR_OX 0x10000000 /* Overflow exception summary */
58#define FPSCR_UX 0x08000000 /* Underflow exception summary */
59#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
60#define FPSCR_XX 0x02000000 /* Inexact exception summary */
61#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
62#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
63#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
64#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
65#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
66#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
67#define FPSCR_FR 0x00040000 /* Fraction rounded */
68#define FPSCR_FI 0x00020000 /* Fraction inexact */
69#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
70#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
71#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
72#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
73#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
74#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
75#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
76#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
77#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
78#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
79#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
80#define FPSCR_RN 0x00000003 /* FPU rounding control */
81
82/* Special Purpose Registers (SPRNs)*/
83
84#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
85#define SPRN_CTR 0x009 /* Count Register */
86#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
87#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
88#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
89#define SPRN_DAR 0x013 /* Data Address Register */
90#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
91#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
92#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
93#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
94#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
95#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
96#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
97#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
98#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
99#define DBCR_EDM 0x80000000
100#define DBCR_IDM 0x40000000
101#define DBCR_RST(x) (((x) & 0x3) << 28)
102#define DBCR_RST_NONE 0
103#define DBCR_RST_CORE 1
104#define DBCR_RST_CHIP 2
105#define DBCR_RST_SYSTEM 3
106#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
107#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
108#define DBCR_EDE 0x02000000 /* Exception Debug Event */
109#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
110#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
111#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
112#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
113#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
114#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
115#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
116#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
117#define DAC_BYTE 0
118#define DAC_HALF 1
119#define DAC_WORD 2
120#define DAC_QUAD 3
121#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
122#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
123#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
124#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
125#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
126#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
127#define DBCR_SIA 0x00000008 /* Second IAC Enable */
128#define DBCR_SDA 0x00000004 /* Second DAC Enable */
129#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
130#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
131#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
132#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
133#define SPRN_DBSR 0x3F0 /* Debug Status Register */
134#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
135#define DCCR_NOCACHE 0 /* Noncacheable */
136#define DCCR_CACHE 1 /* Cacheable */
137#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
138#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
139#define DCWR_COPY 0 /* Copy-back */
140#define DCWR_WRITE 1 /* Write-through */
141#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
142#define SPRN_DEC 0x016 /* Decrement Register */
143#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
144#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
145#define SPRN_EAR 0x11A /* External Address Register */
146#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
147#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
148#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
149#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
150#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
151#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
152#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
153#define ESR_PTR 0x02000000 /* Program Exception - Trap */
154#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
155#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
156#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
157#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
158#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
159#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
160#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
161#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
162#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
163#define HID0_SBCLK (1<<27)
164#define HID0_EICE (1<<26)
165#define HID0_ECLK (1<<25)
166#define HID0_PAR (1<<24)
167#define HID0_DOZE (1<<23)
168#define HID0_NAP (1<<22)
169#define HID0_SLEEP (1<<21)
170#define HID0_DPM (1<<20)
171#define HID0_ICE (1<<15) /* Instruction Cache Enable */
172#define HID0_DCE (1<<14) /* Data Cache Enable */
173#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
174#define HID0_DLOCK (1<<12) /* Data Cache Lock */
175#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
176#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
177#define HID0_DCI HID0_DCFI
178#define HID0_SPD (1<<9) /* Speculative disable */
179#define HID0_SGE (1<<7) /* Store Gathering Enable */
180#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
181#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
182#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
183#define HID0_ABE (1<<3) /* Address Broadcast Enable */
184#define HID0_BHTE (1<<2) /* Branch History Table Enable */
185#define HID0_BTCD (1<<1) /* Branch target cache disable */
186#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
187#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
188#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
189#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
190#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
191#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
192#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
193#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
194#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
195#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
196#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
197#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
198#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
199#define ICCR_NOCACHE 0 /* Noncacheable */
200#define ICCR_CACHE 1 /* Cacheable */
201#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
202#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
203#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
204#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
205#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
206#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
207#define SPRN_LR 0x008 /* Link Register */
208#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
209#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
210#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
211#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
212#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
213#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
214#define SPRN_PID 0x3B1 /* Process ID */
215#define SPRN_PIR 0x3FF /* Processor Identification Register */
216#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
217#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
218#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
219#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
220#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
221#define SPRN_PVR 0x11F /* Processor Version Register */
222#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
223#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
224#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
225#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
226#define SGR_NORMAL 0
227#define SGR_GUARDED 1
228#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
229#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
230#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
231#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
232#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
233#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
234#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
235#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
236#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
237#define SPRN_TBHI 0x3DC /* Time Base High */
238#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
239#define SPRN_TBLO 0x3DD /* Time Base Low */
240#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
241#define SPRN_TBRL 0x10D /* Time Base Read Lower Register */
242#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
243#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
244#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
245#define SPRN_TCR 0x3DA /* Timer Control Register */
246#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
247#define WP_2_17 0 /* 2^17 clocks */
248#define WP_2_21 1 /* 2^21 clocks */
249#define WP_2_25 2 /* 2^25 clocks */
250#define WP_2_29 3 /* 2^29 clocks */
251#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
252#define WRC_NONE 0 /* No reset will occur */
253#define WRC_CORE 1 /* Core reset will occur */
254#define WRC_CHIP 2 /* Chip reset will occur */
255#define WRC_SYSTEM 3 /* System reset will occur */
256#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
257#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
258#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
259#define FP_2_9 0 /* 2^9 clocks */
260#define FP_2_13 1 /* 2^13 clocks */
261#define FP_2_17 2 /* 2^17 clocks */
262#define FP_2_21 3 /* 2^21 clocks */
263#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
264#define TCR_ARE 0x00400000 /* Auto Reload Enable */
265#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
266#define THRM1_TIN (1<<0)
267#define THRM1_TIV (1<<1)
268#define THRM1_THRES (0x7f<<2)
269#define THRM1_TID (1<<29)
270#define THRM1_TIE (1<<30)
271#define THRM1_V (1<<31)
272#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
273#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
274#define THRM3_E (1<<31)
275#define SPRN_TSR 0x3D8 /* Timer Status Register */
276#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
277#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
278#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
279#define WRS_NONE 0 /* No WDT reset occurred */
280#define WRS_CORE 1 /* WDT forced core reset */
281#define WRS_CHIP 2 /* WDT forced chip reset */
282#define WRS_SYSTEM 3 /* WDT forced system reset */
283#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
284#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
285#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
286#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
287#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
288#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
289#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
290#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
291#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
292#define SPRN_XER 0x001 /* Fixed Point Exception Register */
293#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
294
295/* Short-hand versions for a number of the above SPRNs */
296
297#define CTR SPRN_CTR /* Counter Register */
298#define DAR SPRN_DAR /* Data Address Register */
299#define DABR SPRN_DABR /* Data Address Breakpoint Register */
300#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
301#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
302#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
303#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
304#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
305#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
306#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
307#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
308#define DCMP SPRN_DCMP /* Data TLB Compare Register */
309#define DEC SPRN_DEC /* Decrement Register */
310#define DMISS SPRN_DMISS /* Data TLB Miss Register */
311#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
312#define EAR SPRN_EAR /* External Address Register */
313#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
314#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
315#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
316#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
317#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
318#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
319#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
320#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
321#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
322#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
323#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
324#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
325#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
326#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
327#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
328#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
329#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
330#define LR SPRN_LR
331#define PVR SPRN_PVR /* Processor Version */
332#define RPA SPRN_RPA /* Required Physical Address Register */
333#define SDR1 SPRN_SDR1 /* MMU hash base register */
334#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
335#define SPR1 SPRN_SPRG1
336#define SPR2 SPRN_SPRG2
337#define SPR3 SPRN_SPRG3
338#define SPRG0 SPRN_SPRG0
339#define SPRG1 SPRN_SPRG1
340#define SPRG2 SPRN_SPRG2
341#define SPRG3 SPRN_SPRG3
342#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
343#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
344#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
345#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
346#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
347#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
348#define ICTC 1019
349#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
350#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
351#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
352#define XER SPRN_XER
353
354
355/* Device Control Registers */
356
357#define DCRN_BEAR 0x090 /* Bus Error Address Register */
358#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
359#define BESR_DSES 0x80000000 /* Data-Side Error Status */
360#define BESR_DMES 0x40000000 /* DMA Error Status */
361#define BESR_RWS 0x20000000 /* Read/Write Status */
362#define BESR_ETMASK 0x1C000000 /* Error Type */
363#define ET_PROT 0
364#define ET_PARITY 1
365#define ET_NCFG 2
366#define ET_BUSERR 4
367#define ET_BUSTO 6
368#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
369#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
370#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
371#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
372#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
373#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
374#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
375#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
376#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
377#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
378#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
379#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
380#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
381#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
382#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
383#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
384#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
385#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
386#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
387#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
388#define DCRN_DMASR 0x0E0 /* DMA Status Register */
389#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
390#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
391#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
392#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
393#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
394#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
395#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
396#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
397#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
398#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
399#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
400#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
401#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
402#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
403#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
404#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
405#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
406#define IOCR_E0TE 0x80000000
407#define IOCR_E0LP 0x40000000
408#define IOCR_E1TE 0x20000000
409#define IOCR_E1LP 0x10000000
410#define IOCR_E2TE 0x08000000
411#define IOCR_E2LP 0x04000000
412#define IOCR_E3TE 0x02000000
413#define IOCR_E3LP 0x01000000
414#define IOCR_E4TE 0x00800000
415#define IOCR_E4LP 0x00400000
416#define IOCR_EDT 0x00080000
417#define IOCR_SOR 0x00040000
418#define IOCR_EDO 0x00008000
419#define IOCR_2XC 0x00004000
420#define IOCR_ATC 0x00002000
421#define IOCR_SPD 0x00001000
422#define IOCR_BEM 0x00000800
423#define IOCR_PTD 0x00000400
424#define IOCR_ARE 0x00000080
425#define IOCR_DRC 0x00000020
426#define IOCR_RDM(x) (((x) & 0x3) << 3)
427#define IOCR_TCS 0x00000004
428#define IOCR_SCS 0x00000002
429#define IOCR_SPC 0x00000001
430
431
432/* Processor Version Register */
433
434/* Processor Version Register (PVR) field extraction */
435
436#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
437#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
438
439/*
440 * IBM has further subdivided the standard PowerPC 16-bit version and
441 * revision subfields of the PVR for the PowerPC 403s into the following:
442 */
443
444#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
445#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
446#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
447#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
448#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
449#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
450
451/* Processor Version Numbers */
452
453#define PVR_403GA 0x00200000
454#define PVR_403GB 0x00200100
455#define PVR_403GC 0x00200200
456#define PVR_403GCX 0x00201400
457#define PVR_405GP 0x40110000
458#define PVR_405GP_RB 0x40110040
459#define PVR_405GP_RC 0x40110082
460#define PVR_405GP_RD 0x401100C4
461#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
462#define PVR_405CR_RA 0x40110041
463#define PVR_405CR_RB 0x401100C5
464#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
465#define PVR_405GPR_RA 0x50910951
466#define PVR_440GP_RB 0x40120440
467#define PVR_440GP_RC 0x40120481
468#define PVR_601 0x00010000
469#define PVR_602 0x00050000
470#define PVR_603 0x00030000
471#define PVR_603e 0x00060000
472#define PVR_603ev 0x00070000
473#define PVR_603r 0x00071000
474#define PVR_604 0x00040000
475#define PVR_604e 0x00090000
476#define PVR_604r 0x000A0000
477#define PVR_620 0x00140000
478#define PVR_740 0x00080000
479#define PVR_750 PVR_740
480#define PVR_740P 0x10080000
481#define PVR_750P PVR_740P
482/*
483 * For the 8xx processors, all of them report the same PVR family for
484 * the PowerPC core. The various versions of these processors must be
485 * differentiated by the version number in the Communication Processor
486 * Module (CPM).
487 */
488#define PVR_821 0x00500000
489#define PVR_823 PVR_821
490#define PVR_850 PVR_821
491#define PVR_860 PVR_821
492#define PVR_7400 0x000C0000
493#define PVR_8240 0x00810100
494#define PVR_8260 PVR_8240
495
496
497/* I am just adding a single entry for 8260 boards. I think we may be
498 * able to combine mbx, fads, rpxlite, bseip, and classic into a single
499 * generic 8xx as well. The boards containing these processors are either
500 * identical at the processor level (due to the high integration) or so
501 * wildly different that testing _machine at run time is best replaced by
502 * conditional compilation by board type (found in their respective .h file).
503 * -- Dan
504 */
505#define _MACH_prep 0x00000001
506#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
507#define _MACH_chrp 0x00000004 /* chrp machine */
508#define _MACH_mbx 0x00000008 /* Motorola MBX board */
509#define _MACH_apus 0x00000010 /* amiga with phase5 powerup */
510#define _MACH_fads 0x00000020 /* Motorola FADS board */
511#define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */
512#define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */
513#define _MACH_yk 0x00000100 /* Motorola Yellowknife */
514#define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */
515#define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */
516#define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */
517#define _MACH_walnut 0x00001000 /* IBM "Walnut" 405GP eval. board */
518#define _MACH_8260 0x00002000 /* Generic 8260 */
519#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
520#define _MACH_tqm860 0x00008000 /* TQM860/L */
521#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
522
523
524/* see residual.h for these */
525#define _PREP_Motorola 0x01 /* motorola prep */
526#define _PREP_Firm 0x02 /* firmworks prep */
527#define _PREP_IBM 0x00 /* ibm prep */
528#define _PREP_Bull 0x03 /* bull prep */
529#define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */
530
531/*
532 * Radstone board types
533 */
534#define RS_SYS_TYPE_PPC1 0
535#define RS_SYS_TYPE_PPC2 1
536#define RS_SYS_TYPE_PPC1a 2
537#define RS_SYS_TYPE_PPC2a 3
538#define RS_SYS_TYPE_PPC4 4
539#define RS_SYS_TYPE_PPC4a 5
540#define RS_SYS_TYPE_PPC2ep 6
541
542/* these are arbitrary */
543#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
544#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
545
546#define _GLOBAL(n)\
547 .globl n;\
548n:
549
550/* Macros for setting and retrieving special purpose registers */
551
552#define stringify(s) tostring(s)
553#define tostring(s) #s
554
555#define mfdcr(rn) ({unsigned int rval; \
556 asm volatile("mfdcr %0," stringify(rn) \
557 : "=r" (rval)); rval;})
558#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
559
560#define mfmsr() ({unsigned int rval; \
561 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
562#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
563
564#define mfspr(rn) ({unsigned int rval; \
565 asm volatile("mfspr %0," stringify(rn) \
566 : "=r" (rval)); rval;})
567#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
568
569#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
570
571/* Segment Registers */
572
573#define SR0 0
574#define SR1 1
575#define SR2 2
576#define SR3 3
577#define SR4 4
578#define SR5 5
579#define SR6 6
580#define SR7 7
581#define SR8 8
582#define SR9 9
583#define SR10 10
584#define SR11 11
585#define SR12 12
586#define SR13 13
587#define SR14 14
588#define SR15 15
589
590#ifndef __ASSEMBLY__
591#ifndef CONFIG_MACH_SPECIFIC
592extern int _machine;
593extern int have_of;
594#endif /* CONFIG_MACH_SPECIFIC */
595
596/* what kind of prep workstation we are */
597extern int _prep_type;
598/*
599 * This is used to identify the board type from a given PReP board
600 * vendor. Board revision is also made available.
601 */
602extern unsigned char ucSystemType;
603extern unsigned char ucBoardRev;
604extern unsigned char ucBoardRevMaj, ucBoardRevMin;
605
606struct task_struct;
607void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
608void release_thread(struct task_struct *);
609
610/*
611 * Create a new kernel thread.
612 */
613extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
614
615/*
616 * Bus types
617 */
618#define EISA_bus 0
619#define EISA_bus__is_a_macro /* for versions in ksyms.c */
620#define MCA_bus 0
621#define MCA_bus__is_a_macro /* for versions in ksyms.c */
622
623/* Lazy FPU handling on uni-processor */
624extern struct task_struct *last_task_used_math;
625extern struct task_struct *last_task_used_altivec;
626
627/*
628 * this is the minimum allowable io space due to the location
629 * of the io areas on prep (first one at 0x80000000) but
630 * as soon as I get around to remapping the io areas with the BATs
631 * to match the mac we can raise this. -- Cort
632 */
633#define TASK_SIZE (0x80000000UL)
634
635/* This decides where the kernel will search for a free chunk of vm
636 * space during mmap's.
637 */
638#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
639
640typedef struct {
641 unsigned long seg;
642} mm_segment_t;
643
644struct thread_struct {
645 unsigned long ksp; /* Kernel stack pointer */
646 unsigned long wchan; /* Event task is sleeping on */
647 struct pt_regs *regs; /* Pointer to saved register state */
648 mm_segment_t fs; /* for get_fs() validation */
649 void *pgdir; /* root of page-table tree */
650 signed long last_syscall;
651 double fpr[32]; /* Complete floating point set */
652 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
653 unsigned long fpscr; /* Floating point status */
654#ifdef CONFIG_ALTIVEC
655 vector128 vr[32]; /* Complete AltiVec set */
656 vector128 vscr; /* AltiVec status */
657 unsigned long vrsave;
658#endif /* CONFIG_ALTIVEC */
659};
660
661#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
662
663#define INIT_THREAD { \
664 INIT_SP, /* ksp */ \
665 0, /* wchan */ \
666 (struct pt_regs *)INIT_SP - 1, /* regs */ \
667 KERNEL_DS, /*fs*/ \
668 swapper_pg_dir, /* pgdir */ \
669 0, /* last_syscall */ \
670 {0}, 0, 0 \
671}
672
673/*
674 * Note: the vm_start and vm_end fields here should *not*
675 * be in kernel space. (Could vm_end == vm_start perhaps?)
676 */
677#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
678 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
679 1, NULL, NULL }
680
681/*
682 * Return saved PC of a blocked thread. For now, this is the "user" PC
683 */
684static inline unsigned long thread_saved_pc(struct thread_struct *t)
685{
686 return (t->regs) ? t->regs->nip : 0;
687}
688
689#define copy_segments(tsk, mm) do { } while (0)
690#define release_segments(mm) do { } while (0)
691#define forget_segments() do { } while (0)
692
693unsigned long get_wchan(struct task_struct *p);
694
695#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
696#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
697
698/*
699 * NOTE! The task struct and the stack go together
700 */
701#define THREAD_SIZE (2*PAGE_SIZE)
702#define alloc_task_struct() \
703 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
704#define free_task_struct(p) free_pages((unsigned long)(p),1)
705#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
706
707/* in process.c - for early bootup debug -- Cort */
708int ll_printk(const char *, ...);
709void ll_puts(const char *);
710
711#define init_task (init_task_union.task)
712#define init_stack (init_task_union.stack)
713
714/* In misc.c */
715void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
716
717#endif /* ndef ASSEMBLY*/
718
719#ifdef CONFIG_MACH_SPECIFIC
720#if defined(CONFIG_8xx)
721#define _machine _MACH_8xx
722#define have_of 0
723#elif defined(CONFIG_OAK)
724#define _machine _MACH_oak
725#define have_of 0
726#elif defined(CONFIG_WALNUT)
727#define _machine _MACH_walnut
728#define have_of 0
729#elif defined(CONFIG_APUS)
730#define _machine _MACH_apus
731#define have_of 0
732#elif defined(CONFIG_GEMINI)
733#define _machine _MACH_gemini
734#define have_of 0
735#elif defined(CONFIG_8260)
736#define _machine _MACH_8260
737#define have_of 0
738#elif defined(CONFIG_SANDPOINT)
739#define _machine _MACH_sandpoint
740#define have_of 0
741#else
742#error "Machine not defined correctly"
743#endif
744#endif /* CONFIG_MACH_SPECIFIC */
745
746#endif /* __ASM_PPC_PROCESSOR_H */