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gerrit.cesnet.cz / github / trini / u-boot / 7ce343e49993341f2cdd559e0c44ad7507f71eb7 / . / board / siemens / SCM / fpga_scm.c
blob: 661bf66c66c76e5da45519f371ad49240ab3b46a [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
26#include <mpc8260.h>
27#include <common.h>
28#include "../common/fpga.h"
29
30fpga_t fpga_list[] = {
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]31 {"FIOX", CFG_FIOX_BASE,
32 CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE}
33 ,
34 {"FDOHM", CFG_FDOHM_BASE,
35 CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE}
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]36};
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]37int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]38
39
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]40ulong fpga_control (fpga_t * fpga, int cmd)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]41{
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]42 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]43
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]44 switch (cmd) {
45 case FPGA_INIT_IS_HIGH:
46 immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
47 return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]48
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]49 case FPGA_INIT_SET_LOW:
50 immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
51 immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
52 break;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]53
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]54 case FPGA_INIT_SET_HIGH:
55 immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
56 immr->im_ioport.iop_pdatd |= fpga->init_mask;
57 break;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]58
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]59 case FPGA_PROG_SET_LOW:
60 immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
61 break;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]62
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]63 case FPGA_PROG_SET_HIGH:
64 immr->im_ioport.iop_pdatd |= fpga->prog_mask;
65 break;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]66
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]67 case FPGA_DONE_IS_HIGH:
68 return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]69
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]70 case FPGA_READ_MODE:
71 break;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]72
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]73 case FPGA_LOAD_MODE:
74 break;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]75
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]76 case FPGA_GET_ID:
77 if (fpga->conf_base == CFG_FIOX_BASE) {
78 ulong ver =
79 *(volatile ulong *) (fpga->conf_base + 0x10);
80 return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
81 } else if (fpga->conf_base == CFG_FDOHM_BASE) {
82 return (*(volatile ushort *) fpga->conf_base) & 0xff;
83 } else {
84 return *(volatile ulong *) fpga->conf_base;
85 }
86
87 case FPGA_INIT_PORTS:
88 immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
89 immr->im_ioport.iop_psord &= ~fpga->init_mask;
90 immr->im_ioport.iop_pdird &= ~fpga->init_mask;
91
92 immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
93 immr->im_ioport.iop_psord &= ~fpga->prog_mask;
94 immr->im_ioport.iop_pdird |= fpga->prog_mask;
95
96 immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
97 immr->im_ioport.iop_psord &= ~fpga->done_mask;
98 immr->im_ioport.iop_pdird &= ~fpga->done_mask;
99
100 break;
101
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]102 }
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]103 return 0;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]104}