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gerrit.cesnet.cz / github / trini / u-boot / c609719b8d1b2dca590e0ed499016d041203e403 / . / board / siemens / SCM / fpga_scm.c
blob: 3b93794adcc33f1894a4324aa3bc6668618f7e49 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame^]1/*
2 * (C) Copyright 2002
3 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
26#include <mpc8260.h>
27#include <common.h>
28#include "../common/fpga.h"
29
30fpga_t fpga_list[] = {
31 { "FIOX" , CFG_FIOX_BASE ,
32 CFG_PD_FIOX_INIT , CFG_PD_FIOX_PROG , CFG_PD_FIOX_DONE },
33 { "FDOHM", CFG_FDOHM_BASE,
34 CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE }
35};
36int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
37
38
39ulong fpga_control (fpga_t* fpga, int cmd)
40{
41 volatile immap_t *immr = (immap_t *)CFG_IMMR;
42
43 switch (cmd) {
44 case FPGA_INIT_IS_HIGH:
45 immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
46 return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1:0;
47
48 case FPGA_INIT_SET_LOW:
49 immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
50 immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
51 break;
52
53 case FPGA_INIT_SET_HIGH:
54 immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
55 immr->im_ioport.iop_pdatd |= fpga->init_mask;
56 break;
57
58 case FPGA_PROG_SET_LOW:
59 immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
60 break;
61
62 case FPGA_PROG_SET_HIGH:
63 immr->im_ioport.iop_pdatd |= fpga->prog_mask;
64 break;
65
66 case FPGA_DONE_IS_HIGH:
67 return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1:0;
68
69 case FPGA_READ_MODE:
70 break;
71
72 case FPGA_LOAD_MODE:
73 break;
74
75 case FPGA_GET_ID:
76 if (fpga->conf_base == CFG_FIOX_BASE) {
77 ulong ver = *(volatile ulong *)(fpga->conf_base + 0x10);
78 return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
79 }
80 else if (fpga->conf_base == CFG_FDOHM_BASE) {
81 return (*(volatile ushort *)fpga->conf_base) & 0xff;
82 }
83 else {
84 return *(volatile ulong *)fpga->conf_base;
85 }
86
87 case FPGA_INIT_PORTS:
88 immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
89 immr->im_ioport.iop_psord &= ~fpga->init_mask;
90 immr->im_ioport.iop_pdird &= ~fpga->init_mask;
91
92 immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
93 immr->im_ioport.iop_psord &= ~fpga->prog_mask;
94 immr->im_ioport.iop_pdird |= fpga->prog_mask;
95
96 immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
97 immr->im_ioport.iop_psord &= ~fpga->done_mask;
98 immr->im_ioport.iop_pdird &= ~fpga->done_mask;
99
100 break;
101
102 }
103 return 0;
104}