blob: b607329cc1b95646b26662fee37a1e7c69539f96 [file] [log] [blame]
York Sune2b65ea2015-03-20 19:28:24 -07001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_RDB_H
8#define __LS2_RDB_H
9
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053010#include "ls2080a_common.h"
York Sune2b65ea2015-03-20 19:28:24 -070011
12#undef CONFIG_CONS_INDEX
13#define CONFIG_CONS_INDEX 2
14
Rai Harnindered2530d2016-03-23 17:04:38 +053015#define I2C_MUX_CH_VOL_MONITOR 0xa
16#define I2C_VOL_MONITOR_ADDR 0x38
17#define CONFIG_VOL_MONITOR_IR36021_READ
18#define CONFIG_VOL_MONITOR_IR36021_SET
19
20#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
21#ifndef CONFIG_SPL_BUILD
22#define CONFIG_VID
23#endif
24/* step the IR regulator in 5mV increments */
25#define IR_VDD_STEP_DOWN 5
26#define IR_VDD_STEP_UP 5
27/* The lowest and highest voltage allowed for LS2080ARDB */
28#define VDD_MV_MIN 819
29#define VDD_MV_MAX 1212
30
York Sune2b65ea2015-03-20 19:28:24 -070031#ifndef __ASSEMBLY__
32unsigned long get_board_sys_clk(void);
33#endif
34
35#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
36#define CONFIG_DDR_CLK_FREQ 133333333
37#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
38
39#define CONFIG_DDR_SPD
40#define CONFIG_DDR_ECC
41#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
42#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
43#define SPD_EEPROM_ADDRESS1 0x51
44#define SPD_EEPROM_ADDRESS2 0x52
York Sunfc7b3852015-05-28 14:54:09 +053045#define SPD_EEPROM_ADDRESS3 0x53
46#define SPD_EEPROM_ADDRESS4 0x54
York Sune2b65ea2015-03-20 19:28:24 -070047#define SPD_EEPROM_ADDRESS5 0x55
48#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
49#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
50#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
51#define CONFIG_DIMM_SLOTS_PER_CTLR 2
52#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053053#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sune2b65ea2015-03-20 19:28:24 -070054#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053055#endif
York Sune2b65ea2015-03-20 19:28:24 -070056#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
57
Tang Yuantian989c5f02015-12-09 15:32:18 +080058/* SATA */
59#define CONFIG_LIBATA
60#define CONFIG_SCSI_AHCI
61#define CONFIG_SCSI_AHCI_PLAT
Simon Glassc649e3c2016-05-01 11:36:02 -060062#define CONFIG_SCSI
Tang Yuantian989c5f02015-12-09 15:32:18 +080063
64#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
65#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
66
67#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
68#define CONFIG_SYS_SCSI_MAX_LUN 1
69#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
70 CONFIG_SYS_SCSI_MAX_LUN)
71
York Sune2b65ea2015-03-20 19:28:24 -070072/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
73
74#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
75#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
76#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
77
78#define CONFIG_SYS_NOR0_CSPR \
79 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
80 CSPR_PORT_SIZE_16 | \
81 CSPR_MSEL_NOR | \
82 CSPR_V)
83#define CONFIG_SYS_NOR0_CSPR_EARLY \
84 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
85 CSPR_PORT_SIZE_16 | \
86 CSPR_MSEL_NOR | \
87 CSPR_V)
88#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
89#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
90 FTIM0_NOR_TEADC(0x5) | \
91 FTIM0_NOR_TEAHC(0x5))
92#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
93 FTIM1_NOR_TRAD_NOR(0x1a) |\
94 FTIM1_NOR_TSEQRAD_NOR(0x13))
95#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
96 FTIM2_NOR_TCH(0x4) | \
97 FTIM2_NOR_TWPH(0x0E) | \
98 FTIM2_NOR_TWP(0x1c))
99#define CONFIG_SYS_NOR_FTIM3 0x04000000
100#define CONFIG_SYS_IFC_CCR 0x01000000
101
102#ifndef CONFIG_SYS_NO_FLASH
103#define CONFIG_FLASH_CFI_DRIVER
104#define CONFIG_SYS_FLASH_CFI
105#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
106#define CONFIG_SYS_FLASH_QUIET_TEST
107#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
108
109#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
110#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
111#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
112#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
113
114#define CONFIG_SYS_FLASH_EMPTY_INFO
115#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
116 CONFIG_SYS_FLASH_BASE + 0x40000000}
117#endif
118
119#define CONFIG_NAND_FSL_IFC
120#define CONFIG_SYS_NAND_MAX_ECCPOS 256
121#define CONFIG_SYS_NAND_MAX_OOBFREE 2
122
York Sune2b65ea2015-03-20 19:28:24 -0700123#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
124#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
125 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
126 | CSPR_MSEL_NAND /* MSEL = NAND */ \
127 | CSPR_V)
128#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
129
130#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
131 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
132 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
133 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
134 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
135 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
136 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
137
138#define CONFIG_SYS_NAND_ONFI_DETECTION
139
140/* ONFI NAND Flash mode0 Timing Params */
141#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
142 FTIM0_NAND_TWP(0x30) | \
143 FTIM0_NAND_TWCHT(0x0e) | \
144 FTIM0_NAND_TWH(0x14))
145#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
146 FTIM1_NAND_TWBE(0xab) | \
147 FTIM1_NAND_TRR(0x1c) | \
148 FTIM1_NAND_TRP(0x30))
149#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
150 FTIM2_NAND_TREH(0x14) | \
151 FTIM2_NAND_TWHRE(0x3c))
152#define CONFIG_SYS_NAND_FTIM3 0x0
153
154#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
155#define CONFIG_SYS_MAX_NAND_DEVICE 1
156#define CONFIG_MTD_NAND_VERIFY_WRITE
157#define CONFIG_CMD_NAND
158
159#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
160
161#define CONFIG_FSL_QIXIS /* use common QIXIS code */
162#define QIXIS_LBMAP_SWITCH 0x06
163#define QIXIS_LBMAP_MASK 0x0f
164#define QIXIS_LBMAP_SHIFT 0
165#define QIXIS_LBMAP_DFLTBANK 0x00
166#define QIXIS_LBMAP_ALTBANK 0x04
Scott Wood32eda7c2015-03-24 13:25:03 -0700167#define QIXIS_LBMAP_NAND 0x09
York Sune2b65ea2015-03-20 19:28:24 -0700168#define QIXIS_RST_CTL_RESET 0x31
169#define QIXIS_RST_CTL_RESET_EN 0x30
170#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
171#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
172#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Scott Wood32eda7c2015-03-24 13:25:03 -0700173#define QIXIS_RCW_SRC_NAND 0x119
York Sune2b65ea2015-03-20 19:28:24 -0700174#define QIXIS_RST_FORCE_MEM 0x01
175
176#define CONFIG_SYS_CSPR3_EXT (0x0)
177#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
178 | CSPR_PORT_SIZE_8 \
179 | CSPR_MSEL_GPCM \
180 | CSPR_V)
181#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
182 | CSPR_PORT_SIZE_8 \
183 | CSPR_MSEL_GPCM \
184 | CSPR_V)
185
186#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
187#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
188/* QIXIS Timing parameters for IFC CS3 */
189#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
190 FTIM0_GPCM_TEADC(0x0e) | \
191 FTIM0_GPCM_TEAHC(0x0e))
192#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
193 FTIM1_GPCM_TRAD(0x3f))
194#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
195 FTIM2_GPCM_TCH(0xf) | \
196 FTIM2_GPCM_TWP(0x3E))
197#define CONFIG_SYS_CS3_FTIM3 0x0
198
Scott Wood32eda7c2015-03-24 13:25:03 -0700199#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
200#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
201#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
202#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
203#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
204#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
205#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
206#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
207#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
208#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
209#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
210#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
211#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
212#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
213#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
214#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
215#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
216#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
217
218#define CONFIG_ENV_IS_IN_NAND
219#define CONFIG_ENV_OFFSET (2048 * 1024)
220#define CONFIG_ENV_SECT_SIZE 0x20000
221#define CONFIG_ENV_SIZE 0x2000
222#define CONFIG_SPL_PAD_TO 0x80000
223#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
224#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
225#else
York Sune2b65ea2015-03-20 19:28:24 -0700226#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
227#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
228#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
229#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
230#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
231#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
232#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
233#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
234#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
235#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
236#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
237#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
238#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
239#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
240#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
241#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
242#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
243
Scott Wood32eda7c2015-03-24 13:25:03 -0700244#define CONFIG_ENV_IS_IN_FLASH
245#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
246#define CONFIG_ENV_SECT_SIZE 0x20000
247#define CONFIG_ENV_SIZE 0x2000
248#endif
249
York Sune2b65ea2015-03-20 19:28:24 -0700250/* Debug Server firmware */
251#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
252#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
253
York Sune2b65ea2015-03-20 19:28:24 -0700254#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
255
256/*
257 * I2C
258 */
Prabhakar Kushwaha40123502015-05-28 14:54:01 +0530259#define I2C_MUX_PCA_ADDR 0x75
260#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
York Sune2b65ea2015-03-20 19:28:24 -0700261
262/* I2C bus multiplexer */
263#define I2C_MUX_CH_DEFAULT 0x8
264
Haikun Wang0c42a8d2015-07-03 16:51:35 +0800265/* SPI */
266#ifdef CONFIG_FSL_DSPI
Haikun Wang0c42a8d2015-07-03 16:51:35 +0800267#define CONFIG_SPI_FLASH
Haikun Wang0c42a8d2015-07-03 16:51:35 +0800268#define CONFIG_SPI_FLASH_BAR
Yuan Yao21640db2016-10-11 12:13:40 +0800269#define CONFIG_SPI_FLASH_STMICRO
Haikun Wang0c42a8d2015-07-03 16:51:35 +0800270#endif
271
York Sune2b65ea2015-03-20 19:28:24 -0700272/*
273 * RTC configuration
274 */
275#define RTC
276#define CONFIG_RTC_DS3231 1
277#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Priyanka Jain65814402015-05-28 14:53:56 +0530278#define CONFIG_CMD_DATE
York Sune2b65ea2015-03-20 19:28:24 -0700279
280/* EEPROM */
281#define CONFIG_ID_EEPROM
282#define CONFIG_CMD_EEPROM
283#define CONFIG_SYS_I2C_EEPROM_NXID
284#define CONFIG_SYS_EEPROM_BUS_NUM 0
285#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
286#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
287#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
288#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
289
York Sune2b65ea2015-03-20 19:28:24 -0700290#define CONFIG_FSL_MEMAC
York Sune2b65ea2015-03-20 19:28:24 -0700291
292#ifdef CONFIG_PCI
York Sune2b65ea2015-03-20 19:28:24 -0700293#define CONFIG_PCI_SCAN_SHOW
294#define CONFIG_CMD_PCI
York Sune2b65ea2015-03-20 19:28:24 -0700295#endif
296
Yangbo Lu8b064602015-03-20 19:28:31 -0700297/* MMC */
Yangbo Lu8b064602015-03-20 19:28:31 -0700298#ifdef CONFIG_MMC
Yangbo Lu8b064602015-03-20 19:28:31 -0700299#define CONFIG_FSL_ESDHC
300#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
301#define CONFIG_GENERIC_MMC
Yangbo Lu8b064602015-03-20 19:28:31 -0700302#endif
York Sune2b65ea2015-03-20 19:28:24 -0700303
Yangbo Lu5a4d7442015-05-28 14:53:55 +0530304#define CONFIG_MISC_INIT_R
305
Nikhil Badolae16b6042015-06-26 17:02:18 +0530306/*
307 * USB
308 */
309#define CONFIG_HAS_FSL_XHCI_USB
Nikhil Badolae16b6042015-06-26 17:02:18 +0530310#define CONFIG_USB_XHCI_FSL
Nikhil Badolae16b6042015-06-26 17:02:18 +0530311#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
312#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
Nikhil Badolae16b6042015-06-26 17:02:18 +0530313
Alexander Grafb99ebaf2016-11-17 01:03:02 +0100314#undef CONFIG_CMDLINE_EDITING
315#include <config_distro_defaults.h>
316
317#define BOOT_TARGET_DEVICES(func) \
318 func(USB, usb, 0) \
319 func(MMC, mmc, 0) \
320 func(SCSI, scsi, 0) \
321 func(DHCP, dhcp, na)
322#include <config_distro_bootcmd.h>
323
York Sune2b65ea2015-03-20 19:28:24 -0700324/* Initial environment variables */
325#undef CONFIG_EXTRA_ENV_SETTINGS
Udit Agarwal9ed44782017-01-06 15:58:57 +0530326#ifdef CONFIG_SECURE_BOOT
York Sune2b65ea2015-03-20 19:28:24 -0700327#define CONFIG_EXTRA_ENV_SETTINGS \
328 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Alexander Grafb99ebaf2016-11-17 01:03:02 +0100329 "scriptaddr=0x80800000\0" \
330 "kernel_addr_r=0x81000000\0" \
331 "pxefile_addr_r=0x81000000\0" \
332 "fdt_addr_r=0x88000000\0" \
333 "ramdisk_addr_r=0x89000000\0" \
York Sune2b65ea2015-03-20 19:28:24 -0700334 "loadaddr=0x80100000\0" \
335 "kernel_addr=0x100000\0" \
336 "ramdisk_addr=0x800000\0" \
337 "ramdisk_size=0x2000000\0" \
338 "fdt_high=0xa0000000\0" \
339 "initrd_high=0xffffffffffffffff\0" \
340 "kernel_start=0x581100000\0" \
341 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha16ed8562016-02-03 17:03:51 +0530342 "kernel_size=0x2800000\0" \
Alexander Grafb99ebaf2016-11-17 01:03:02 +0100343 "fdtfile=fsl-ls2080a-rdb.dtb\0" \
Udit Agarwal9ed44782017-01-06 15:58:57 +0530344 "mcinitcmd=esbc_validate 0x580c80000;" \
345 "esbc_validate 0x580cc0000;" \
346 "fsl_mc start mc 0x580300000" \
347 " 0x580800000 \0" \
Alexander Grafb99ebaf2016-11-17 01:03:02 +0100348 BOOTENV
Udit Agarwal9ed44782017-01-06 15:58:57 +0530349#else
350#define CONFIG_EXTRA_ENV_SETTINGS \
351 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
352 "scriptaddr=0x80800000\0" \
353 "kernel_addr_r=0x81000000\0" \
354 "pxefile_addr_r=0x81000000\0" \
355 "fdt_addr_r=0x88000000\0" \
356 "ramdisk_addr_r=0x89000000\0" \
357 "loadaddr=0x80100000\0" \
358 "kernel_addr=0x100000\0" \
359 "ramdisk_addr=0x800000\0" \
360 "ramdisk_size=0x2000000\0" \
361 "fdt_high=0xa0000000\0" \
362 "initrd_high=0xffffffffffffffff\0" \
363 "kernel_start=0x581100000\0" \
364 "kernel_load=0xa0000000\0" \
365 "kernel_size=0x2800000\0" \
366 "fdtfile=fsl-ls2080a-rdb.dtb\0" \
367 "mcinitcmd=fsl_mc start mc 0x580300000" \
368 " 0x580800000 \0" \
369 BOOTENV
370#endif
371
York Sune2b65ea2015-03-20 19:28:24 -0700372
Prabhakar Kushwaha56cd0762015-08-02 09:11:44 +0530373#undef CONFIG_BOOTARGS
374#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
York Suned77b702016-02-29 15:58:20 -0800375 "earlycon=uart8250,mmio,0x21c0600 " \
Prabhakar Kushwaha56cd0762015-08-02 09:11:44 +0530376 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
Ashish Kumar9e71bb9c2016-01-14 18:12:29 +0530377 " hugepagesz=2m hugepages=256"
Prabhakar Kushwaha56cd0762015-08-02 09:11:44 +0530378
Alexander Grafb99ebaf2016-11-17 01:03:02 +0100379#undef CONFIG_BOOTCOMMAND
380/* Try to boot an on-NOR kernel first, then do normal distro boot */
381#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
382 " && cp.b $kernel_start $kernel_load $kernel_size" \
383 " && bootm $kernel_load" \
384 " || run distro_bootcmd"
385
Prabhakar Kushwaha3484d952015-05-28 14:53:54 +0530386/* MAC/PHY configuration */
387#ifdef CONFIG_FSL_MC_ENET
388#define CONFIG_PHYLIB_10G
Shaohui Xiec69384e2015-09-24 18:20:32 +0800389#define CONFIG_PHY_AQUANTIA
Prabhakar Kushwaha3484d952015-05-28 14:53:54 +0530390#define CONFIG_PHY_CORTINA
391#define CONFIG_PHYLIB
392#define CONFIG_SYS_CORTINA_FW_IN_NOR
393#define CONFIG_CORTINA_FW_ADDR 0x581000000
394#define CONFIG_CORTINA_FW_LENGTH 0x40000
395
396#define CORTINA_PHY_ADDR1 0x10
397#define CORTINA_PHY_ADDR2 0x11
398#define CORTINA_PHY_ADDR3 0x12
399#define CORTINA_PHY_ADDR4 0x13
400#define AQ_PHY_ADDR1 0x00
401#define AQ_PHY_ADDR2 0x01
402#define AQ_PHY_ADDR3 0x02
403#define AQ_PHY_ADDR4 0x03
Shaohui Xieabc7d0f2016-01-28 15:38:15 +0800404#define AQR405_IRQ_MASK 0x36
Prabhakar Kushwaha3484d952015-05-28 14:53:54 +0530405
406#define CONFIG_MII
Prabhakar Kushwaha7ad9cc92016-04-19 08:53:42 +0530407#define CONFIG_ETHPRIME "DPMAC1@xgmii"
Prabhakar Kushwaha3484d952015-05-28 14:53:54 +0530408#define CONFIG_PHY_GIGE
Prabhakar Kushwaha95279312015-06-28 11:03:59 +0530409#define CONFIG_PHY_AQUANTIA
Prabhakar Kushwaha3484d952015-05-28 14:53:54 +0530410#endif
411
Saksham Jainfcfdb6d2016-03-23 16:24:35 +0530412#include <asm/fsl_secure_boot.h>
413
York Sune2b65ea2015-03-20 19:28:24 -0700414#endif /* __LS2_RDB_H */