blob: a9c064a45dfbb0e40aa9ca84182a45337f13fbe0 [file] [log] [blame]
Wolfgang Denk6ccec442006-10-24 14:42:37 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk6ccec442006-10-24 14:42:37 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020012
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000013#define CONFIG_AT32AP
14#define CONFIG_AT32AP7000
15#define CONFIG_ATSTK1002
16#define CONFIG_ATSTK1000
Wolfgang Denk6ccec442006-10-24 14:42:37 +020017
Wolfgang Denk6ccec442006-10-24 14:42:37 +020018/*
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020019 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
20 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
21 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Wolfgang Denk6ccec442006-10-24 14:42:37 +020023 */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000024#define CONFIG_PLL
25#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_OSC0_HZ 20000000
27#define CONFIG_SYS_PLL0_DIV 1
28#define CONFIG_SYS_PLL0_MUL 7
29#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020030/*
31 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020033 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_CLKDIV_CPU 0
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020035/*
36 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020038 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_CLKDIV_HSB 1
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020040/*
41 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020043 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_CLKDIV_PBA 2
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020045/*
46 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020048 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_CLKDIV_PBB 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +020050
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070051/* Reserve VM regions for SDRAM and NOR flash */
52#define CONFIG_SYS_NR_VM_REGIONS 2
53
Wolfgang Denk6ccec442006-10-24 14:42:37 +020054/*
55 * The PLLOPT register controls the PLL like this:
56 * icp = PLLOPT<2>
57 * ivco = PLLOPT<1:0>
58 *
59 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
60 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_PLL0_OPT 0x04
Wolfgang Denk6ccec442006-10-24 14:42:37 +020062
Andreas Bießmannf4278b72010-11-04 23:15:31 +000063#define CONFIG_USART_BASE ATMEL_BASE_USART1
64#define CONFIG_USART_ID 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +020065
66/* User serviceable stuff */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000067#define CONFIG_DOS_PARTITION
Haavard Skinnemoen8e687512006-12-17 18:56:46 +010068
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000069#define CONFIG_CMDLINE_TAG
70#define CONFIG_SETUP_MEMORY_TAGS
71#define CONFIG_INITRD_TAG
Wolfgang Denk6ccec442006-10-24 14:42:37 +020072
73#define CONFIG_STACKSIZE (2048)
74
75#define CONFIG_BAUDRATE 115200
76#define CONFIG_BOOTARGS \
Eirik Aanonsene80e5852007-09-18 08:47:20 +020077 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +010078
79#define CONFIG_BOOTCOMMAND \
80 "fsload; bootm $(fileaddr)"
81
82/*
83 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
84 * data on the serial line may interrupt the boot sequence.
85 */
Hans-Christian Egtvedt696dd132007-08-30 15:03:05 +020086#define CONFIG_BOOTDELAY 1
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000087#define CONFIG_AUTOBOOT
88#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +020089#define CONFIG_AUTOBOOT_PROMPT \
90 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +010091#define CONFIG_AUTOBOOT_DELAY_STR "d"
92#define CONFIG_AUTOBOOT_STOP_STR " "
Wolfgang Denk6ccec442006-10-24 14:42:37 +020093
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +010094/*
Haavard Skinnemoen8b6684a2007-10-24 15:48:37 +020095 * After booting the board for the first time, new ethernet addresses
96 * should be generated and assigned to the environment variables
97 * "ethaddr" and "eth1addr". This is normally done during production.
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +010098 */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000099#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100100
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500101/*
102 * BOOTP options
103 */
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106
Andreas Bießmann5c98d7f2015-02-06 23:06:50 +0100107/* generic board */
108#define CONFIG_SYS_GENERIC_BOARD
109#define CONFIG_BOARD_EARLY_INIT_F
110#define CONFIG_BOARD_EARLY_INIT_R
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200111
Jon Loeliger0b361c92007-07-04 22:31:42 -0500112/*
113 * Command line configuration.
114 */
115#include <config_cmd_default.h>
116
117#define CONFIG_CMD_ASKENV
118#define CONFIG_CMD_DHCP
119#define CONFIG_CMD_EXT2
120#define CONFIG_CMD_FAT
121#define CONFIG_CMD_JFFS2
122#define CONFIG_CMD_MMC
Jon Loeliger0b361c92007-07-04 22:31:42 -0500123
David Brownell55ac7a72008-02-22 12:54:39 -0800124#undef CONFIG_CMD_FPGA
Jon Loeliger0b361c92007-07-04 22:31:42 -0500125#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200126#undef CONFIG_CMD_SOURCE
Jon Loeliger0b361c92007-07-04 22:31:42 -0500127#undef CONFIG_CMD_XIMG
128
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000129#define CONFIG_ATMEL_USART
130#define CONFIG_MACB
131#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000133#define CONFIG_SYS_HSDRAMC
134#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200135#define CONFIG_GENERIC_ATMEL_MCI
136#define CONFIG_GENERIC_MMC
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_DCACHE_LINESZ 32
139#define CONFIG_SYS_ICACHE_LINESZ 32
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200140
141#define CONFIG_NR_DRAM_BANKS 1
142
Andreas Bießmann22178652011-06-28 04:15:58 +0000143#define CONFIG_SYS_FLASH_CFI
144#define CONFIG_FLASH_CFI_DRIVER
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_BASE 0x00000000
147#define CONFIG_SYS_FLASH_SIZE 0x800000
148#define CONFIG_SYS_MAX_FLASH_BANKS 1
149#define CONFIG_SYS_MAX_FLASH_SECT 135
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann47293c12011-04-18 04:12:44 +0000152#define CONFIG_SYS_TEXT_BASE 0x00000000
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
155#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
156#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200157
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000158#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200159#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MALLOC_LEN (256*1024)
Haavard Skinnemoen1f4f2122006-11-20 15:53:10 +0100165
Haavard Skinnemoen8269ab52007-11-22 17:01:24 +0100166/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
168#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200169
170/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_PROMPT "U-Boot> "
172#define CONFIG_SYS_CBSIZE 256
173#define CONFIG_SYS_MAXARGS 16
174#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000175#define CONFIG_SYS_LONGHELP
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
178#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
179#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200180
181#endif /* __CONFIG_H */