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Wolfgang Denk6ccec442006-10-24 14:42:37 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020027#include <asm/arch/memory-map.h>
28
Wolfgang Denk6ccec442006-10-24 14:42:37 +020029#define CONFIG_AVR32 1
30#define CONFIG_AT32AP 1
31#define CONFIG_AT32AP7000 1
32#define CONFIG_ATSTK1002 1
33#define CONFIG_ATSTK1000 1
34
35#define CONFIG_ATSTK1000_EXT_FLASH 1
36
37/*
38 * Timer clock frequency. We're using the CPU-internal COUNT register
39 * for this, so this is equivalent to the CPU core clock frequency
40 */
41#define CFG_HZ 1000
42
43/*
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020044 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
45 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
46 * PLL frequency.
47 * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
Wolfgang Denk6ccec442006-10-24 14:42:37 +020048 */
49#define CONFIG_PLL 1
50#define CFG_POWER_MANAGER 1
51#define CFG_OSC0_HZ 20000000
52#define CFG_PLL0_DIV 1
53#define CFG_PLL0_MUL 7
54#define CFG_PLL0_SUPPRESS_CYCLES 16
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020055/*
56 * Set the CPU running at:
57 * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
58 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020059#define CFG_CLKDIV_CPU 0
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020060/*
61 * Set the HSB running at:
62 * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
63 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020064#define CFG_CLKDIV_HSB 1
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020065/*
66 * Set the PBA running at:
67 * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
68 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020069#define CFG_CLKDIV_PBA 2
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020070/*
71 * Set the PBB running at:
72 * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
73 */
Wolfgang Denk6ccec442006-10-24 14:42:37 +020074#define CFG_CLKDIV_PBB 1
75
76/*
77 * The PLLOPT register controls the PLL like this:
78 * icp = PLLOPT<2>
79 * ivco = PLLOPT<1:0>
80 *
81 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
82 */
83#define CFG_PLL0_OPT 0x04
84
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010085#undef CONFIG_USART0
86#define CONFIG_USART1 1
87#undef CONFIG_USART2
88#undef CONFIG_USART3
Wolfgang Denk6ccec442006-10-24 14:42:37 +020089
90/* User serviceable stuff */
Haavard Skinnemoen8e687512006-12-17 18:56:46 +010091#define CONFIG_DOS_PARTITION 1
92
Wolfgang Denk6ccec442006-10-24 14:42:37 +020093#define CONFIG_CMDLINE_TAG 1
94#define CONFIG_SETUP_MEMORY_TAGS 1
95#define CONFIG_INITRD_TAG 1
96
97#define CONFIG_STACKSIZE (2048)
98
99#define CONFIG_BAUDRATE 115200
100#define CONFIG_BOOTARGS \
Eirik Aanonsene80e5852007-09-18 08:47:20 +0200101 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100102
103#define CONFIG_BOOTCOMMAND \
104 "fsload; bootm $(fileaddr)"
105
106/*
107 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
108 * data on the serial line may interrupt the boot sequence.
109 */
Hans-Christian Egtvedt696dd132007-08-30 15:03:05 +0200110#define CONFIG_BOOTDELAY 1
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100111#define CONFIG_AUTOBOOT 1
112#define CONFIG_AUTOBOOT_KEYED 1
113#define CONFIG_AUTOBOOT_PROMPT \
Wolfgang Denkb99c1e62007-04-18 16:53:52 +0200114 "Press SPACE to abort autoboot in %d seconds\n"
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +0100115#define CONFIG_AUTOBOOT_DELAY_STR "d"
116#define CONFIG_AUTOBOOT_STOP_STR " "
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200117
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100118/*
Haavard Skinnemoen8b6684a2007-10-24 15:48:37 +0200119 * After booting the board for the first time, new ethernet addresses
120 * should be generated and assigned to the environment variables
121 * "ethaddr" and "eth1addr". This is normally done during production.
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100122 */
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100123#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
124#define CONFIG_NET_MULTI 1
125
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500126/*
127 * BOOTP options
128 */
129#define CONFIG_BOOTP_SUBNETMASK
130#define CONFIG_BOOTP_GATEWAY
131
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200132
Jon Loeliger0b361c92007-07-04 22:31:42 -0500133/*
134 * Command line configuration.
135 */
136#include <config_cmd_default.h>
137
138#define CONFIG_CMD_ASKENV
139#define CONFIG_CMD_DHCP
140#define CONFIG_CMD_EXT2
141#define CONFIG_CMD_FAT
142#define CONFIG_CMD_JFFS2
143#define CONFIG_CMD_MMC
Jon Loeliger0b361c92007-07-04 22:31:42 -0500144
145#undef CONFIG_CMD_AUTOSCRIPT
David Brownell55ac7a72008-02-22 12:54:39 -0800146#undef CONFIG_CMD_FPGA
Jon Loeliger0b361c92007-07-04 22:31:42 -0500147#undef CONFIG_CMD_SETGETDCR
148#undef CONFIG_CMD_XIMG
149
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200150#define CONFIG_ATMEL_USART 1
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100151#define CONFIG_MACB 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200152#define CONFIG_PIO2 1
153#define CFG_NR_PIOS 5
154#define CFG_HSDRAMC 1
Haavard Skinnemoen8e687512006-12-17 18:56:46 +0100155#define CONFIG_MMC 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200156
157#define CFG_DCACHE_LINESZ 32
158#define CFG_ICACHE_LINESZ 32
159
160#define CONFIG_NR_DRAM_BANKS 1
161
162/* External flash on STK1000 */
163#if 0
164#define CFG_FLASH_CFI 1
165#define CFG_FLASH_CFI_DRIVER 1
166#endif
167
168#define CFG_FLASH_BASE 0x00000000
169#define CFG_FLASH_SIZE 0x800000
170#define CFG_MAX_FLASH_BANKS 1
171#define CFG_MAX_FLASH_SECT 135
172
173#define CFG_MONITOR_BASE CFG_FLASH_BASE
174
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200175#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
176#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
177#define CFG_SDRAM_BASE EBI_SDRAM_BASE
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200178
179#define CFG_ENV_IS_IN_FLASH 1
180#define CFG_ENV_SIZE 65536
181#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
182
183#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
184
185#define CFG_MALLOC_LEN (256*1024)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200186#define CFG_DMA_ALLOC_LEN (16384)
Haavard Skinnemoen1f4f2122006-11-20 15:53:10 +0100187
Haavard Skinnemoen8269ab52007-11-22 17:01:24 +0100188/* Allow 4MB for the kernel run-time image */
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200189#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200190#define CFG_BOOTPARAMS_LEN (16 * 1024)
191
192/* Other configuration settings that shouldn't have to change all that often */
David Brownell55ac7a72008-02-22 12:54:39 -0800193#define CFG_PROMPT "U-Boot> "
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200194#define CFG_CBSIZE 256
David Brownell55ac7a72008-02-22 12:54:39 -0800195#define CFG_MAXARGS 16
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200196#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
197#define CFG_LONGHELP 1
198
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200199#define CFG_MEMTEST_START EBI_SDRAM_BASE
Haavard Skinnemoen9add9882007-10-02 19:09:01 +0200200#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200201#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
202
203#endif /* __CONFIG_H */