blob: 359a915586c7b5327a0b755dc4806268811d4578 [file] [log] [blame]
Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Dave Liu19580e62007-09-18 12:37:57 +08002 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
Dave Liuf6eda7f2006-10-25 14:41:21 -05003 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +01004 * (C) Copyright 2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +02006 *
Dave Liu5f820432006-11-03 19:33:44 -06007 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05008 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
Eran Libertyf046ccd2005-07-28 10:08:46 -050028 */
29
30#include <common.h>
31#include <asm/processor.h>
32#include <i2c.h>
33#include <spd.h>
34#include <asm/mmu.h>
35#include <spd_sdram.h>
36
Kim Phillips81fd52c2008-03-28 10:18:53 -050037DECLARE_GLOBAL_DATA_PTR;
38
Kim Phillipsbbea46f2007-08-16 22:52:48 -050039void board_add_ram_info(int use_default)
40{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Kim Phillipsbbea46f2007-08-16 22:52:48 -050042 volatile ddr83xx_t *ddr = &immap->ddr;
Kim Phillips81fd52c2008-03-28 10:18:53 -050043 char buf[32];
Kim Phillipsbbea46f2007-08-16 22:52:48 -050044
45 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
46 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
47
48 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
49 puts(", 32-bit");
50 else
51 puts(", 64-bit");
52
53 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
Kim Phillips81fd52c2008-03-28 10:18:53 -050054 puts(", ECC on");
Kim Phillipsbbea46f2007-08-16 22:52:48 -050055 else
Kim Phillips81fd52c2008-03-28 10:18:53 -050056 puts(", ECC off");
57
58 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
Kim Phillipsbbea46f2007-08-16 22:52:48 -050059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
Kim Phillipsbbea46f2007-08-16 22:52:48 -050061 puts("\nSDRAM: ");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
Kim Phillipsbbea46f2007-08-16 22:52:48 -050063#endif
64}
65
Eran Libertyf046ccd2005-07-28 10:08:46 -050066#ifdef CONFIG_SPD_EEPROM
67
Dave Liuf6eda7f2006-10-25 14:41:21 -050068#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
Eran Libertyf046ccd2005-07-28 10:08:46 -050069extern void dma_init(void);
70extern uint dma_check(void);
71extern int dma_xfer(void *dest, uint count, void *src);
72#endif
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#ifndef CONFIG_SYS_READ_SPD
75#define CONFIG_SYS_READ_SPD i2c_read
Eran Libertyf046ccd2005-07-28 10:08:46 -050076#endif
77
Eran Libertyf046ccd2005-07-28 10:08:46 -050078/*
79 * Convert picoseconds into clock cycles (rounding up if needed).
80 */
Eran Libertyf046ccd2005-07-28 10:08:46 -050081int
82picos_to_clk(int picos)
83{
Kim Phillips35cf1552008-03-28 10:18:40 -050084 unsigned int mem_bus_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -050085 int clks;
86
Kim Phillips35cf1552008-03-28 10:18:40 -050087 mem_bus_clk = gd->mem_clk >> 1;
88 clks = picos / (1000000000 / (mem_bus_clk / 1000));
89 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
Dave Liuf6eda7f2006-10-25 14:41:21 -050090 clks++;
Eran Libertyf046ccd2005-07-28 10:08:46 -050091
92 return clks;
93}
94
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +010095unsigned int banksize(unsigned char row_dens)
Eran Libertyf046ccd2005-07-28 10:08:46 -050096{
97 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
98}
99
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100100int read_spd(uint addr)
101{
102 return ((int) addr);
103}
104
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100105#undef SPD_DEBUG
106#ifdef SPD_DEBUG
107static void spd_debug(spd_eeprom_t *spd)
108{
109 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
110 printf ("SPD size: %d\n", spd->info_size);
111 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
112 printf ("Memory type: %d\n", spd->mem_type);
113 printf ("Row addr: %d\n", spd->nrow_addr);
114 printf ("Column addr: %d\n", spd->ncol_addr);
115 printf ("# of rows: %d\n", spd->nrows);
116 printf ("Row density: %d\n", spd->row_dens);
117 printf ("# of banks: %d\n", spd->nbanks);
118 printf ("Data width: %d\n",
119 256 * spd->dataw_msb + spd->dataw_lsb);
120 printf ("Chip width: %d\n", spd->primw);
121 printf ("Refresh rate: %02X\n", spd->refresh);
122 printf ("CAS latencies: %02X\n", spd->cas_lat);
123 printf ("Write latencies: %02X\n", spd->write_lat);
124 printf ("tRP: %d\n", spd->trp);
125 printf ("tRCD: %d\n", spd->trcd);
126 printf ("\n");
127}
128#endif /* SPD_DEBUG */
129
130long int spd_sdram()
Eran Libertyf046ccd2005-07-28 10:08:46 -0500131{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500133 volatile ddr83xx_t *ddr = &immap->ddr;
134 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
Eran Libertyf046ccd2005-07-28 10:08:46 -0500135 spd_eeprom_t spd;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800136 unsigned int n_ranks;
137 unsigned int odt_rd_cfg, odt_wr_cfg;
138 unsigned char twr_clk, twtr_clk;
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500139 unsigned int sdram_type;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500140 unsigned int memsize;
141 unsigned int law_size;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500142 unsigned char caslat, caslat_ctrl;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800143 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
144 unsigned int trcd_clk, trtp_clk;
145 unsigned char cke_min_clk;
146 unsigned char add_lat, wr_lat;
147 unsigned char wr_data_delay;
148 unsigned char four_act;
149 unsigned char cpo;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500150 unsigned char burstlen;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800151 unsigned char odt_cfg, mode_odt_enable;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500152 unsigned int max_bus_clk;
153 unsigned int max_data_rate, effective_data_rate;
154 unsigned int ddrc_clk;
155 unsigned int refresh_clk;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800156 unsigned int sdram_cfg;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500157 unsigned int ddrc_ecc_enable;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800158 unsigned int pvr = get_pvr();
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500159
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100160 /* Read SPD parameters with I2C */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100162#ifdef SPD_DEBUG
163 spd_debug(&spd);
164#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500165 /* Check the memory type */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800166 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500167 debug("DDR: Module mem type is %02X\n", spd.mem_type);
Dave Liuf6eda7f2006-10-25 14:41:21 -0500168 return 0;
169 }
170
171 /* Check the number of physical bank */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800172 if (spd.mem_type == SPD_MEMTYPE_DDR) {
173 n_ranks = spd.nrows;
174 } else {
175 n_ranks = (spd.nrows & 0x7) + 1;
176 }
177
178 if (n_ranks > 2) {
179 printf("DDR: The number of physical bank is %02X\n", n_ranks);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500180 return 0;
181 }
182
Dave Liuf6eda7f2006-10-25 14:41:21 -0500183 /* Check if the number of row of the module is in the range of DDRC */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800184 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500185 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
186 spd.nrow_addr);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500187 return 0;
188 }
189
Dave Liuf6eda7f2006-10-25 14:41:21 -0500190 /* Check if the number of col of the module is in the range of DDRC */
191 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
192 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
193 spd.ncol_addr);
194 return 0;
195 }
Xie Xiaobod61853c2007-02-14 18:27:17 +0800196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#ifdef CONFIG_SYS_DDRCDR_VALUE
Xie Xiaobod61853c2007-02-14 18:27:17 +0800198 /*
199 * Adjust DDR II IO voltage biasing. It just makes it work.
200 */
201 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800203 }
Dave Liu19580e62007-09-18 12:37:57 +0800204 udelay(50000);
Xie Xiaobod61853c2007-02-14 18:27:17 +0800205#endif
206
207 /*
208 * ODT configuration recommendation from DDR Controller Chapter.
209 */
210 odt_rd_cfg = 0; /* Never assert ODT */
211 odt_wr_cfg = 0; /* Never assert ODT */
212 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
213 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
214 }
215
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100216 /* Setup DDR chip select register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#ifdef CONFIG_SYS_83XX_DDR_USES_CS0
Dave Liu5f820432006-11-03 19:33:44 -0600218 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
219 ddr->cs_config[0] = ( 1 << 31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800220 | (odt_rd_cfg << 20)
221 | (odt_wr_cfg << 16)
Dave Liu5f820432006-11-03 19:33:44 -0600222 | (spd.nrow_addr - 12) << 8
223 | (spd.ncol_addr - 8) );
224 debug("\n");
225 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
226 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
227
Xie Xiaobod61853c2007-02-14 18:27:17 +0800228 if (n_ranks == 2) {
Dave Liu5f820432006-11-03 19:33:44 -0600229 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
230 | ((banksize(spd.row_dens) >> 23) - 1) );
231 ddr->cs_config[1] = ( 1<<31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800232 | (odt_rd_cfg << 20)
233 | (odt_wr_cfg << 16)
Dave Liu5f820432006-11-03 19:33:44 -0600234 | (spd.nrow_addr-12) << 8
235 | (spd.ncol_addr-8) );
236 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
237 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
238 }
239
240#else
Eran Libertyf046ccd2005-07-28 10:08:46 -0500241 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
242 ddr->cs_config[2] = ( 1 << 31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800243 | (odt_rd_cfg << 20)
244 | (odt_wr_cfg << 16)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500245 | (spd.nrow_addr - 12) << 8
246 | (spd.ncol_addr - 8) );
247 debug("\n");
248 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
249 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500250
Xie Xiaobod61853c2007-02-14 18:27:17 +0800251 if (n_ranks == 2) {
Eran Libertyf046ccd2005-07-28 10:08:46 -0500252 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
253 | ((banksize(spd.row_dens) >> 23) - 1) );
254 ddr->cs_config[3] = ( 1<<31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800255 | (odt_rd_cfg << 20)
256 | (odt_wr_cfg << 16)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500257 | (spd.nrow_addr-12) << 8
258 | (spd.ncol_addr-8) );
259 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
260 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
261 }
Timur Tabi2ad6b512006-10-31 18:44:42 -0600262#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500263
Eran Libertyf046ccd2005-07-28 10:08:46 -0500264 /*
265 * Figure out memory size in Megabytes.
266 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800267 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500268
269 /*
270 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
271 */
272 law_size = 19 + __ilog2(memsize);
273
274 /*
275 * Set up LAWBAR for all of DDR.
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500278 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
279 debug("DDR:bar=0x%08x\n", ecm->bar);
280 debug("DDR:ar=0x%08x\n", ecm->ar);
281
282 /*
Dave Liuf6eda7f2006-10-25 14:41:21 -0500283 * Find the largest CAS by locating the highest 1 bit
284 * in the spd.cas_lat field. Translate it to a DDR
285 * controller field value:
286 *
Xie Xiaobod61853c2007-02-14 18:27:17 +0800287 * CAS Lat DDR I DDR II Ctrl
288 * Clocks SPD Bit SPD Bit Value
289 * ------- ------- ------- -----
290 * 1.0 0 0001
291 * 1.5 1 0010
292 * 2.0 2 2 0011
293 * 2.5 3 0100
294 * 3.0 4 3 0101
295 * 3.5 5 0110
296 * 4.0 6 4 0111
297 * 4.5 1000
298 * 5.0 5 1001
Eran Libertyf046ccd2005-07-28 10:08:46 -0500299 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500300 caslat = __ilog2(spd.cas_lat);
Xie Xiaobod61853c2007-02-14 18:27:17 +0800301 if ((spd.mem_type == SPD_MEMTYPE_DDR)
302 && (caslat > 6)) {
303 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
304 return 0;
305 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
306 && (caslat < 2 || caslat > 5)) {
307 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
308 spd.cas_lat);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500309 return 0;
310 }
Xie Xiaobod61853c2007-02-14 18:27:17 +0800311 debug("DDR: caslat SPD bit is %d\n", caslat);
312
Dave Liuf6eda7f2006-10-25 14:41:21 -0500313 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
314 + (spd.clk_cycle & 0x0f));
315 max_data_rate = max_bus_clk * 2;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500316
Dave Liuf6eda7f2006-10-25 14:41:21 -0500317 debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500318
Kim Phillips35cf1552008-03-28 10:18:40 -0500319 ddrc_clk = gd->mem_clk / 1000000;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800320 effective_data_rate = 0;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500321
Xie Xiaobod61853c2007-02-14 18:27:17 +0800322 if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
323 if (ddrc_clk <= 460 && ddrc_clk > 350) {
324 /* DDR controller clk at 350~460 */
Dave Liu5f820432006-11-03 19:33:44 -0600325 effective_data_rate = 400; /* 5ns */
326 caslat = caslat;
327 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
328 /* DDR controller clk at 280~350 */
329 effective_data_rate = 333; /* 6ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600330 if (spd.clk_cycle2 == 0x60)
Dave Liu5f820432006-11-03 19:33:44 -0600331 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600332 else
Dave Liu5f820432006-11-03 19:33:44 -0600333 caslat = caslat;
Dave Liu5f820432006-11-03 19:33:44 -0600334 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
335 /* DDR controller clk at 230~280 */
336 effective_data_rate = 266; /* 7.5ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600337 if (spd.clk_cycle3 == 0x75)
Dave Liu5f820432006-11-03 19:33:44 -0600338 caslat = caslat - 2;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800339 else if (spd.clk_cycle2 == 0x75)
Dave Liu5f820432006-11-03 19:33:44 -0600340 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600341 else
Dave Liu5f820432006-11-03 19:33:44 -0600342 caslat = caslat;
Dave Liu5f820432006-11-03 19:33:44 -0600343 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
344 /* DDR controller clk at 90~230 */
345 effective_data_rate = 200; /* 10ns */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800346 if (spd.clk_cycle3 == 0xa0)
Dave Liu5f820432006-11-03 19:33:44 -0600347 caslat = caslat - 2;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800348 else if (spd.clk_cycle2 == 0xa0)
Dave Liu5f820432006-11-03 19:33:44 -0600349 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600350 else
Dave Liu5f820432006-11-03 19:33:44 -0600351 caslat = caslat;
Dave Liu5f820432006-11-03 19:33:44 -0600352 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500353 } else if (max_data_rate >= 323) { /* it is DDR 333 */
354 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liu5f820432006-11-03 19:33:44 -0600355 /* DDR controller clk at 280~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500356 effective_data_rate = 333; /* 6ns */
357 caslat = caslat;
358 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600359 /* DDR controller clk at 230~280 */
360 effective_data_rate = 266; /* 7.5ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600361 if (spd.clk_cycle2 == 0x75)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500362 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600363 else
Dave Liu5f820432006-11-03 19:33:44 -0600364 caslat = caslat;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500365 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600366 /* DDR controller clk at 90~230 */
367 effective_data_rate = 200; /* 10ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600368 if (spd.clk_cycle3 == 0xa0)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500369 caslat = caslat - 2;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800370 else if (spd.clk_cycle2 == 0xa0)
Dave Liu5f820432006-11-03 19:33:44 -0600371 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600372 else
Dave Liu5f820432006-11-03 19:33:44 -0600373 caslat = caslat;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500374 }
375 } else if (max_data_rate >= 256) { /* it is DDR 266 */
376 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liu5f820432006-11-03 19:33:44 -0600377 /* DDR controller clk at 280~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500378 printf("DDR: DDR controller freq is more than "
379 "max data rate of the module\n");
380 return 0;
381 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600382 /* DDR controller clk at 230~280 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500383 effective_data_rate = 266; /* 7.5ns */
384 caslat = caslat;
385 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600386 /* DDR controller clk at 90~230 */
387 effective_data_rate = 200; /* 10ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600388 if (spd.clk_cycle2 == 0xa0)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500389 caslat = caslat - 1;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500390 }
391 } else if (max_data_rate >= 190) { /* it is DDR 200 */
392 if (ddrc_clk <= 350 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600393 /* DDR controller clk at 230~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500394 printf("DDR: DDR controller freq is more than "
395 "max data rate of the module\n");
396 return 0;
397 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600398 /* DDR controller clk at 90~230 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500399 effective_data_rate = 200; /* 10ns */
400 caslat = caslat;
401 }
Eran Libertyf046ccd2005-07-28 10:08:46 -0500402 }
403
Dave Liu5f820432006-11-03 19:33:44 -0600404 debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
405 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
Timur Tabibed85ca2006-10-31 18:13:36 -0600406
Dave Liu5f820432006-11-03 19:33:44 -0600407 /*
408 * Errata DDR6 work around: input enable 2 cycles earlier.
409 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
410 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800411 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
412 if (caslat == 2)
413 ddr->debug_reg = 0x201c0000; /* CL=2 */
414 else if (caslat == 3)
415 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
416 else if (caslat == 4)
417 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
Timur Tabie857a5b2006-11-28 12:09:35 -0600418
Xie Xiaobod61853c2007-02-14 18:27:17 +0800419 __asm__ __volatile__ ("sync");
Timur Tabibed85ca2006-10-31 18:13:36 -0600420
Xie Xiaobod61853c2007-02-14 18:27:17 +0800421 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
422 }
Timur Tabibed85ca2006-10-31 18:13:36 -0600423
Eran Libertyf046ccd2005-07-28 10:08:46 -0500424 /*
Xie Xiaobod61853c2007-02-14 18:27:17 +0800425 * Convert caslat clocks to DDR controller value.
426 * Force caslat_ctrl to be DDR Controller field-sized.
Eran Libertyf046ccd2005-07-28 10:08:46 -0500427 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800428 if (spd.mem_type == SPD_MEMTYPE_DDR) {
429 caslat_ctrl = (caslat + 1) & 0x07;
430 } else {
431 caslat_ctrl = (2 * caslat - 1) & 0x0f;
432 }
433
434 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
435 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
436 caslat, caslat_ctrl);
437
438 /*
439 * Timing Config 0.
440 * Avoid writing for DDR I.
441 */
442 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
443 unsigned char taxpd_clk = 8; /* By the book. */
444 unsigned char tmrd_clk = 2; /* By the book. */
445 unsigned char act_pd_exit = 2; /* Empirical? */
446 unsigned char pre_pd_exit = 6; /* Empirical? */
447
448 ddr->timing_cfg_0 = (0
449 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
450 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
451 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
452 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
453 );
454 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
455 }
456
457 /*
458 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
459 * use conservative value.
460 * For DDR II, they are bytes 36 and 37, in quarter nanos.
461 */
462
463 if (spd.mem_type == SPD_MEMTYPE_DDR) {
464 twr_clk = 3; /* Clocks */
465 twtr_clk = 1; /* Clocks */
466 } else {
467 twr_clk = picos_to_clk(spd.twr * 250);
468 twtr_clk = picos_to_clk(spd.twtr * 250);
469 }
470
471 /*
472 * Calculate Trfc, in picos.
473 * DDR I: Byte 42 straight up in ns.
474 * DDR II: Byte 40 and 42 swizzled some, in ns.
475 */
476 if (spd.mem_type == SPD_MEMTYPE_DDR) {
477 trfc = spd.trfc * 1000; /* up to ps */
478 } else {
479 unsigned int byte40_table_ps[8] = {
480 0,
481 250,
482 330,
483 500,
484 660,
485 750,
486 0,
487 0
488 };
489
490 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
491 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
492 }
493 trfc_clk = picos_to_clk(trfc);
494
495 /*
496 * Trcd, Byte 29, from quarter nanos to ps and clocks.
497 */
498 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
499
500 /*
501 * Convert trfc_clk to DDR controller fields. DDR I should
502 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
503 * 83xx controller has an extended REFREC field of three bits.
504 * The controller automatically adds 8 clocks to this value,
505 * so preadjust it down 8 first before splitting it up.
506 */
507 trfc_low = (trfc_clk - 8) & 0xf;
508 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500509
510 ddr->timing_cfg_1 =
Xie Xiaobod61853c2007-02-14 18:27:17 +0800511 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
512 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200513 (trcd_clk << 20 ) | /* ACTTORW */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800514 (caslat_ctrl << 16 ) | /* CASLAT */
515 (trfc_low << 12 ) | /* REFEC */
516 ((twr_clk & 0x07) << 8) | /* WRRREC */
517 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
518 ((twtr_clk & 0x07) << 0) /* WRTORD */
519 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500520
Xie Xiaobod61853c2007-02-14 18:27:17 +0800521 /*
522 * Additive Latency
523 * For DDR I, 0.
524 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
525 * which comes from Trcd, and also note that:
526 * add_lat + caslat must be >= 4
527 */
528 add_lat = 0;
529 if (spd.mem_type == SPD_MEMTYPE_DDR2
530 && (odt_wr_cfg || odt_rd_cfg)
531 && (caslat < 4)) {
532 add_lat = trcd_clk - 1;
533 if ((add_lat + caslat) < 4) {
534 add_lat = 0;
535 }
536 }
537
538 /*
539 * Write Data Delay
540 * Historically 0x2 == 4/8 clock delay.
541 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
542 */
543 wr_data_delay = 2;
544
545 /*
546 * Write Latency
547 * Read to Precharge
548 * Minimum CKE Pulse Width.
549 * Four Activate Window
550 */
551 if (spd.mem_type == SPD_MEMTYPE_DDR) {
552 /*
553 * This is a lie. It should really be 1, but if it is
554 * set to 1, bits overlap into the old controller's
555 * otherwise unused ACSM field. If we leave it 0, then
556 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
557 */
558 wr_lat = 0;
559
560 trtp_clk = 2; /* By the book. */
561 cke_min_clk = 1; /* By the book. */
562 four_act = 1; /* By the book. */
563
564 } else {
565 wr_lat = caslat - 1;
566
567 /* Convert SPD value from quarter nanos to picos. */
568 trtp_clk = picos_to_clk(spd.trtp * 250);
569
570 cke_min_clk = 3; /* By the book. */
571 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
572 }
573
574 /*
575 * Empirically set ~MCAS-to-preamble override for DDR 2.
576 * Your milage will vary.
577 */
578 cpo = 0;
579 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
Dave Liu061aad42008-01-10 23:09:33 +0800580 if (effective_data_rate == 266) {
581 cpo = 0x4; /* READ_LAT + 1/2 */
582 } else if (effective_data_rate == 333 || effective_data_rate == 400) {
Dave Liu19580e62007-09-18 12:37:57 +0800583 cpo = 0x7; /* READ_LAT + 5/4 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800584 } else {
585 /* Automatic calibration */
586 cpo = 0x1f;
587 }
588 }
589
590 ddr->timing_cfg_2 = (0
591 | ((add_lat & 0x7) << 28) /* ADD_LAT */
592 | ((cpo & 0x1f) << 23) /* CPO */
593 | ((wr_lat & 0x7) << 19) /* WR_LAT */
594 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
595 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
596 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
597 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
598 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500599
600 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
601 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
602
Dave Liuf6eda7f2006-10-25 14:41:21 -0500603 /* Check DIMM data bus width */
Lee Nipper3f9c5422008-04-10 09:35:06 -0500604 if (spd.dataw_lsb < 64) {
Dave Liu036575c2007-08-04 13:37:39 +0800605 if (spd.mem_type == SPD_MEMTYPE_DDR)
606 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
Dave Liu49bb5992007-08-10 15:48:59 +0800607 else
Dave Liu036575c2007-08-04 13:37:39 +0800608 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500609 debug("\n DDR DIMM: data bus width is 32 bit");
Dave Liu5f820432006-11-03 19:33:44 -0600610 } else {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500611 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500612 debug("\n DDR DIMM: data bus width is 64 bit");
Dave Liuf6eda7f2006-10-25 14:41:21 -0500613 }
614
615 /* Is this an ECC DDR chip? */
Timur Tabie857a5b2006-11-28 12:09:35 -0600616 if (spd.config == 0x02)
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500617 debug(" with ECC\n");
Timur Tabie857a5b2006-11-28 12:09:35 -0600618 else
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500619 debug(" without ECC\n");
Dave Liuf6eda7f2006-10-25 14:41:21 -0500620
621 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
622 Burst type is sequential
Eran Libertyf046ccd2005-07-28 10:08:46 -0500623 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800624 if (spd.mem_type == SPD_MEMTYPE_DDR) {
625 switch (caslat) {
Dave Liu5f820432006-11-03 19:33:44 -0600626 case 1:
627 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
628 break;
629 case 2:
630 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
631 break;
632 case 3:
633 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
634 break;
635 case 4:
636 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
637 break;
638 default:
639 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
640 return 0;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800641 }
642 } else {
643 mode_odt_enable = 0x0; /* Default disabled */
644 if (odt_wr_cfg || odt_rd_cfg) {
645 /*
646 * Bits 6 and 2 in Extended MRS(1)
647 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
648 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
649 */
650 mode_odt_enable = 0x40; /* 150 Ohm */
651 }
652
653 ddr->sdram_mode =
654 (0
655 | (1 << (16 + 10)) /* DQS Differential disable */
656 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
657 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
Xie Xiaobo6fbf2612007-03-09 19:08:25 +0800658 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800659 | (caslat << 4) /* caslat */
660 | (burstlen << 0) /* Burst length */
661 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500662 }
663 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
664
Xie Xiaobod61853c2007-02-14 18:27:17 +0800665 /*
666 * Clear EMRS2 and EMRS3.
667 */
668 ddr->sdram_mode2 = 0;
669 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
670
Dave Liu5f820432006-11-03 19:33:44 -0600671 switch (spd.refresh) {
672 case 0x00:
673 case 0x80:
674 refresh_clk = picos_to_clk(15625000);
675 break;
676 case 0x01:
677 case 0x81:
678 refresh_clk = picos_to_clk(3900000);
679 break;
680 case 0x02:
681 case 0x82:
682 refresh_clk = picos_to_clk(7800000);
683 break;
684 case 0x03:
685 case 0x83:
686 refresh_clk = picos_to_clk(31300000);
687 break;
688 case 0x04:
689 case 0x84:
690 refresh_clk = picos_to_clk(62500000);
691 break;
692 case 0x05:
693 case 0x85:
694 refresh_clk = picos_to_clk(125000000);
695 break;
696 default:
697 refresh_clk = 0x512;
698 break;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500699 }
700
701 /*
702 * Set BSTOPRE to 0x100 for page mode
703 * If auto-charge is used, set BSTOPRE = 0
704 */
Dave Liu5f820432006-11-03 19:33:44 -0600705 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500706 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
707
Xie Xiaobod61853c2007-02-14 18:27:17 +0800708 /*
709 * SDRAM Cfg 2
710 */
711 odt_cfg = 0;
Dave Liu19580e62007-09-18 12:37:57 +0800712#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
Xie Xiaobod61853c2007-02-14 18:27:17 +0800713 if (odt_rd_cfg | odt_wr_cfg) {
714 odt_cfg = 0x2; /* ODT to IOs during reads */
715 }
Dave Liu19580e62007-09-18 12:37:57 +0800716#endif
Xie Xiaobod61853c2007-02-14 18:27:17 +0800717 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
718 ddr->sdram_cfg2 = (0
719 | (0 << 26) /* True DQS */
720 | (odt_cfg << 21) /* ODT only read */
721 | (1 << 12) /* 1 refresh at a time */
722 );
723
724 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
725 }
726
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200727#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
728 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500729#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500730 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100731
Eran Libertyf046ccd2005-07-28 10:08:46 -0500732 asm("sync;isync");
733
Dave Liuf6eda7f2006-10-25 14:41:21 -0500734 udelay(600);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500735
736 /*
Dave Liu5f820432006-11-03 19:33:44 -0600737 * Figure out the settings for the sdram_cfg register. Build up
738 * the value in 'sdram_cfg' before writing since the write into
Eran Libertyf046ccd2005-07-28 10:08:46 -0500739 * the register will actually enable the memory controller, and all
740 * settings must be done before enabling.
741 *
742 * sdram_cfg[0] = 1 (ddr sdram logic enable)
743 * sdram_cfg[1] = 1 (self-refresh-enable)
Xie Xiaobod61853c2007-02-14 18:27:17 +0800744 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
745 * 010 DDR 1 SDRAM
746 * 011 DDR 2 SDRAM
Dave Liuf6eda7f2006-10-25 14:41:21 -0500747 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
748 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500749 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800750 if (spd.mem_type == SPD_MEMTYPE_DDR)
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500751 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800752 else
Kim Phillips4cc1cd52007-08-17 09:30:00 -0500753 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800754
755 sdram_cfg = (0
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500756 | SDRAM_CFG_MEM_EN /* DDR enable */
757 | SDRAM_CFG_SREN /* Self refresh */
758 | sdram_type /* SDRAM type */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800759 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500760
Dave Liuf6eda7f2006-10-25 14:41:21 -0500761 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
Timur Tabie857a5b2006-11-28 12:09:35 -0600762 if (spd.mod_attr & 0x02)
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500763 sdram_cfg |= SDRAM_CFG_RD_EN;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500764
Dave Liuf6eda7f2006-10-25 14:41:21 -0500765 /* The DIMM is 32bit width */
Lee Nipper3f9c5422008-04-10 09:35:06 -0500766 if (spd.dataw_lsb < 64) {
Dave Liu036575c2007-08-04 13:37:39 +0800767 if (spd.mem_type == SPD_MEMTYPE_DDR)
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500768 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
Dave Liu036575c2007-08-04 13:37:39 +0800769 if (spd.mem_type == SPD_MEMTYPE_DDR2)
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500770 sdram_cfg |= SDRAM_CFG_32_BE;
Dave Liu036575c2007-08-04 13:37:39 +0800771 }
Timur Tabie857a5b2006-11-28 12:09:35 -0600772
Dave Liuf6eda7f2006-10-25 14:41:21 -0500773 ddrc_ecc_enable = 0;
774
Eran Libertyf046ccd2005-07-28 10:08:46 -0500775#if defined(CONFIG_DDR_ECC)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500776 /* Enable ECC with sdram_cfg[2] */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500777 if (spd.config == 0x02) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500778 sdram_cfg |= 0x20000000;
779 ddrc_ecc_enable = 1;
780 /* disable error detection */
781 ddr->err_disable = ~ECC_ERROR_ENABLE;
782 /* set single bit error threshold to maximum value,
783 * reset counter to zero */
784 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
Dave Liu5f820432006-11-03 19:33:44 -0600785 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500786 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500787
788 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
789 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500790#endif
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500791 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500792
793#if defined(CONFIG_DDR_2T_TIMING)
794 /*
795 * Enable 2T timing by setting sdram_cfg[16].
796 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500797 sdram_cfg |= SDRAM_CFG_2T_EN;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500798#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500799 /* Enable controller, and GO! */
800 ddr->sdram_cfg = sdram_cfg;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500801 asm("sync;isync");
802 udelay(500);
803
804 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100805 return memsize; /*in MBytes*/
Eran Libertyf046ccd2005-07-28 10:08:46 -0500806}
Eran Libertyf046ccd2005-07-28 10:08:46 -0500807#endif /* CONFIG_SPD_EEPROM */
808
Dave Liuf6eda7f2006-10-25 14:41:21 -0500809#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500810/*
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100811 * Use timebase counter, get_timer() is not availabe
812 * at this point of initialization yet.
813 */
814static __inline__ unsigned long get_tbms (void)
815{
816 unsigned long tbl;
817 unsigned long tbu1, tbu2;
818 unsigned long ms;
819 unsigned long long tmp;
820
821 ulong tbclk = get_tbclk();
822
823 /* get the timebase ticks */
824 do {
825 asm volatile ("mftbu %0":"=r" (tbu1):);
826 asm volatile ("mftb %0":"=r" (tbl):);
827 asm volatile ("mftbu %0":"=r" (tbu2):);
828 } while (tbu1 != tbu2);
829
830 /* convert ticks to ms */
831 tmp = (unsigned long long)(tbu1);
832 tmp = (tmp << 32);
833 tmp += (unsigned long long)(tbl);
834 ms = tmp/(tbclk/1000);
835
836 return ms;
837}
838
839/*
Eran Libertyf046ccd2005-07-28 10:08:46 -0500840 * Initialize all of memory for ECC, then enable errors.
841 */
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200842/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100843void ddr_enable_ecc(unsigned int dram_size)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500844{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200845 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500846 volatile ddr83xx_t *ddr= &immap->ddr;
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100847 unsigned long t_start, t_end;
Dave Liu90f30a72006-11-02 18:05:50 -0600848 register u64 *p;
849 register uint size;
850 unsigned int pattern[2];
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100851#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
852 uint i;
853#endif
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100854 icache_enable();
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100855 t_start = get_tbms();
Dave Liu90f30a72006-11-02 18:05:50 -0600856 pattern[0] = 0xdeadbeef;
857 pattern[1] = 0xdeadbeef;
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100858
859#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
Dave Liu90f30a72006-11-02 18:05:50 -0600860 debug("ddr init: CPU FP write method\n");
861 size = dram_size;
862 for (p = 0; p < (u64*)(size); p++) {
863 ppcDWstore((u32*)p, pattern);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500864 }
Dave Liu90f30a72006-11-02 18:05:50 -0600865 __asm__ __volatile__ ("sync");
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100866#else
Dave Liu90f30a72006-11-02 18:05:50 -0600867 debug("ddr init: DMA method\n");
868 size = 0x2000;
869 for (p = 0; p < (u64*)(size); p++) {
870 ppcDWstore((u32*)p, pattern);
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100871 }
Dave Liu90f30a72006-11-02 18:05:50 -0600872 __asm__ __volatile__ ("sync");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500873
Dave Liu90f30a72006-11-02 18:05:50 -0600874 /* Initialise DMA for direct transfer */
875 dma_init();
876 /* Start DMA to transfer */
Dave Liu5f820432006-11-03 19:33:44 -0600877 dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
878 dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
879 dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
880 dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
881 dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
882 dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
883 dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
884 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
885 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
886 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500887
888 for (i = 1; i < dram_size / 0x800000; i++) {
889 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
890 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500891#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500892
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100893 t_end = get_tbms();
894 icache_disable();
895
896 debug("\nREADY!!\n");
897 debug("ddr init duration: %ld ms\n", t_end - t_start);
898
899 /* Clear All ECC Errors */
900 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
901 ddr->err_detect |= ECC_ERROR_DETECT_MME;
902 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
903 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
904 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
905 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
906 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
907 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
908
909 /* Disable ECC-Interrupts */
910 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
911
912 /* Enable errors for ECC */
913 ddr->err_disable &= ECC_ERROR_ENABLE;
914
915 __asm__ __volatile__ ("sync");
916 __asm__ __volatile__ ("isync");
917}
Eran Libertyf046ccd2005-07-28 10:08:46 -0500918#endif /* CONFIG_DDR_ECC */