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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Dave Liuf6eda7f2006-10-25 14:41:21 -05002 * (C) Copyright 2006 Freescale Semiconductor, Inc.
3 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +01004 * (C) Copyright 2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +02006 *
Dave Liu5f820432006-11-03 19:33:44 -06007 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05008 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
Eran Libertyf046ccd2005-07-28 10:08:46 -050028 */
29
30#include <common.h>
31#include <asm/processor.h>
32#include <i2c.h>
33#include <spd.h>
34#include <asm/mmu.h>
35#include <spd_sdram.h>
36
37#ifdef CONFIG_SPD_EEPROM
38
Timur Tabie857a5b2006-11-28 12:09:35 -060039DECLARE_GLOBAL_DATA_PTR;
40
Dave Liuf6eda7f2006-10-25 14:41:21 -050041#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
Eran Libertyf046ccd2005-07-28 10:08:46 -050042extern void dma_init(void);
43extern uint dma_check(void);
44extern int dma_xfer(void *dest, uint count, void *src);
45#endif
46
Eran Libertyf046ccd2005-07-28 10:08:46 -050047#ifndef CFG_READ_SPD
48#define CFG_READ_SPD i2c_read
49#endif
50
Eran Libertyf046ccd2005-07-28 10:08:46 -050051/*
52 * Convert picoseconds into clock cycles (rounding up if needed).
53 */
Eran Libertyf046ccd2005-07-28 10:08:46 -050054int
55picos_to_clk(int picos)
56{
Dave Liuf6eda7f2006-10-25 14:41:21 -050057 unsigned int ddr_bus_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -050058 int clks;
59
Timur Tabie857a5b2006-11-28 12:09:35 -060060 ddr_bus_clk = gd->ddr_clk >> 1;
Xie Xiaobo6fbf2612007-03-09 19:08:25 +080061 clks = picos / (1000000000 / (ddr_bus_clk / 1000));
62 if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
Dave Liuf6eda7f2006-10-25 14:41:21 -050063 clks++;
Eran Libertyf046ccd2005-07-28 10:08:46 -050064
65 return clks;
66}
67
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +010068unsigned int banksize(unsigned char row_dens)
Eran Libertyf046ccd2005-07-28 10:08:46 -050069{
70 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
71}
72
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +010073int read_spd(uint addr)
74{
75 return ((int) addr);
76}
77
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010078#undef SPD_DEBUG
79#ifdef SPD_DEBUG
80static void spd_debug(spd_eeprom_t *spd)
81{
82 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
83 printf ("SPD size: %d\n", spd->info_size);
84 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
85 printf ("Memory type: %d\n", spd->mem_type);
86 printf ("Row addr: %d\n", spd->nrow_addr);
87 printf ("Column addr: %d\n", spd->ncol_addr);
88 printf ("# of rows: %d\n", spd->nrows);
89 printf ("Row density: %d\n", spd->row_dens);
90 printf ("# of banks: %d\n", spd->nbanks);
91 printf ("Data width: %d\n",
92 256 * spd->dataw_msb + spd->dataw_lsb);
93 printf ("Chip width: %d\n", spd->primw);
94 printf ("Refresh rate: %02X\n", spd->refresh);
95 printf ("CAS latencies: %02X\n", spd->cas_lat);
96 printf ("Write latencies: %02X\n", spd->write_lat);
97 printf ("tRP: %d\n", spd->trp);
98 printf ("tRCD: %d\n", spd->trcd);
99 printf ("\n");
100}
101#endif /* SPD_DEBUG */
102
103long int spd_sdram()
Eran Libertyf046ccd2005-07-28 10:08:46 -0500104{
Timur Tabid239d742006-11-03 12:00:28 -0600105 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500106 volatile ddr83xx_t *ddr = &immap->ddr;
107 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
Eran Libertyf046ccd2005-07-28 10:08:46 -0500108 spd_eeprom_t spd;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800109 unsigned int n_ranks;
110 unsigned int odt_rd_cfg, odt_wr_cfg;
111 unsigned char twr_clk, twtr_clk;
112 unsigned char sdram_type;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500113 unsigned int memsize;
114 unsigned int law_size;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500115 unsigned char caslat, caslat_ctrl;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800116 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
117 unsigned int trcd_clk, trtp_clk;
118 unsigned char cke_min_clk;
119 unsigned char add_lat, wr_lat;
120 unsigned char wr_data_delay;
121 unsigned char four_act;
122 unsigned char cpo;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500123 unsigned char burstlen;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800124 unsigned char odt_cfg, mode_odt_enable;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500125 unsigned int max_bus_clk;
126 unsigned int max_data_rate, effective_data_rate;
127 unsigned int ddrc_clk;
128 unsigned int refresh_clk;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800129 unsigned int sdram_cfg;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500130 unsigned int ddrc_ecc_enable;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800131 unsigned int pvr = get_pvr();
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500132
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100133 /* Read SPD parameters with I2C */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500134 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100135#ifdef SPD_DEBUG
136 spd_debug(&spd);
137#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500138 /* Check the memory type */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800139 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500140 printf("DDR: Module mem type is %02X\n", spd.mem_type);
141 return 0;
142 }
143
144 /* Check the number of physical bank */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800145 if (spd.mem_type == SPD_MEMTYPE_DDR) {
146 n_ranks = spd.nrows;
147 } else {
148 n_ranks = (spd.nrows & 0x7) + 1;
149 }
150
151 if (n_ranks > 2) {
152 printf("DDR: The number of physical bank is %02X\n", n_ranks);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500153 return 0;
154 }
155
Dave Liuf6eda7f2006-10-25 14:41:21 -0500156 /* Check if the number of row of the module is in the range of DDRC */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800157 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500158 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
159 spd.nrow_addr);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500160 return 0;
161 }
162
Dave Liuf6eda7f2006-10-25 14:41:21 -0500163 /* Check if the number of col of the module is in the range of DDRC */
164 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
165 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
166 spd.ncol_addr);
167 return 0;
168 }
Xie Xiaobod61853c2007-02-14 18:27:17 +0800169
170#ifdef CFG_DDRCDR_VALUE
171 /*
172 * Adjust DDR II IO voltage biasing. It just makes it work.
173 */
174 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
175 immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
176 }
177#endif
178
179 /*
180 * ODT configuration recommendation from DDR Controller Chapter.
181 */
182 odt_rd_cfg = 0; /* Never assert ODT */
183 odt_wr_cfg = 0; /* Never assert ODT */
184 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
185 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
186 }
187
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100188 /* Setup DDR chip select register */
Dave Liu5f820432006-11-03 19:33:44 -0600189#ifdef CFG_83XX_DDR_USES_CS0
190 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
191 ddr->cs_config[0] = ( 1 << 31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800192 | (odt_rd_cfg << 20)
193 | (odt_wr_cfg << 16)
Dave Liu5f820432006-11-03 19:33:44 -0600194 | (spd.nrow_addr - 12) << 8
195 | (spd.ncol_addr - 8) );
196 debug("\n");
197 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
198 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
199
Xie Xiaobod61853c2007-02-14 18:27:17 +0800200 if (n_ranks == 2) {
Dave Liu5f820432006-11-03 19:33:44 -0600201 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
202 | ((banksize(spd.row_dens) >> 23) - 1) );
203 ddr->cs_config[1] = ( 1<<31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800204 | (odt_rd_cfg << 20)
205 | (odt_wr_cfg << 16)
Dave Liu5f820432006-11-03 19:33:44 -0600206 | (spd.nrow_addr-12) << 8
207 | (spd.ncol_addr-8) );
208 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
209 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
210 }
211
212#else
Eran Libertyf046ccd2005-07-28 10:08:46 -0500213 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
214 ddr->cs_config[2] = ( 1 << 31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800215 | (odt_rd_cfg << 20)
216 | (odt_wr_cfg << 16)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500217 | (spd.nrow_addr - 12) << 8
218 | (spd.ncol_addr - 8) );
219 debug("\n");
220 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
221 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500222
Xie Xiaobod61853c2007-02-14 18:27:17 +0800223 if (n_ranks == 2) {
Eran Libertyf046ccd2005-07-28 10:08:46 -0500224 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
225 | ((banksize(spd.row_dens) >> 23) - 1) );
226 ddr->cs_config[3] = ( 1<<31
Xie Xiaobod61853c2007-02-14 18:27:17 +0800227 | (odt_rd_cfg << 20)
228 | (odt_wr_cfg << 16)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500229 | (spd.nrow_addr-12) << 8
230 | (spd.ncol_addr-8) );
231 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
232 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
233 }
Timur Tabi2ad6b512006-10-31 18:44:42 -0600234#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500235
Eran Libertyf046ccd2005-07-28 10:08:46 -0500236 /*
237 * Figure out memory size in Megabytes.
238 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800239 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500240
241 /*
242 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
243 */
244 law_size = 19 + __ilog2(memsize);
245
246 /*
247 * Set up LAWBAR for all of DDR.
248 */
249 ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
250 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
251 debug("DDR:bar=0x%08x\n", ecm->bar);
252 debug("DDR:ar=0x%08x\n", ecm->ar);
253
254 /*
Dave Liuf6eda7f2006-10-25 14:41:21 -0500255 * Find the largest CAS by locating the highest 1 bit
256 * in the spd.cas_lat field. Translate it to a DDR
257 * controller field value:
258 *
Xie Xiaobod61853c2007-02-14 18:27:17 +0800259 * CAS Lat DDR I DDR II Ctrl
260 * Clocks SPD Bit SPD Bit Value
261 * ------- ------- ------- -----
262 * 1.0 0 0001
263 * 1.5 1 0010
264 * 2.0 2 2 0011
265 * 2.5 3 0100
266 * 3.0 4 3 0101
267 * 3.5 5 0110
268 * 4.0 6 4 0111
269 * 4.5 1000
270 * 5.0 5 1001
Eran Libertyf046ccd2005-07-28 10:08:46 -0500271 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500272 caslat = __ilog2(spd.cas_lat);
Xie Xiaobod61853c2007-02-14 18:27:17 +0800273 if ((spd.mem_type == SPD_MEMTYPE_DDR)
274 && (caslat > 6)) {
275 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
276 return 0;
277 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
278 && (caslat < 2 || caslat > 5)) {
279 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
280 spd.cas_lat);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500281 return 0;
282 }
Xie Xiaobod61853c2007-02-14 18:27:17 +0800283 debug("DDR: caslat SPD bit is %d\n", caslat);
284
Dave Liuf6eda7f2006-10-25 14:41:21 -0500285 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
286 + (spd.clk_cycle & 0x0f));
287 max_data_rate = max_bus_clk * 2;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500288
Dave Liuf6eda7f2006-10-25 14:41:21 -0500289 debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500290
Timur Tabie857a5b2006-11-28 12:09:35 -0600291 ddrc_clk = gd->ddr_clk / 1000000;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800292 effective_data_rate = 0;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500293
Xie Xiaobod61853c2007-02-14 18:27:17 +0800294 if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
295 if (ddrc_clk <= 460 && ddrc_clk > 350) {
296 /* DDR controller clk at 350~460 */
Dave Liu5f820432006-11-03 19:33:44 -0600297 effective_data_rate = 400; /* 5ns */
298 caslat = caslat;
299 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
300 /* DDR controller clk at 280~350 */
301 effective_data_rate = 333; /* 6ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600302 if (spd.clk_cycle2 == 0x60)
Dave Liu5f820432006-11-03 19:33:44 -0600303 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600304 else
Dave Liu5f820432006-11-03 19:33:44 -0600305 caslat = caslat;
Dave Liu5f820432006-11-03 19:33:44 -0600306 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
307 /* DDR controller clk at 230~280 */
308 effective_data_rate = 266; /* 7.5ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600309 if (spd.clk_cycle3 == 0x75)
Dave Liu5f820432006-11-03 19:33:44 -0600310 caslat = caslat - 2;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800311 else if (spd.clk_cycle2 == 0x75)
Dave Liu5f820432006-11-03 19:33:44 -0600312 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600313 else
Dave Liu5f820432006-11-03 19:33:44 -0600314 caslat = caslat;
Dave Liu5f820432006-11-03 19:33:44 -0600315 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
316 /* DDR controller clk at 90~230 */
317 effective_data_rate = 200; /* 10ns */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800318 if (spd.clk_cycle3 == 0xa0)
Dave Liu5f820432006-11-03 19:33:44 -0600319 caslat = caslat - 2;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800320 else if (spd.clk_cycle2 == 0xa0)
Dave Liu5f820432006-11-03 19:33:44 -0600321 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600322 else
Dave Liu5f820432006-11-03 19:33:44 -0600323 caslat = caslat;
Dave Liu5f820432006-11-03 19:33:44 -0600324 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500325 } else if (max_data_rate >= 323) { /* it is DDR 333 */
326 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liu5f820432006-11-03 19:33:44 -0600327 /* DDR controller clk at 280~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500328 effective_data_rate = 333; /* 6ns */
329 caslat = caslat;
330 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600331 /* DDR controller clk at 230~280 */
332 effective_data_rate = 266; /* 7.5ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600333 if (spd.clk_cycle2 == 0x75)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500334 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600335 else
Dave Liu5f820432006-11-03 19:33:44 -0600336 caslat = caslat;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500337 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600338 /* DDR controller clk at 90~230 */
339 effective_data_rate = 200; /* 10ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600340 if (spd.clk_cycle3 == 0xa0)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500341 caslat = caslat - 2;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800342 else if (spd.clk_cycle2 == 0xa0)
Dave Liu5f820432006-11-03 19:33:44 -0600343 caslat = caslat - 1;
Timur Tabie857a5b2006-11-28 12:09:35 -0600344 else
Dave Liu5f820432006-11-03 19:33:44 -0600345 caslat = caslat;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500346 }
347 } else if (max_data_rate >= 256) { /* it is DDR 266 */
348 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liu5f820432006-11-03 19:33:44 -0600349 /* DDR controller clk at 280~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500350 printf("DDR: DDR controller freq is more than "
351 "max data rate of the module\n");
352 return 0;
353 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600354 /* DDR controller clk at 230~280 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500355 effective_data_rate = 266; /* 7.5ns */
356 caslat = caslat;
357 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600358 /* DDR controller clk at 90~230 */
359 effective_data_rate = 200; /* 10ns */
Timur Tabie857a5b2006-11-28 12:09:35 -0600360 if (spd.clk_cycle2 == 0xa0)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500361 caslat = caslat - 1;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500362 }
363 } else if (max_data_rate >= 190) { /* it is DDR 200 */
364 if (ddrc_clk <= 350 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600365 /* DDR controller clk at 230~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500366 printf("DDR: DDR controller freq is more than "
367 "max data rate of the module\n");
368 return 0;
369 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600370 /* DDR controller clk at 90~230 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500371 effective_data_rate = 200; /* 10ns */
372 caslat = caslat;
373 }
Eran Libertyf046ccd2005-07-28 10:08:46 -0500374 }
375
Dave Liu5f820432006-11-03 19:33:44 -0600376 debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
377 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
Timur Tabibed85ca2006-10-31 18:13:36 -0600378
Dave Liu5f820432006-11-03 19:33:44 -0600379 /*
380 * Errata DDR6 work around: input enable 2 cycles earlier.
381 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
382 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800383 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
384 if (caslat == 2)
385 ddr->debug_reg = 0x201c0000; /* CL=2 */
386 else if (caslat == 3)
387 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
388 else if (caslat == 4)
389 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
Timur Tabie857a5b2006-11-28 12:09:35 -0600390
Xie Xiaobod61853c2007-02-14 18:27:17 +0800391 __asm__ __volatile__ ("sync");
Timur Tabibed85ca2006-10-31 18:13:36 -0600392
Xie Xiaobod61853c2007-02-14 18:27:17 +0800393 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
394 }
Timur Tabibed85ca2006-10-31 18:13:36 -0600395
Eran Libertyf046ccd2005-07-28 10:08:46 -0500396 /*
Xie Xiaobod61853c2007-02-14 18:27:17 +0800397 * Convert caslat clocks to DDR controller value.
398 * Force caslat_ctrl to be DDR Controller field-sized.
Eran Libertyf046ccd2005-07-28 10:08:46 -0500399 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800400 if (spd.mem_type == SPD_MEMTYPE_DDR) {
401 caslat_ctrl = (caslat + 1) & 0x07;
402 } else {
403 caslat_ctrl = (2 * caslat - 1) & 0x0f;
404 }
405
406 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
407 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
408 caslat, caslat_ctrl);
409
410 /*
411 * Timing Config 0.
412 * Avoid writing for DDR I.
413 */
414 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
415 unsigned char taxpd_clk = 8; /* By the book. */
416 unsigned char tmrd_clk = 2; /* By the book. */
417 unsigned char act_pd_exit = 2; /* Empirical? */
418 unsigned char pre_pd_exit = 6; /* Empirical? */
419
420 ddr->timing_cfg_0 = (0
421 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
422 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
423 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
424 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
425 );
426 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
427 }
428
429 /*
430 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
431 * use conservative value.
432 * For DDR II, they are bytes 36 and 37, in quarter nanos.
433 */
434
435 if (spd.mem_type == SPD_MEMTYPE_DDR) {
436 twr_clk = 3; /* Clocks */
437 twtr_clk = 1; /* Clocks */
438 } else {
439 twr_clk = picos_to_clk(spd.twr * 250);
440 twtr_clk = picos_to_clk(spd.twtr * 250);
441 }
442
443 /*
444 * Calculate Trfc, in picos.
445 * DDR I: Byte 42 straight up in ns.
446 * DDR II: Byte 40 and 42 swizzled some, in ns.
447 */
448 if (spd.mem_type == SPD_MEMTYPE_DDR) {
449 trfc = spd.trfc * 1000; /* up to ps */
450 } else {
451 unsigned int byte40_table_ps[8] = {
452 0,
453 250,
454 330,
455 500,
456 660,
457 750,
458 0,
459 0
460 };
461
462 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
463 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
464 }
465 trfc_clk = picos_to_clk(trfc);
466
467 /*
468 * Trcd, Byte 29, from quarter nanos to ps and clocks.
469 */
470 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
471
472 /*
473 * Convert trfc_clk to DDR controller fields. DDR I should
474 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
475 * 83xx controller has an extended REFREC field of three bits.
476 * The controller automatically adds 8 clocks to this value,
477 * so preadjust it down 8 first before splitting it up.
478 */
479 trfc_low = (trfc_clk - 8) & 0xf;
480 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500481
482 ddr->timing_cfg_1 =
Xie Xiaobod61853c2007-02-14 18:27:17 +0800483 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
484 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
485 (trcd_clk << 20 ) | /* ACTTORW */
486 (caslat_ctrl << 16 ) | /* CASLAT */
487 (trfc_low << 12 ) | /* REFEC */
488 ((twr_clk & 0x07) << 8) | /* WRRREC */
489 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
490 ((twtr_clk & 0x07) << 0) /* WRTORD */
491 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500492
Xie Xiaobod61853c2007-02-14 18:27:17 +0800493 /*
494 * Additive Latency
495 * For DDR I, 0.
496 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
497 * which comes from Trcd, and also note that:
498 * add_lat + caslat must be >= 4
499 */
500 add_lat = 0;
501 if (spd.mem_type == SPD_MEMTYPE_DDR2
502 && (odt_wr_cfg || odt_rd_cfg)
503 && (caslat < 4)) {
504 add_lat = trcd_clk - 1;
505 if ((add_lat + caslat) < 4) {
506 add_lat = 0;
507 }
508 }
509
510 /*
511 * Write Data Delay
512 * Historically 0x2 == 4/8 clock delay.
513 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
514 */
515 wr_data_delay = 2;
516
517 /*
518 * Write Latency
519 * Read to Precharge
520 * Minimum CKE Pulse Width.
521 * Four Activate Window
522 */
523 if (spd.mem_type == SPD_MEMTYPE_DDR) {
524 /*
525 * This is a lie. It should really be 1, but if it is
526 * set to 1, bits overlap into the old controller's
527 * otherwise unused ACSM field. If we leave it 0, then
528 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
529 */
530 wr_lat = 0;
531
532 trtp_clk = 2; /* By the book. */
533 cke_min_clk = 1; /* By the book. */
534 four_act = 1; /* By the book. */
535
536 } else {
537 wr_lat = caslat - 1;
538
539 /* Convert SPD value from quarter nanos to picos. */
540 trtp_clk = picos_to_clk(spd.trtp * 250);
541
542 cke_min_clk = 3; /* By the book. */
543 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
544 }
545
546 /*
547 * Empirically set ~MCAS-to-preamble override for DDR 2.
548 * Your milage will vary.
549 */
550 cpo = 0;
551 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
552 if (effective_data_rate == 266 || effective_data_rate == 333) {
553 cpo = 0x7; /* READ_LAT + 5/4 */
554 } else if (effective_data_rate == 400) {
555 cpo = 0x9; /* READ_LAT + 7/4 */
556 } else {
557 /* Automatic calibration */
558 cpo = 0x1f;
559 }
560 }
561
562 ddr->timing_cfg_2 = (0
563 | ((add_lat & 0x7) << 28) /* ADD_LAT */
564 | ((cpo & 0x1f) << 23) /* CPO */
565 | ((wr_lat & 0x7) << 19) /* WR_LAT */
566 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
567 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
568 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
569 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
570 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500571
572 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
573 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
574
Dave Liuf6eda7f2006-10-25 14:41:21 -0500575 /* Check DIMM data bus width */
Dave Liu5f820432006-11-03 19:33:44 -0600576 if (spd.dataw_lsb == 0x20) {
Dave Liu036575c2007-08-04 13:37:39 +0800577 if (spd.mem_type == SPD_MEMTYPE_DDR)
578 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
579 if (spd.mem_type == SPD_MEMTYPE_DDR2)
580 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500581 printf("\n DDR DIMM: data bus width is 32 bit");
Dave Liu5f820432006-11-03 19:33:44 -0600582 } else {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500583 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
584 printf("\n DDR DIMM: data bus width is 64 bit");
585 }
586
587 /* Is this an ECC DDR chip? */
Timur Tabie857a5b2006-11-28 12:09:35 -0600588 if (spd.config == 0x02)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500589 printf(" with ECC\n");
Timur Tabie857a5b2006-11-28 12:09:35 -0600590 else
Dave Liuf6eda7f2006-10-25 14:41:21 -0500591 printf(" without ECC\n");
592
593 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
594 Burst type is sequential
Eran Libertyf046ccd2005-07-28 10:08:46 -0500595 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800596 if (spd.mem_type == SPD_MEMTYPE_DDR) {
597 switch (caslat) {
Dave Liu5f820432006-11-03 19:33:44 -0600598 case 1:
599 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
600 break;
601 case 2:
602 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
603 break;
604 case 3:
605 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
606 break;
607 case 4:
608 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
609 break;
610 default:
611 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
612 return 0;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800613 }
614 } else {
615 mode_odt_enable = 0x0; /* Default disabled */
616 if (odt_wr_cfg || odt_rd_cfg) {
617 /*
618 * Bits 6 and 2 in Extended MRS(1)
619 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
620 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
621 */
622 mode_odt_enable = 0x40; /* 150 Ohm */
623 }
624
625 ddr->sdram_mode =
626 (0
627 | (1 << (16 + 10)) /* DQS Differential disable */
628 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
629 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
Xie Xiaobo6fbf2612007-03-09 19:08:25 +0800630 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800631 | (caslat << 4) /* caslat */
632 | (burstlen << 0) /* Burst length */
633 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500634 }
635 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
636
Xie Xiaobod61853c2007-02-14 18:27:17 +0800637 /*
638 * Clear EMRS2 and EMRS3.
639 */
640 ddr->sdram_mode2 = 0;
641 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
642
Dave Liu5f820432006-11-03 19:33:44 -0600643 switch (spd.refresh) {
644 case 0x00:
645 case 0x80:
646 refresh_clk = picos_to_clk(15625000);
647 break;
648 case 0x01:
649 case 0x81:
650 refresh_clk = picos_to_clk(3900000);
651 break;
652 case 0x02:
653 case 0x82:
654 refresh_clk = picos_to_clk(7800000);
655 break;
656 case 0x03:
657 case 0x83:
658 refresh_clk = picos_to_clk(31300000);
659 break;
660 case 0x04:
661 case 0x84:
662 refresh_clk = picos_to_clk(62500000);
663 break;
664 case 0x05:
665 case 0x85:
666 refresh_clk = picos_to_clk(125000000);
667 break;
668 default:
669 refresh_clk = 0x512;
670 break;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500671 }
672
673 /*
674 * Set BSTOPRE to 0x100 for page mode
675 * If auto-charge is used, set BSTOPRE = 0
676 */
Dave Liu5f820432006-11-03 19:33:44 -0600677 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500678 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
679
Xie Xiaobod61853c2007-02-14 18:27:17 +0800680 /*
681 * SDRAM Cfg 2
682 */
683 odt_cfg = 0;
684 if (odt_rd_cfg | odt_wr_cfg) {
685 odt_cfg = 0x2; /* ODT to IOs during reads */
686 }
687 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
688 ddr->sdram_cfg2 = (0
689 | (0 << 26) /* True DQS */
690 | (odt_cfg << 21) /* ODT only read */
691 | (1 << 12) /* 1 refresh at a time */
692 );
693
694 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
695 }
696
Paul Gortmaker91e25762007-01-16 11:38:14 -0500697#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
698 ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500699#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500700 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100701
Eran Libertyf046ccd2005-07-28 10:08:46 -0500702 asm("sync;isync");
703
Dave Liuf6eda7f2006-10-25 14:41:21 -0500704 udelay(600);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500705
706 /*
Dave Liu5f820432006-11-03 19:33:44 -0600707 * Figure out the settings for the sdram_cfg register. Build up
708 * the value in 'sdram_cfg' before writing since the write into
Eran Libertyf046ccd2005-07-28 10:08:46 -0500709 * the register will actually enable the memory controller, and all
710 * settings must be done before enabling.
711 *
712 * sdram_cfg[0] = 1 (ddr sdram logic enable)
713 * sdram_cfg[1] = 1 (self-refresh-enable)
Xie Xiaobod61853c2007-02-14 18:27:17 +0800714 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
715 * 010 DDR 1 SDRAM
716 * 011 DDR 2 SDRAM
Dave Liuf6eda7f2006-10-25 14:41:21 -0500717 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
718 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500719 */
Xie Xiaobod61853c2007-02-14 18:27:17 +0800720 if (spd.mem_type == SPD_MEMTYPE_DDR)
721 sdram_type = 2;
722 else
723 sdram_type = 3;
724
725 sdram_cfg = (0
726 | (1 << 31) /* DDR enable */
727 | (1 << 30) /* Self refresh */
728 | (sdram_type << 24) /* SDRAM type */
729 );
Eran Libertyf046ccd2005-07-28 10:08:46 -0500730
Dave Liuf6eda7f2006-10-25 14:41:21 -0500731 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
Timur Tabie857a5b2006-11-28 12:09:35 -0600732 if (spd.mod_attr & 0x02)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500733 sdram_cfg |= 0x10000000;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500734
Dave Liuf6eda7f2006-10-25 14:41:21 -0500735 /* The DIMM is 32bit width */
Dave Liu036575c2007-08-04 13:37:39 +0800736 if (spd.dataw_lsb == 0x20) {
737 if (spd.mem_type == SPD_MEMTYPE_DDR)
738 sdram_cfg |= 0x000C0000;
739 if (spd.mem_type == SPD_MEMTYPE_DDR2)
740 sdram_cfg |= 0x00080000;
741 }
Timur Tabie857a5b2006-11-28 12:09:35 -0600742
Dave Liuf6eda7f2006-10-25 14:41:21 -0500743 ddrc_ecc_enable = 0;
744
Eran Libertyf046ccd2005-07-28 10:08:46 -0500745#if defined(CONFIG_DDR_ECC)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500746 /* Enable ECC with sdram_cfg[2] */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500747 if (spd.config == 0x02) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500748 sdram_cfg |= 0x20000000;
749 ddrc_ecc_enable = 1;
750 /* disable error detection */
751 ddr->err_disable = ~ECC_ERROR_ENABLE;
752 /* set single bit error threshold to maximum value,
753 * reset counter to zero */
754 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
Dave Liu5f820432006-11-03 19:33:44 -0600755 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500756 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500757
758 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
759 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500760#endif
Dave Liu5f820432006-11-03 19:33:44 -0600761 printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500762
763#if defined(CONFIG_DDR_2T_TIMING)
764 /*
765 * Enable 2T timing by setting sdram_cfg[16].
766 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500767 sdram_cfg |= SDRAM_CFG_2T_EN;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500768#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500769 /* Enable controller, and GO! */
770 ddr->sdram_cfg = sdram_cfg;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500771 asm("sync;isync");
772 udelay(500);
773
774 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100775 return memsize; /*in MBytes*/
Eran Libertyf046ccd2005-07-28 10:08:46 -0500776}
Eran Libertyf046ccd2005-07-28 10:08:46 -0500777#endif /* CONFIG_SPD_EEPROM */
778
Dave Liuf6eda7f2006-10-25 14:41:21 -0500779#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500780/*
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100781 * Use timebase counter, get_timer() is not availabe
782 * at this point of initialization yet.
783 */
784static __inline__ unsigned long get_tbms (void)
785{
786 unsigned long tbl;
787 unsigned long tbu1, tbu2;
788 unsigned long ms;
789 unsigned long long tmp;
790
791 ulong tbclk = get_tbclk();
792
793 /* get the timebase ticks */
794 do {
795 asm volatile ("mftbu %0":"=r" (tbu1):);
796 asm volatile ("mftb %0":"=r" (tbl):);
797 asm volatile ("mftbu %0":"=r" (tbu2):);
798 } while (tbu1 != tbu2);
799
800 /* convert ticks to ms */
801 tmp = (unsigned long long)(tbu1);
802 tmp = (tmp << 32);
803 tmp += (unsigned long long)(tbl);
804 ms = tmp/(tbclk/1000);
805
806 return ms;
807}
808
809/*
Eran Libertyf046ccd2005-07-28 10:08:46 -0500810 * Initialize all of memory for ECC, then enable errors.
811 */
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200812/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100813void ddr_enable_ecc(unsigned int dram_size)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500814{
Timur Tabid239d742006-11-03 12:00:28 -0600815 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500816 volatile ddr83xx_t *ddr= &immap->ddr;
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100817 unsigned long t_start, t_end;
Dave Liu90f30a72006-11-02 18:05:50 -0600818 register u64 *p;
819 register uint size;
820 unsigned int pattern[2];
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100821#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
822 uint i;
823#endif
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100824 icache_enable();
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100825 t_start = get_tbms();
Dave Liu90f30a72006-11-02 18:05:50 -0600826 pattern[0] = 0xdeadbeef;
827 pattern[1] = 0xdeadbeef;
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100828
829#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
Dave Liu90f30a72006-11-02 18:05:50 -0600830 debug("ddr init: CPU FP write method\n");
831 size = dram_size;
832 for (p = 0; p < (u64*)(size); p++) {
833 ppcDWstore((u32*)p, pattern);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500834 }
Dave Liu90f30a72006-11-02 18:05:50 -0600835 __asm__ __volatile__ ("sync");
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100836#else
Dave Liu90f30a72006-11-02 18:05:50 -0600837 debug("ddr init: DMA method\n");
838 size = 0x2000;
839 for (p = 0; p < (u64*)(size); p++) {
840 ppcDWstore((u32*)p, pattern);
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100841 }
Dave Liu90f30a72006-11-02 18:05:50 -0600842 __asm__ __volatile__ ("sync");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500843
Dave Liu90f30a72006-11-02 18:05:50 -0600844 /* Initialise DMA for direct transfer */
845 dma_init();
846 /* Start DMA to transfer */
Dave Liu5f820432006-11-03 19:33:44 -0600847 dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
848 dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
849 dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
850 dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
851 dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
852 dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
853 dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
854 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
855 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
856 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500857
858 for (i = 1; i < dram_size / 0x800000; i++) {
859 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
860 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500861#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500862
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100863 t_end = get_tbms();
864 icache_disable();
865
866 debug("\nREADY!!\n");
867 debug("ddr init duration: %ld ms\n", t_end - t_start);
868
869 /* Clear All ECC Errors */
870 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
871 ddr->err_detect |= ECC_ERROR_DETECT_MME;
872 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
873 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
874 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
875 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
876 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
877 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
878
879 /* Disable ECC-Interrupts */
880 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
881
882 /* Enable errors for ECC */
883 ddr->err_disable &= ECC_ERROR_ENABLE;
884
885 __asm__ __volatile__ ("sync");
886 __asm__ __volatile__ ("isync");
887}
Eran Libertyf046ccd2005-07-28 10:08:46 -0500888#endif /* CONFIG_DDR_ECC */