blob: 3e2b9a7745e9542a212c14c1cb4ef9cc3beca22c [file] [log] [blame]
Tom Warrenf7dc4ac2014-01-24 12:46:18 -07001/*
2 * (C) Copyright 2013-2014
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
Tom Warrenf7dc4ac2014-01-24 12:46:18 -07009#include <asm/arch/gpio.h>
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070010#include <asm/arch/pinmux.h>
Alexandre Courbota38a3c42015-07-09 16:33:01 +090011#include <asm/arch-tegra/gpu.h>
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070012#include "pinmux-config-venice2.h"
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070013
14/*
15 * Routine: pinmux_init
16 * Description: Do individual peripheral pinmux configs
17 */
18void pinmux_init(void)
19{
Stephen Warren2eba87a2014-04-22 14:37:57 -060020 pinmux_set_tristate_input_clamping();
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070021
Stephen Warren2eba87a2014-04-22 14:37:57 -060022 gpio_config_table(venice2_gpio_inits,
23 ARRAY_SIZE(venice2_gpio_inits));
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070024
Stephen Warren2eba87a2014-04-22 14:37:57 -060025 pinmux_config_pingrp_table(venice2_pingrps,
26 ARRAY_SIZE(venice2_pingrps));
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070027
Stephen Warren2eba87a2014-04-22 14:37:57 -060028 pinmux_config_drvgrp_table(venice2_drvgrps,
29 ARRAY_SIZE(venice2_drvgrps));
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070030}
Alexandre Courbota38a3c42015-07-09 16:33:01 +090031
32int ft_board_setup(void *blob, bd_t *bd)
33{
34 gpu_enable_node(blob, "/gpu@0,57000000");
35
36 return 0;
37}