Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2004 Texas Insturments |
| 3 | * |
| 4 | * (C) Copyright 2002 |
| 5 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 6 | * Marius Groeger <mgroeger@sysgo.de> |
| 7 | * |
| 8 | * (C) Copyright 2002 |
| 9 | * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
| 10 | * |
| 11 | * See file CREDITS for list of people who contributed to this |
| 12 | * project. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License as |
| 16 | * published by the Free Software Foundation; either version 2 of |
| 17 | * the License, or (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 27 | * MA 02111-1307 USA |
| 28 | */ |
| 29 | |
| 30 | /* |
| 31 | * CPU specific code |
| 32 | */ |
| 33 | |
| 34 | #include <common.h> |
| 35 | #include <command.h> |
| 36 | #include <s3c6400.h> |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 37 | #include <asm/system.h> |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 38 | |
| 39 | static void cache_flush (void); |
| 40 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 41 | static void cp_delay (void) |
| 42 | { |
| 43 | volatile int i; |
| 44 | |
| 45 | /* Many OMAP regs need at least 2 nops */ |
| 46 | for (i = 0; i < 100; i++) |
| 47 | __asm__ __volatile__("nop\n"); |
| 48 | } |
| 49 | |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 50 | int cpu_init (void) |
| 51 | { |
| 52 | return 0; |
| 53 | } |
| 54 | |
| 55 | int cleanup_before_linux (void) |
| 56 | { |
| 57 | /* |
| 58 | * this function is called just before we call linux |
| 59 | * it prepares the processor for linux |
| 60 | * |
| 61 | * we turn off caches etc ... |
| 62 | */ |
| 63 | |
| 64 | disable_interrupts (); |
| 65 | |
| 66 | /* turn off I/D-cache */ |
| 67 | icache_disable(); |
| 68 | dcache_disable(); |
| 69 | cache_flush(); |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | |
| 75 | /* * reset the cpu by setting up the watchdog timer and let him time out */ |
| 76 | void reset_cpu (ulong ignored) |
| 77 | { |
| 78 | printf("reset... \n\n\n"); |
| 79 | SW_RST_REG = 0x6400; |
| 80 | /* loop forever and wait for reset to happen */ |
| 81 | while (1) { |
| 82 | if (serial_tstc()) { |
| 83 | serial_getc(); |
| 84 | break; |
| 85 | } |
| 86 | } |
| 87 | /*NOTREACHED*/ |
| 88 | } |
| 89 | |
| 90 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
| 91 | { |
| 92 | disable_interrupts (); |
| 93 | reset_cpu (0); |
| 94 | /*NOTREACHED*/ |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | void icache_enable (void) |
| 99 | { |
| 100 | ulong reg; |
| 101 | |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 102 | reg = get_cr (); /* get control reg. */ |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 103 | cp_delay (); |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 104 | set_cr (reg | CR_I); |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | void icache_disable (void) |
| 108 | { |
| 109 | ulong reg; |
| 110 | |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 111 | reg = get_cr (); |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 112 | cp_delay (); |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 113 | set_cr (reg & ~CR_I); |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | int icache_status (void) |
| 117 | { |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 118 | return (get_cr () & CR_I) != 0; |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | /* It makes no sense to use the dcache if the MMU is not enabled */ |
| 122 | void dcache_enable (void) |
| 123 | { |
| 124 | ulong reg; |
| 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 126 | reg = get_cr (); |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 127 | cp_delay (); |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 128 | set_cr (reg | CR_C); |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | void dcache_disable (void) |
| 132 | { |
| 133 | ulong reg; |
| 134 | |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 135 | reg = get_cr (); |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 136 | cp_delay (); |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 137 | set_cr (reg & ~CR_C); |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | int dcache_status (void) |
| 141 | { |
Jean-Christophe PLAGNIOL-VILLARD | 677e62f | 2009-04-05 13:02:43 +0200 | [diff] [blame^] | 142 | return (get_cr () & CR_C) != 0; |
Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | /* flush I/D-cache */ |
| 146 | static void cache_flush (void) |
| 147 | { |
| 148 | /* invalidate both caches and flush btb */ |
| 149 | asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0)); |
| 150 | /* mem barrier to sync things */ |
| 151 | asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0)); |
| 152 | } |