blob: 1e94f7d6d01094bfa0e244881a463998959cfcb2 [file] [log] [blame]
Guennadi Liakhovetski9b077732008-08-31 00:39:46 +02001/*
2 * (C) Copyright 2004 Texas Insturments
3 *
4 * (C) Copyright 2002
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * (C) Copyright 2002
9 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * CPU specific code
32 */
33
34#include <common.h>
35#include <command.h>
36#include <s3c6400.h>
37
38static void cache_flush (void);
39
40/* read co-processor 15, register #1 (control register) */
41static unsigned long read_p15_c1 (void)
42{
43 unsigned long value;
44
45 __asm__ __volatile__(
46 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
47 : "=r" (value)
48 :
49 : "memory");
50 return value;
51}
52
53/* write to co-processor 15, register #1 (control register) */
54static void write_p15_c1 (unsigned long value)
55{
56 __asm__ __volatile__(
57 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
58 :
59 : "r" (value)
60 : "memory");
61
62 read_p15_c1();
63}
64
65static void cp_delay (void)
66{
67 volatile int i;
68
69 /* Many OMAP regs need at least 2 nops */
70 for (i = 0; i < 100; i++)
71 __asm__ __volatile__("nop\n");
72}
73
74/* See also ARM Ref. Man. */
75#define C1_MMU (1 << 0) /* mmu off/on */
76#define C1_ALIGN (1 << 1) /* alignment faults off/on */
77#define C1_DC (1 << 2) /* dcache off/on */
78#define C1_WB (1 << 3) /* merging write buffer on/off */
79#define C1_BIG_ENDIAN (1 << 7) /* big endian off/on */
80#define C1_SYS_PROT (1 << 8) /* system protection */
81#define C1_ROM_PROT (1 << 9) /* ROM protection */
82#define C1_IC (1 << 12) /* icache off/on */
83#define C1_HIGH_VECTORS (1 << 13) /* location of vectors: low/high */
84#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
85
86int cpu_init (void)
87{
88 return 0;
89}
90
91int cleanup_before_linux (void)
92{
93 /*
94 * this function is called just before we call linux
95 * it prepares the processor for linux
96 *
97 * we turn off caches etc ...
98 */
99
100 disable_interrupts ();
101
102 /* turn off I/D-cache */
103 icache_disable();
104 dcache_disable();
105 cache_flush();
106
107 return 0;
108}
109
110
111/* * reset the cpu by setting up the watchdog timer and let him time out */
112void reset_cpu (ulong ignored)
113{
114 printf("reset... \n\n\n");
115 SW_RST_REG = 0x6400;
116 /* loop forever and wait for reset to happen */
117 while (1) {
118 if (serial_tstc()) {
119 serial_getc();
120 break;
121 }
122 }
123 /*NOTREACHED*/
124}
125
126int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
127{
128 disable_interrupts ();
129 reset_cpu (0);
130 /*NOTREACHED*/
131 return 0;
132}
133
134void icache_enable (void)
135{
136 ulong reg;
137
138 reg = read_p15_c1 (); /* get control reg. */
139 cp_delay ();
140 write_p15_c1 (reg | C1_IC);
141}
142
143void icache_disable (void)
144{
145 ulong reg;
146
147 reg = read_p15_c1 ();
148 cp_delay ();
149 write_p15_c1 (reg & ~C1_IC);
150}
151
152int icache_status (void)
153{
154 return (read_p15_c1 () & C1_IC) != 0;
155}
156
157/* It makes no sense to use the dcache if the MMU is not enabled */
158void dcache_enable (void)
159{
160 ulong reg;
161
162 reg = read_p15_c1 ();
163 cp_delay ();
164 write_p15_c1 (reg | C1_DC);
165}
166
167void dcache_disable (void)
168{
169 ulong reg;
170
171 reg = read_p15_c1 ();
172 cp_delay ();
173 write_p15_c1 (reg & ~C1_DC);
174}
175
176int dcache_status (void)
177{
178 return (read_p15_c1 () & C1_DC) != 0;
179}
180
181/* flush I/D-cache */
182static void cache_flush (void)
183{
184 /* invalidate both caches and flush btb */
185 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
186 /* mem barrier to sync things */
187 asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
188}