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wdenkefa329c2004-03-23 20:18:25 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenkefa329c2004-03-23 20:18:25 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkefa329c2004-03-23 20:18:25 +00006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
16#define CONFIG_MPC5200
wdenk62b4ac92004-05-05 08:31:53 +000017#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkefa329c2004-03-23 20:18:25 +000018#define CONFIG_PM520 1 /* ... on PM520 board */
19
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xfff00000
21
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
wdenkefa329c2004-03-23 20:18:25 +000023
wdenk49822e22004-06-19 21:19:10 +000024#define CONFIG_MISC_INIT_R
25
Becky Bruce31d82672008-05-08 19:02:12 -050026#define CONFIG_HIGH_BATS 1 /* High BATs supported */
27
wdenkefa329c2004-03-23 20:18:25 +000028/*
29 * Serial console configuration
30 */
31#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
32#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkefa329c2004-03-23 20:18:25 +000034
35
wdenkefa329c2004-03-23 20:18:25 +000036/*
37 * PCI Mapping:
38 * 0x40000000 - 0x4fffffff - PCI Memory
39 * 0x50000000 - 0x50ffffff - PCI IO Space
40 */
41#define CONFIG_PCI 1
42#define CONFIG_PCI_PNP 1
43#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050044#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenkefa329c2004-03-23 20:18:25 +000045
46#define CONFIG_PCI_MEM_BUS 0x40000000
47#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
48#define CONFIG_PCI_MEM_SIZE 0x10000000
49
50#define CONFIG_PCI_IO_BUS 0x50000000
51#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
52#define CONFIG_PCI_IO_SIZE 0x01000000
53
Marian Balakowicz63ff0042005-10-28 22:30:33 +020054#define CONFIG_MII 1
wdenkefa329c2004-03-23 20:18:25 +000055#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkefa329c2004-03-23 20:18:25 +000057#undef CONFIG_NS8382X
58
wdenkefa329c2004-03-23 20:18:25 +000059
wdenk49822e22004-06-19 21:19:10 +000060/* Partitions */
61#define CONFIG_DOS_PARTITION
62
63/* USB */
64#if 1
65#define CONFIG_USB_OHCI
wdenk49822e22004-06-19 21:19:10 +000066#define CONFIG_USB_STORAGE
wdenk49822e22004-06-19 21:19:10 +000067#endif
68
Jon Loeligeracf02692007-07-08 14:49:44 -050069/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
77
78/*
Jon Loeligeracf02692007-07-08 14:49:44 -050079 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
83#define CONFIG_CMD_BEDBUG
84#define CONFIG_CMD_DATE
85#define CONFIG_CMD_DHCP
86#define CONFIG_CMD_EEPROM
87#define CONFIG_CMD_FAT
88#define CONFIG_CMD_I2C
89#define CONFIG_CMD_IDE
90#define CONFIG_CMD_NFS
91#define CONFIG_CMD_SNTP
92#define CONFIG_CMD_USB
93
Jon Loeligeracf02692007-07-08 14:49:44 -050094#define CONFIG_CMD_PCI
Jon Loeligeracf02692007-07-08 14:49:44 -050095
wdenkefa329c2004-03-23 20:18:25 +000096
97/*
98 * Autobooting
99 */
100#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk49822e22004-06-19 21:19:10 +0000101
102#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100103 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk49822e22004-06-19 21:19:10 +0000104 "echo"
105
106#undef CONFIG_BOOTARGS
107
108#define CONFIG_EXTRA_ENV_SETTINGS \
109 "netdev=eth0\0" \
110 "hostname=pm520\0" \
111 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100112 "nfsroot=${serverip}:${rootpath}\0" \
wdenk49822e22004-06-19 21:19:10 +0000113 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100114 "addip=setenv bootargs ${bootargs} " \
115 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
116 ":${hostname}:${netdev}:off panic=1\0" \
wdenk49822e22004-06-19 21:19:10 +0000117 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100118 "bootm ${kernel_addr}\0" \
wdenk49822e22004-06-19 21:19:10 +0000119 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100120 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
121 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk49822e22004-06-19 21:19:10 +0000122 "rootpath=/opt/eldk30/ppc_82xx\0" \
123 "bootfile=/tftpboot/PM520/uImage\0" \
124 ""
125
126#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkefa329c2004-03-23 20:18:25 +0000127
wdenkefa329c2004-03-23 20:18:25 +0000128/*
129 * IPB Bus clocking configuration.
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkefa329c2004-03-23 20:18:25 +0000132/*
133 * I2C configuration
134 */
135#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
wdenkefa329c2004-03-23 20:18:25 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
139#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkefa329c2004-03-23 20:18:25 +0000140
141/*
142 * EEPROM configuration
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
145#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
146#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
147#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenkefa329c2004-03-23 20:18:25 +0000148
149/*
150 * RTC configuration
151 */
152#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenkefa329c2004-03-23 20:18:25 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_DOC_BASE 0xE0000000
156#define CONFIG_SYS_DOC_SIZE 0x00100000
wdenk49822e22004-06-19 21:19:10 +0000157
158#if defined(CONFIG_BOOT_ROM)
159/*
160 * Flash configuration (8,16 or 32 MB)
161 * TEXT base always at 0xFFF00000
162 * ENV_ADDR always at 0xFFF40000
Wolfgang Denkc7428d42005-12-29 15:12:09 +0100163 * FLASH_BASE at 0xFA000000 for 64 MB
164 * 0xFC000000 for 32 MB
wdenk49822e22004-06-19 21:19:10 +0000165 * 0xFD000000 for 16 MB
166 * 0xFD800000 for 8 MB
167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_BASE 0xFA000000
169#define CONFIG_SYS_FLASH_SIZE 0x04000000
170#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
171#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200172#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
wdenk49822e22004-06-19 21:19:10 +0000173#else
174/*
175 * Flash configuration (8,16 or 32 MB)
176 * TEXT base always at 0xFFF00000
177 * ENV_ADDR always at 0xFFF40000
Wolfgang Denkc7428d42005-12-29 15:12:09 +0100178 * FLASH_BASE at 0xFC000000 for 64 MB
179 * 0xFE000000 for 32 MB
wdenk49822e22004-06-19 21:19:10 +0000180 * 0xFF000000 for 16 MB
181 * 0xFF800000 for 8 MB
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_BASE 0xFC000000
184#define CONFIG_SYS_FLASH_SIZE 0x04000000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
wdenk49822e22004-06-19 21:19:10 +0000186#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
wdenkefa329c2004-03-23 20:18:25 +0000188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenkefa329c2004-03-23 20:18:25 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
192#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
193#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
194#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
195#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
wdenkefa329c2004-03-23 20:18:25 +0000196
197#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
198
199#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
200
201
202/*
203 * Environment settings
204 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200205#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200206#define CONFIG_ENV_SIZE 0x10000
207#define CONFIG_ENV_SECT_SIZE 0x40000
wdenkefa329c2004-03-23 20:18:25 +0000208#define CONFIG_ENV_OVERWRITE 1
209
210/*
211 * Memory map
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MBAR 0xf0000000
214#define CONFIG_SYS_SDRAM_BASE 0x00000000
215#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenkefa329c2004-03-23 20:18:25 +0000216
217/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200219#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
wdenkefa329c2004-03-23 20:18:25 +0000220
221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200222#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkefa329c2004-03-23 20:18:25 +0000224
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200225#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
227# define CONFIG_SYS_RAMBOOT 1
wdenkefa329c2004-03-23 20:18:25 +0000228#endif
229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
231#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
232#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkefa329c2004-03-23 20:18:25 +0000233
234/*
235 * Ethernet configuration
236 */
wdenk62b4ac92004-05-05 08:31:53 +0000237#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800238#define CONFIG_MPC5xxx_FEC_MII100
wdenk62b4ac92004-05-05 08:31:53 +0000239/*
Ben Warren86321fc2009-02-05 23:58:25 -0800240 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
wdenk62b4ac92004-05-05 08:31:53 +0000241 */
Ben Warren86321fc2009-02-05 23:58:25 -0800242/* #define CONFIG_MPC5xxx_FEC_MII10 */
wdenkefa329c2004-03-23 20:18:25 +0000243#define CONFIG_PHY_ADDR 0x00
244
245/*
246 * GPIO configuration
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
wdenkefa329c2004-03-23 20:18:25 +0000249
250/*
251 * Miscellaneous configurable options
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_LONGHELP /* undef to save memory */
254#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligeracf02692007-07-08 14:49:44 -0500255#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkefa329c2004-03-23 20:18:25 +0000257#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkefa329c2004-03-23 20:18:25 +0000259#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
261#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
262#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkefa329c2004-03-23 20:18:25 +0000263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
265#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenkefa329c2004-03-23 20:18:25 +0000266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkefa329c2004-03-23 20:18:25 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkefa329c2004-03-23 20:18:25 +0000270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligeracf02692007-07-08 14:49:44 -0500272#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligeracf02692007-07-08 14:49:44 -0500274#endif
275
wdenkefa329c2004-03-23 20:18:25 +0000276/*
277 * Various low-level settings
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
280#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenkefa329c2004-03-23 20:18:25 +0000281
wdenk49822e22004-06-19 21:19:10 +0000282#if defined(CONFIG_BOOT_ROM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
284#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
285#define CONFIG_SYS_BOOTCS_CFG 0x00047800
286#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
287#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
288#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
289#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
290#define CONFIG_SYS_CS1_CFG 0x0004FF00
wdenk49822e22004-06-19 21:19:10 +0000291#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
293#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
294#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
295#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
296#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
297#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
298#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
299#define CONFIG_SYS_CS1_CFG 0x00047800
wdenk49822e22004-06-19 21:19:10 +0000300#endif
wdenkefa329c2004-03-23 20:18:25 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_CS_BURST 0x00000000
303#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenkefa329c2004-03-23 20:18:25 +0000304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_RESET_ADDRESS 0xff000000
wdenkefa329c2004-03-23 20:18:25 +0000306
wdenk49822e22004-06-19 21:19:10 +0000307/*-----------------------------------------------------------------------
308 * USB stuff
309 *-----------------------------------------------------------------------
310 */
311#define CONFIG_USB_CLOCK 0x0001BBBB
312#define CONFIG_USB_CONFIG 0x00005000
313
314/*-----------------------------------------------------------------------
315 * IDE/ATA stuff Supports IDE harddisk
316 *-----------------------------------------------------------------------
317 */
318
319#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
320
321#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
322#undef CONFIG_IDE_LED /* LED for ide not supported */
323
324#undef CONFIG_IDE_RESET /* reset for ide supported */
325#define CONFIG_IDE_PREINIT
326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
328#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
wdenk49822e22004-06-19 21:19:10 +0000329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk49822e22004-06-19 21:19:10 +0000331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenk49822e22004-06-19 21:19:10 +0000333
334/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenk49822e22004-06-19 21:19:10 +0000336
337/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenk49822e22004-06-19 21:19:10 +0000339
340/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
wdenk49822e22004-06-19 21:19:10 +0000342
343/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_ATA_STRIDE 4
wdenk49822e22004-06-19 21:19:10 +0000345
wdenkefa329c2004-03-23 20:18:25 +0000346#endif /* __CONFIG_H */