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wdenkba56f622004-02-06 23:19:44 +00001/*-----------------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -04002 * This source code is dual-licensed. You may use it under the terms of the
3 * GNU General Public License version 2, or under the license below.
wdenkba56f622004-02-06 23:19:44 +00004 *
Wolfgang Denk265817c2005-09-25 00:53:22 +02005 * This source code has been made available to you by IBM on an AS-IS
6 * basis. Anyone receiving this source is licensed under IBM
7 * copyrights to use it in any way he or she deems fit, including
8 * copying it, modifying it, compiling it, and redistributing it either
9 * with or without modifications. No license under IBM patents or
10 * patent applications is to be implied by the copyright license.
wdenkba56f622004-02-06 23:19:44 +000011 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020012 * Any user of this software should understand that IBM cannot provide
13 * technical support for this software and will not be responsible for
14 * any consequences resulting from the use of this software.
wdenkba56f622004-02-06 23:19:44 +000015 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020016 * Any person who transfers this source code or any derivative work
17 * must include the IBM copyright notice, this paragraph, and the
18 * preceding two paragraphs in the transferred software.
wdenkba56f622004-02-06 23:19:44 +000019 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020020 * COPYRIGHT I B M CORPORATION 1995
21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkba56f622004-02-06 23:19:44 +000022 *-----------------------------------------------------------------------------*/
23/*-----------------------------------------------------------------------------+
24 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020025 * File Name: enetemac.c
wdenkba56f622004-02-06 23:19:44 +000026 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020027 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
wdenkba56f622004-02-06 23:19:44 +000028 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020029 * Author: Mark Wisner
wdenkba56f622004-02-06 23:19:44 +000030 *
31 * Change Activity-
32 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020033 * Date Description of Change BY
34 * --------- --------------------- ---
35 * 05-May-99 Created MKW
36 * 27-Jun-99 Clean up JWB
37 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
38 * 29-Jul-99 Added Full duplex support MKW
39 * 06-Aug-99 Changed names for Mal CR reg MKW
40 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
41 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
42 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
43 * to avoid chaining maximum sized packets. Push starting
44 * RX descriptor address up to the next cache line boundary.
45 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
46 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
Niklaus Gigerddc922f2009-10-04 20:04:20 +020047 * EMAC0_RXM register. JWB
Wolfgang Denk265817c2005-09-25 00:53:22 +020048 * 12-Mar-01 anne-sophie.harnois@nextream.fr
49 * - Variables are compatible with those already defined in
50 * include/net.h
51 * - Receive buffer descriptor ring is used to send buffers
52 * to the user
53 * - Info print about send/received/handled packet number if
54 * INFO_405_ENET is set
55 * 17-Apr-01 stefan.roese@esd-electronics.com
56 * - MAL reset in "eth_halt" included
57 * - Enet speed and duplex output now in one line
58 * 08-May-01 stefan.roese@esd-electronics.com
59 * - MAL error handling added (eth_init called again)
60 * 13-Nov-01 stefan.roese@esd-electronics.com
Niklaus Gigerddc922f2009-10-04 20:04:20 +020061 * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
Wolfgang Denk265817c2005-09-25 00:53:22 +020062 * 04-Jan-02 stefan.roese@esd-electronics.com
63 * - Wait for PHY auto negotiation to complete added
64 * 06-Feb-02 stefan.roese@esd-electronics.com
65 * - Bug fixed in waiting for auto negotiation to complete
66 * 26-Feb-02 stefan.roese@esd-electronics.com
67 * - rx and tx buffer descriptors now allocated (no fixed address
68 * used anymore)
69 * 17-Jun-02 stefan.roese@esd-electronics.com
70 * - MAL error debug printf 'M' removed (rx de interrupt may
71 * occur upon many incoming packets with only 4 rx buffers).
wdenkba56f622004-02-06 23:19:44 +000072 *-----------------------------------------------------------------------------*
Wolfgang Denk265817c2005-09-25 00:53:22 +020073 * 17-Nov-03 travis.sawyer@sandburst.com
74 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
75 * in the 440GX. This port should work with the 440GP
76 * (2 EMACs) also
77 * 15-Aug-05 sr@denx.de
78 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
79 now handling all 4xx cpu's.
wdenkba56f622004-02-06 23:19:44 +000080 *-----------------------------------------------------------------------------*/
81
82#include <config.h>
wdenkba56f622004-02-06 23:19:44 +000083#include <common.h>
84#include <net.h>
85#include <asm/processor.h>
Stefan Roese2d834762007-10-23 14:03:17 +020086#include <asm/io.h>
Stefan Roeseff768cb2007-10-31 18:01:24 +010087#include <asm/cache.h>
88#include <asm/mmu.h>
wdenkba56f622004-02-06 23:19:44 +000089#include <commproc.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020090#include <asm/ppc4xx.h>
91#include <asm/ppc4xx-emac.h>
92#include <asm/ppc4xx-mal.h>
wdenkba56f622004-02-06 23:19:44 +000093#include <miiphy.h>
94#include <malloc.h>
Stefan Roesef0813ab2011-11-15 08:01:58 +000095#include <linux/compiler.h>
wdenkba56f622004-02-06 23:19:44 +000096
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -050097#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
Stefan Roesed6c61aa2005-08-16 18:18:00 +020098#error "CONFIG_MII has to be defined!"
99#endif
wdenkba56f622004-02-06 23:19:44 +0000100
Wolfgang Denk265817c2005-09-25 00:53:22 +0200101#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
Stefan Roese1338e6a2007-10-23 14:05:08 +0200102#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
wdenkba56f622004-02-06 23:19:44 +0000103
wdenkba56f622004-02-06 23:19:44 +0000104/* Ethernet Transmit and Receive Buffers */
105/* AS.HARNOIS
106 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
107 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
108 */
Wolfgang Denk265817c2005-09-25 00:53:22 +0200109#define ENET_MAX_MTU PKTSIZE
wdenkba56f622004-02-06 23:19:44 +0000110#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
111
wdenkba56f622004-02-06 23:19:44 +0000112/*-----------------------------------------------------------------------------+
113 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
114 * Interrupt Controller).
115 *-----------------------------------------------------------------------------*/
Stefan Roesed1631fe2008-06-26 13:40:57 +0200116#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
117
118#if defined(CONFIG_HAS_ETH3)
119#if !defined(CONFIG_440GX)
120#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
121 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
122#else
123/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
124#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
125#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
126#endif /* !defined(CONFIG_440GX) */
127#elif defined(CONFIG_HAS_ETH2)
128#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
129 UIC_MASK(ETH_IRQ_NUM(2)))
130#elif defined(CONFIG_HAS_ETH1)
131#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
132#else
133#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
134#endif
135
136/*
137 * Define a default version for UIC_ETHxB for non 440GX so that we can
138 * use common code for all 4xx variants
139 */
140#if !defined(UIC_ETHxB)
141#define UIC_ETHxB 0
142#endif
143
144#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
145#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
146#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
147#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
148#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
149
150#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
151#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
152
153/*
154 * We have 3 different interrupt types:
155 * - MAL interrupts indicating successful transfer
156 * - MAL error interrupts indicating MAL related errors
157 * - EMAC interrupts indicating EMAC related errors
158 *
159 * All those interrupts can be on different UIC's, but since
160 * now at least all interrupts from one type are on the same
161 * UIC. Only exception is 440GX where the EMAC interrupts are
162 * spread over two UIC's!
163 */
Stefan Roese5de85142008-06-26 17:36:39 +0200164#if defined(CONFIG_440GX)
165#define UIC_BASE_MAL UIC1_DCR_BASE
166#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
167#define UIC_BASE_EMAC UIC2_DCR_BASE
168#define UIC_BASE_EMAC_B UIC3_DCR_BASE
169#else
Stefan Roesed1631fe2008-06-26 13:40:57 +0200170#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
171#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
172#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
Stefan Roesed1631fe2008-06-26 13:40:57 +0200173#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
174#endif
wdenkba56f622004-02-06 23:19:44 +0000175
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200176#undef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +0000177
Wolfgang Denk265817c2005-09-25 00:53:22 +0200178#define BI_PHYMODE_NONE 0
179#define BI_PHYMODE_ZMII 1
wdenk3c74e322004-02-22 23:46:08 +0000180#define BI_PHYMODE_RGMII 2
Stefan Roese887e2ec2006-09-07 11:51:23 +0200181#define BI_PHYMODE_GMII 3
182#define BI_PHYMODE_RTBI 4
183#define BI_PHYMODE_TBI 5
Stefan Roesedbbd1252007-10-05 17:10:59 +0200184#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100185 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200186 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200187#define BI_PHYMODE_SMII 6
188#define BI_PHYMODE_MII 7
Stefan Roese8ac41e32008-03-11 15:05:26 +0100189#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
190#define BI_PHYMODE_RMII 8
191#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200192#endif
Victor Gallardo78d78232008-09-04 23:49:36 -0700193#define BI_PHYMODE_SGMII 9
wdenk3c74e322004-02-22 23:46:08 +0000194
Stefan Roese1941cce2007-10-05 17:35:10 +0200195#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200196 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100197 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200198 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200199#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
200#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200201
Stefan Roese8ac41e32008-03-11 15:05:26 +0100202#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
203#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
204#endif
205
206#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
207#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
208#else
209#define MAL_RX_CHAN_MUL 1
210#endif
211
Victor Gallardo78d78232008-09-04 23:49:36 -0700212/*--------------------------------------------------------------------+
213 * Fixed PHY (PHY-less) support for Ethernet Ports.
214 *--------------------------------------------------------------------*/
215
216/*
217 * Some boards do not have a PHY for each ethernet port. These ports
218 * are known as Fixed PHY (or PHY-less) ports. For such ports, set
219 * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
Victor Gallardo78d78232008-09-04 23:49:36 -0700221 * duplex should be for these ports in the board configuration
222 * file.
223 *
224 * For Example:
225 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
226 *
227 * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
228 * #define CONFIG_PHY1_ADDR 1
229 * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
230 * #define CONFIG_PHY3_ADDR 3
231 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
Victor Gallardo78d78232008-09-04 23:49:36 -0700233 * {devnum, speed, duplex},
234 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 * #define CONFIG_SYS_FIXED_PHY_PORTS \
236 * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
237 * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
Victor Gallardo78d78232008-09-04 23:49:36 -0700238 */
239
240#ifndef CONFIG_FIXED_PHY
241#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
242#endif
243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#ifndef CONFIG_SYS_FIXED_PHY_PORTS
245#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
Victor Gallardo78d78232008-09-04 23:49:36 -0700246#endif
247
248struct fixed_phy_port {
249 unsigned int devnum; /* ethernet port */
250 unsigned int speed; /* specified speed 10,100 or 1000 */
251 unsigned int duplex; /* specified duplex FULL or HALF */
252};
253
254static const struct fixed_phy_port fixed_phy_port[] = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
Victor Gallardo78d78232008-09-04 23:49:36 -0700256};
257
wdenkba56f622004-02-06 23:19:44 +0000258/*-----------------------------------------------------------------------------+
259 * Global variables. TX and RX descriptors and buffers.
260 *-----------------------------------------------------------------------------*/
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200261
Stefan Roese1e25f952005-10-20 16:34:28 +0200262/*
263 * Get count of EMAC devices (doesn't have to be the max. possible number
264 * supported by the cpu)
Stefan Roese353f2682007-10-23 10:10:08 +0200265 *
266 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
267 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
268 * 405EX/405EXr eval board, using the same binary.
Stefan Roese1e25f952005-10-20 16:34:28 +0200269 */
Stefan Roese353f2682007-10-23 10:10:08 +0200270#if defined(CONFIG_BOARD_EMAC_COUNT)
271#define LAST_EMAC_NUM board_emac_count()
272#else /* CONFIG_BOARD_EMAC_COUNT */
Stefan Roese1e25f952005-10-20 16:34:28 +0200273#if defined(CONFIG_HAS_ETH3)
274#define LAST_EMAC_NUM 4
275#elif defined(CONFIG_HAS_ETH2)
276#define LAST_EMAC_NUM 3
277#elif defined(CONFIG_HAS_ETH1)
278#define LAST_EMAC_NUM 2
279#else
280#define LAST_EMAC_NUM 1
281#endif
Stefan Roese353f2682007-10-23 10:10:08 +0200282#endif /* CONFIG_BOARD_EMAC_COUNT */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200283
Stefan Roese5fb692c2007-01-18 10:25:34 +0100284/* normal boards start with EMAC0 */
285#if !defined(CONFIG_EMAC_NR_START)
286#define CONFIG_EMAC_NR_START 0
287#endif
288
Stefan Roeseff768cb2007-10-31 18:01:24 +0100289#define MAL_RX_DESC_SIZE 2048
290#define MAL_TX_DESC_SIZE 2048
291#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
292
wdenkba56f622004-02-06 23:19:44 +0000293/*-----------------------------------------------------------------------------+
294 * Prototypes and externals.
295 *-----------------------------------------------------------------------------*/
296static void enet_rcv (struct eth_device *dev, unsigned long malisr);
297
298int enetInt (struct eth_device *dev);
299static void mal_err (struct eth_device *dev, unsigned long isr,
300 unsigned long uic, unsigned long maldef,
301 unsigned long mal_errr);
302static void emac_err (struct eth_device *dev, unsigned long isr);
303
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200304extern int phy_setup_aneg (char *devname, unsigned char addr);
Mike Frysinger5700bb62010-07-27 18:35:08 -0400305extern int emac4xx_miiphy_read (const char *devname, unsigned char addr,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200306 unsigned char reg, unsigned short *value);
Mike Frysinger5700bb62010-07-27 18:35:08 -0400307extern int emac4xx_miiphy_write (const char *devname, unsigned char addr,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200308 unsigned char reg, unsigned short value);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200309
Stefan Roese353f2682007-10-23 10:10:08 +0200310int board_emac_count(void);
311
Stefan Roese8ac41e32008-03-11 15:05:26 +0100312static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
313{
314#if defined(CONFIG_440SPE) || \
315 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
316 defined(CONFIG_405EX)
317 u32 val;
318
Stefan Roesed1c3b272009-09-09 16:25:29 +0200319 mfsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100320 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200321 mtsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100322#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
323 u32 val;
324
325 mfsdr(SDR0_ETH_CFG, val);
326 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
327 mtsdr(SDR0_ETH_CFG, val);
328#endif
329}
330
331static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
332{
333#if defined(CONFIG_440SPE) || \
334 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
335 defined(CONFIG_405EX)
336 u32 val;
337
Stefan Roesed1c3b272009-09-09 16:25:29 +0200338 mfsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100339 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200340 mtsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100341#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
342 u32 val;
343
344 mfsdr(SDR0_ETH_CFG, val);
345 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
346 mtsdr(SDR0_ETH_CFG, val);
347#endif
348}
349
wdenkba56f622004-02-06 23:19:44 +0000350/*-----------------------------------------------------------------------------+
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200351| ppc_4xx_eth_halt
wdenkba56f622004-02-06 23:19:44 +0000352| Disable MAL channel, and EMACn
wdenkba56f622004-02-06 23:19:44 +0000353+-----------------------------------------------------------------------------*/
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200354static void ppc_4xx_eth_halt (struct eth_device *dev)
wdenkba56f622004-02-06 23:19:44 +0000355{
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200356 EMAC_4XX_HW_PST hw_p = dev->priv;
Stefan Roese9ad31982008-03-19 16:35:12 +0100357 u32 val = 10000;
wdenkba56f622004-02-06 23:19:44 +0000358
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200359 out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
wdenkba56f622004-02-06 23:19:44 +0000360
361 /* 1st reset MAL channel */
362 /* Note: writing a 0 to a channel has no effect */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200363#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200364 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200365#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200366 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200367#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200368 mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
wdenkba56f622004-02-06 23:19:44 +0000369
370 /* wait for reset */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200371 while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
wdenkba56f622004-02-06 23:19:44 +0000372 udelay (1000); /* Delay 1 MS so as not to hammer the register */
Stefan Roese9ad31982008-03-19 16:35:12 +0100373 val--;
374 if (val == 0)
wdenkba56f622004-02-06 23:19:44 +0000375 break;
wdenkba56f622004-02-06 23:19:44 +0000376 }
377
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200378 /* provide clocks for EMAC internal loopback */
Stefan Roese8ac41e32008-03-11 15:05:26 +0100379 emac_loopback_enable(hw_p);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200380
Stefan Roese8ac41e32008-03-11 15:05:26 +0100381 /* EMAC RESET */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200382 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
wdenkba56f622004-02-06 23:19:44 +0000383
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200384 /* remove clocks for EMAC internal loopback */
Stefan Roese8ac41e32008-03-11 15:05:26 +0100385 emac_loopback_disable(hw_p);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200386
Stefan Roesea93316c2005-10-18 19:17:12 +0200387#ifndef CONFIG_NETCONSOLE
Stefan Roesec157d8e2005-08-01 16:41:48 +0200388 hw_p->print_speed = 1; /* print speed message again next time */
Stefan Roesea93316c2005-10-18 19:17:12 +0200389#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200390
Stefan Roese4c9e8552008-03-19 16:20:49 +0100391#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
392 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
Stefan Roese9ad31982008-03-19 16:35:12 +0100393 mfsdr(SDR0_ETH_CFG, val);
394 val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
395 mtsdr(SDR0_ETH_CFG, val);
Stefan Roese4c9e8552008-03-19 16:20:49 +0100396#endif
397
wdenkba56f622004-02-06 23:19:44 +0000398 return;
399}
400
Stefan Roese846b0dd2005-08-08 12:42:22 +0200401#if defined (CONFIG_440GX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200402int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
wdenk855a4962004-03-14 18:23:55 +0000403{
404 unsigned long pfc1;
405 unsigned long zmiifer;
406 unsigned long rmiifer;
407
Stefan Roesed1c3b272009-09-09 16:25:29 +0200408 mfsdr(SDR0_PFC1, pfc1);
wdenk855a4962004-03-14 18:23:55 +0000409 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
410
411 zmiifer = 0;
412 rmiifer = 0;
413
414 switch (pfc1) {
415 case 1:
416 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
417 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
418 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
419 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
420 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
421 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
422 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
423 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
424 break;
425 case 2:
Stefan Roesef6e495f2006-11-27 17:43:25 +0100426 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
427 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
428 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
429 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
wdenk855a4962004-03-14 18:23:55 +0000430 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
431 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
432 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
433 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
434 break;
435 case 3:
436 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
437 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
438 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
439 bis->bi_phymode[1] = BI_PHYMODE_NONE;
440 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
441 bis->bi_phymode[3] = BI_PHYMODE_NONE;
442 break;
443 case 4:
444 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
445 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
446 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
447 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
448 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
449 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
450 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
451 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
452 break;
453 case 5:
454 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
455 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
456 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
457 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
458 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
459 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
460 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
461 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
462 break;
463 case 6:
464 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
465 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
466 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
wdenk855a4962004-03-14 18:23:55 +0000467 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
468 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
469 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
wdenk855a4962004-03-14 18:23:55 +0000470 break;
471 case 0:
472 default:
473 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
474 rmiifer = 0x0;
475 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
476 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
477 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
478 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
479 break;
480 }
481
482 /* Ensure we setup mdio for this devnum and ONLY this devnum */
483 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
484
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200485 out_be32((void *)ZMII0_FER, zmiifer);
Stefan Roeseff768cb2007-10-31 18:01:24 +0100486 out_be32((void *)RGMII_FER, rmiifer);
wdenk855a4962004-03-14 18:23:55 +0000487
488 return ((int)pfc1);
wdenk855a4962004-03-14 18:23:55 +0000489}
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200490#endif /* CONFIG_440_GX */
wdenk855a4962004-03-14 18:23:55 +0000491
Stefan Roese887e2ec2006-09-07 11:51:23 +0200492#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
493int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
494{
495 unsigned long zmiifer=0x0;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200496 unsigned long pfc1;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200497
Stefan Roesed1c3b272009-09-09 16:25:29 +0200498 mfsdr(SDR0_PFC1, pfc1);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200499 pfc1 &= SDR0_PFC1_SELECT_MASK;
500
Wolfgang Denk2f152782007-05-05 18:23:11 +0200501 switch (pfc1) {
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200502 case SDR0_PFC1_SELECT_CONFIG_2:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200503 /* 1 x GMII port */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200504 out_be32((void *)ZMII0_FER, 0x00);
Stefan Roese2d834762007-10-23 14:03:17 +0200505 out_be32((void *)RGMII_FER, 0x00000037);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200506 bis->bi_phymode[0] = BI_PHYMODE_GMII;
507 bis->bi_phymode[1] = BI_PHYMODE_NONE;
508 break;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200509 case SDR0_PFC1_SELECT_CONFIG_4:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200510 /* 2 x RGMII ports */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200511 out_be32((void *)ZMII0_FER, 0x00);
Stefan Roese2d834762007-10-23 14:03:17 +0200512 out_be32((void *)RGMII_FER, 0x00000055);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200513 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
514 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
515 break;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200516 case SDR0_PFC1_SELECT_CONFIG_6:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200517 /* 2 x SMII ports */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200518 out_be32((void *)ZMII0_FER,
Stefan Roese2d834762007-10-23 14:03:17 +0200519 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
520 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
521 out_be32((void *)RGMII_FER, 0x00000000);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200522 bis->bi_phymode[0] = BI_PHYMODE_SMII;
523 bis->bi_phymode[1] = BI_PHYMODE_SMII;
524 break;
525 case SDR0_PFC1_SELECT_CONFIG_1_2:
526 /* only 1 x MII supported */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200527 out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
Stefan Roese2d834762007-10-23 14:03:17 +0200528 out_be32((void *)RGMII_FER, 0x00000000);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200529 bis->bi_phymode[0] = BI_PHYMODE_MII;
530 bis->bi_phymode[1] = BI_PHYMODE_NONE;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200531 break;
532 default:
533 break;
534 }
535
536 /* Ensure we setup mdio for this devnum and ONLY this devnum */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200537 zmiifer = in_be32((void *)ZMII0_FER);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200538 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200539 out_be32((void *)ZMII0_FER, zmiifer);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200540
541 return ((int)0x0);
542}
543#endif /* CONFIG_440EPX */
544
Stefan Roesedbbd1252007-10-05 17:10:59 +0200545#if defined(CONFIG_405EX)
546int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
547{
Grant Erickson1740c1b2008-07-08 08:35:00 -0700548 u32 rgmiifer = 0;
Stefan Roesedbbd1252007-10-05 17:10:59 +0200549
550 /*
Grant Erickson1740c1b2008-07-08 08:35:00 -0700551 * The 405EX(r)'s RGMII bridge can operate in one of several
552 * modes, only one of which (2 x RGMII) allows the
553 * simultaneous use of both EMACs on the 405EX.
Stefan Roesedbbd1252007-10-05 17:10:59 +0200554 */
Grant Erickson1740c1b2008-07-08 08:35:00 -0700555
556 switch (CONFIG_EMAC_PHY_MODE) {
557
558 case EMAC_PHY_MODE_NONE:
559 /* No ports */
560 rgmiifer |= RGMII_FER_DIS << 0;
561 rgmiifer |= RGMII_FER_DIS << 4;
562 out_be32((void *)RGMII_FER, rgmiifer);
563 bis->bi_phymode[0] = BI_PHYMODE_NONE;
564 bis->bi_phymode[1] = BI_PHYMODE_NONE;
565 break;
566 case EMAC_PHY_MODE_NONE_RGMII:
567 /* 1 x RGMII port on channel 0 */
568 rgmiifer |= RGMII_FER_RGMII << 0;
569 rgmiifer |= RGMII_FER_DIS << 4;
570 out_be32((void *)RGMII_FER, rgmiifer);
571 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
572 bis->bi_phymode[1] = BI_PHYMODE_NONE;
573 break;
574 case EMAC_PHY_MODE_RGMII_NONE:
575 /* 1 x RGMII port on channel 1 */
576 rgmiifer |= RGMII_FER_DIS << 0;
577 rgmiifer |= RGMII_FER_RGMII << 4;
578 out_be32((void *)RGMII_FER, rgmiifer);
579 bis->bi_phymode[0] = BI_PHYMODE_NONE;
580 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
581 break;
582 case EMAC_PHY_MODE_RGMII_RGMII:
Stefan Roesedbbd1252007-10-05 17:10:59 +0200583 /* 2 x RGMII ports */
Grant Erickson1740c1b2008-07-08 08:35:00 -0700584 rgmiifer |= RGMII_FER_RGMII << 0;
585 rgmiifer |= RGMII_FER_RGMII << 4;
586 out_be32((void *)RGMII_FER, rgmiifer);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200587 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
588 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
589 break;
Grant Erickson1740c1b2008-07-08 08:35:00 -0700590 case EMAC_PHY_MODE_NONE_GMII:
591 /* 1 x GMII port on channel 0 */
592 rgmiifer |= RGMII_FER_GMII << 0;
593 rgmiifer |= RGMII_FER_DIS << 4;
594 out_be32((void *)RGMII_FER, rgmiifer);
595 bis->bi_phymode[0] = BI_PHYMODE_GMII;
596 bis->bi_phymode[1] = BI_PHYMODE_NONE;
597 break;
598 case EMAC_PHY_MODE_NONE_MII:
599 /* 1 x MII port on channel 0 */
600 rgmiifer |= RGMII_FER_MII << 0;
601 rgmiifer |= RGMII_FER_DIS << 4;
602 out_be32((void *)RGMII_FER, rgmiifer);
603 bis->bi_phymode[0] = BI_PHYMODE_MII;
604 bis->bi_phymode[1] = BI_PHYMODE_NONE;
605 break;
606 case EMAC_PHY_MODE_GMII_NONE:
607 /* 1 x GMII port on channel 1 */
608 rgmiifer |= RGMII_FER_DIS << 0;
609 rgmiifer |= RGMII_FER_GMII << 4;
610 out_be32((void *)RGMII_FER, rgmiifer);
611 bis->bi_phymode[0] = BI_PHYMODE_NONE;
612 bis->bi_phymode[1] = BI_PHYMODE_GMII;
613 break;
614 case EMAC_PHY_MODE_MII_NONE:
615 /* 1 x MII port on channel 1 */
616 rgmiifer |= RGMII_FER_DIS << 0;
617 rgmiifer |= RGMII_FER_MII << 4;
618 out_be32((void *)RGMII_FER, rgmiifer);
619 bis->bi_phymode[0] = BI_PHYMODE_NONE;
620 bis->bi_phymode[1] = BI_PHYMODE_MII;
Stefan Roesedbbd1252007-10-05 17:10:59 +0200621 break;
622 default:
623 break;
624 }
625
626 /* Ensure we setup mdio for this devnum and ONLY this devnum */
Grant Erickson1740c1b2008-07-08 08:35:00 -0700627 rgmiifer = in_be32((void *)RGMII_FER);
628 rgmiifer |= (1 << (19-devnum));
629 out_be32((void *)RGMII_FER, rgmiifer);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200630
631 return ((int)0x0);
632}
633#endif /* CONFIG_405EX */
634
Stefan Roese8ac41e32008-03-11 15:05:26 +0100635#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
636int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
637{
638 u32 eth_cfg;
639 u32 zmiifer; /* ZMII0_FER reg. */
640 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
641 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100642 int mode;
Stefan Roese8ac41e32008-03-11 15:05:26 +0100643
644 zmiifer = 0;
645 rmiifer = 0;
646 rmiifer1 = 0;
647
Stefan Roese4c9e8552008-03-19 16:20:49 +0100648#if defined(CONFIG_460EX)
649 mode = 9;
Victor Gallardo78d78232008-09-04 23:49:36 -0700650 mfsdr(SDR0_ETH_CFG, eth_cfg);
651 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
652 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
653 mode = 11; /* config SGMII */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100654#else
655 mode = 10;
Victor Gallardo78d78232008-09-04 23:49:36 -0700656 mfsdr(SDR0_ETH_CFG, eth_cfg);
657 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
658 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
659 ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
660 mode = 12; /* config SGMII */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100661#endif
662
Stefan Roese8ac41e32008-03-11 15:05:26 +0100663 /* TODO:
664 * NOTE: 460GT has 2 RGMII bridge cores:
665 * emac0 ------ RGMII0_BASE
666 * |
667 * emac1 -----+
668 *
669 * emac2 ------ RGMII1_BASE
670 * |
671 * emac3 -----+
672 *
673 * 460EX has 1 RGMII bridge core:
674 * and RGMII1_BASE is disabled
675 * emac0 ------ RGMII0_BASE
676 * |
677 * emac1 -----+
678 */
679
680 /*
681 * Right now only 2*RGMII is supported. Please extend when needed.
682 * sr - 2008-02-19
Victor Gallardo78d78232008-09-04 23:49:36 -0700683 * Add SGMII support.
684 * vg - 2008-07-28
Stefan Roese8ac41e32008-03-11 15:05:26 +0100685 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100686 switch (mode) {
Stefan Roese8ac41e32008-03-11 15:05:26 +0100687 case 1:
688 /* 1 MII - 460EX */
689 /* GMC0 EMAC4_0, ZMII Bridge */
690 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
691 bis->bi_phymode[0] = BI_PHYMODE_MII;
692 bis->bi_phymode[1] = BI_PHYMODE_NONE;
693 bis->bi_phymode[2] = BI_PHYMODE_NONE;
694 bis->bi_phymode[3] = BI_PHYMODE_NONE;
695 break;
696 case 2:
697 /* 2 MII - 460GT */
698 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
699 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
700 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
701 bis->bi_phymode[0] = BI_PHYMODE_MII;
702 bis->bi_phymode[1] = BI_PHYMODE_NONE;
703 bis->bi_phymode[2] = BI_PHYMODE_MII;
704 bis->bi_phymode[3] = BI_PHYMODE_NONE;
705 break;
706 case 3:
707 /* 2 RMII - 460EX */
708 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
709 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
710 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
711 bis->bi_phymode[0] = BI_PHYMODE_RMII;
712 bis->bi_phymode[1] = BI_PHYMODE_RMII;
713 bis->bi_phymode[2] = BI_PHYMODE_NONE;
714 bis->bi_phymode[3] = BI_PHYMODE_NONE;
715 break;
716 case 4:
717 /* 4 RMII - 460GT */
718 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
719 /* ZMII Bridge */
720 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
721 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
722 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
723 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
724 bis->bi_phymode[0] = BI_PHYMODE_RMII;
725 bis->bi_phymode[1] = BI_PHYMODE_RMII;
726 bis->bi_phymode[2] = BI_PHYMODE_RMII;
727 bis->bi_phymode[3] = BI_PHYMODE_RMII;
728 break;
729 case 5:
730 /* 2 SMII - 460EX */
731 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
732 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
733 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
734 bis->bi_phymode[0] = BI_PHYMODE_SMII;
735 bis->bi_phymode[1] = BI_PHYMODE_SMII;
736 bis->bi_phymode[2] = BI_PHYMODE_NONE;
737 bis->bi_phymode[3] = BI_PHYMODE_NONE;
738 break;
739 case 6:
740 /* 4 SMII - 460GT */
741 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
742 /* ZMII Bridge */
743 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
744 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
745 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
746 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
747 bis->bi_phymode[0] = BI_PHYMODE_SMII;
748 bis->bi_phymode[1] = BI_PHYMODE_SMII;
749 bis->bi_phymode[2] = BI_PHYMODE_SMII;
750 bis->bi_phymode[3] = BI_PHYMODE_SMII;
751 break;
752 case 7:
753 /* This is the default mode that we want for board bringup - Maple */
754 /* 1 GMII - 460EX */
755 /* GMC0 EMAC4_0, RGMII Bridge 0 */
756 rmiifer |= RGMII_FER_MDIO(0);
757
758 if (devnum == 0) {
759 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
760 bis->bi_phymode[0] = BI_PHYMODE_GMII;
761 bis->bi_phymode[1] = BI_PHYMODE_NONE;
762 bis->bi_phymode[2] = BI_PHYMODE_NONE;
763 bis->bi_phymode[3] = BI_PHYMODE_NONE;
764 } else {
765 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
766 bis->bi_phymode[0] = BI_PHYMODE_NONE;
767 bis->bi_phymode[1] = BI_PHYMODE_GMII;
768 bis->bi_phymode[2] = BI_PHYMODE_NONE;
769 bis->bi_phymode[3] = BI_PHYMODE_NONE;
770 }
771 break;
772 case 8:
773 /* 2 GMII - 460GT */
774 /* GMC0 EMAC4_0, RGMII Bridge 0 */
775 /* GMC1 EMAC4_2, RGMII Bridge 1 */
776 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
777 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
778 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
779 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
780
781 bis->bi_phymode[0] = BI_PHYMODE_GMII;
782 bis->bi_phymode[1] = BI_PHYMODE_NONE;
783 bis->bi_phymode[2] = BI_PHYMODE_GMII;
784 bis->bi_phymode[3] = BI_PHYMODE_NONE;
785 break;
786 case 9:
787 /* 2 RGMII - 460EX */
788 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
789 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
790 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
791 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
792
793 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
794 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
795 bis->bi_phymode[2] = BI_PHYMODE_NONE;
796 bis->bi_phymode[3] = BI_PHYMODE_NONE;
797 break;
798 case 10:
799 /* 4 RGMII - 460GT */
800 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
801 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
802 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
803 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
804 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
805 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
806 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
807 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
808 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
809 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
810 break;
Victor Gallardo78d78232008-09-04 23:49:36 -0700811 case 11:
812 /* 2 SGMII - 460EX */
813 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
814 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
815 bis->bi_phymode[2] = BI_PHYMODE_NONE;
816 bis->bi_phymode[3] = BI_PHYMODE_NONE;
817 break;
818 case 12:
819 /* 3 SGMII - 460GT */
820 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
821 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
822 bis->bi_phymode[2] = BI_PHYMODE_SGMII;
823 bis->bi_phymode[3] = BI_PHYMODE_NONE;
824 break;
Stefan Roese8ac41e32008-03-11 15:05:26 +0100825 default:
826 break;
827 }
828
829 /* Set EMAC for MDIO */
830 mfsdr(SDR0_ETH_CFG, eth_cfg);
831 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
832 mtsdr(SDR0_ETH_CFG, eth_cfg);
833
834 out_be32((void *)RGMII_FER, rmiifer);
835#if defined(CONFIG_460GT)
836 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
837#endif
838
839 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
840 mfsdr(SDR0_ETH_CFG, eth_cfg);
841 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
842 mtsdr(SDR0_ETH_CFG, eth_cfg);
843
844 return 0;
845}
846#endif /* CONFIG_460EX || CONFIG_460GT */
847
Stefan Roeseff768cb2007-10-31 18:01:24 +0100848static inline void *malloc_aligned(u32 size, u32 align)
849{
850 return (void *)(((u32)malloc(size + align) + align - 1) &
851 ~(align - 1));
852}
853
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200854static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
wdenkba56f622004-02-06 23:19:44 +0000855{
Stefan Roeseff768cb2007-10-31 18:01:24 +0100856 int i;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200857 unsigned long reg = 0;
wdenkba56f622004-02-06 23:19:44 +0000858 unsigned long msr;
859 unsigned long speed;
860 unsigned long duplex;
861 unsigned long failsafe;
862 unsigned mode_reg;
863 unsigned short devnum;
864 unsigned short reg_short;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200865#if defined(CONFIG_440GX) || \
866 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200867 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100868 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200869 defined(CONFIG_405EX)
Felix Radensky0c24dec2009-05-31 20:44:15 +0300870 u32 opbfreq;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200871 sys_info_t sysinfo;
Alessio Centazzo0544c632009-07-11 11:56:06 -0700872#if defined(CONFIG_440GX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200873 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100874 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200875 defined(CONFIG_405EX)
Stefan Roesef0813ab2011-11-15 08:01:58 +0000876 __maybe_unused int ethgroup = -1;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100877#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200878#endif
Stefan Roeseff768cb2007-10-31 18:01:24 +0100879 u32 bd_cached;
880 u32 bd_uncached = 0;
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +0100881#ifdef CONFIG_4xx_DCACHE
882 static u32 last_used_ea = 0;
883#endif
Stefan Roesee54ec0f2008-04-03 14:50:34 +0200884#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
885 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
886 defined(CONFIG_405EX)
887 int rgmii_channel;
888#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200889
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200890 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +0000891
892 /* before doing anything, figure out if we have a MAC address */
893 /* if not, bail */
Stefan Roese4f92ac32005-10-10 17:43:58 +0200894 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
895 printf("ERROR: ethaddr not set!\n");
wdenkba56f622004-02-06 23:19:44 +0000896 return -1;
Stefan Roese4f92ac32005-10-10 17:43:58 +0200897 }
wdenkba56f622004-02-06 23:19:44 +0000898
Stefan Roese887e2ec2006-09-07 11:51:23 +0200899#if defined(CONFIG_440GX) || \
900 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200901 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100902 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200903 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000904 /* Need to get the OPB frequency so we can access the PHY */
905 get_sys_info (&sysinfo);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200906#endif
wdenkba56f622004-02-06 23:19:44 +0000907
wdenkba56f622004-02-06 23:19:44 +0000908 msr = mfmsr ();
909 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
910
911 devnum = hw_p->devnum;
912
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200913#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +0000914 /* AS.HARNOIS
915 * We should have :
Wolfgang Denk265817c2005-09-25 00:53:22 +0200916 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
wdenkba56f622004-02-06 23:19:44 +0000917 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
918 * is possible that new packets (without relationship with
919 * current transfer) have got the time to arrived before
920 * netloop calls eth_halt
921 */
922 printf ("About preceeding transfer (eth%d):\n"
923 "- Sent packet number %d\n"
924 "- Received packet number %d\n"
925 "- Handled packet number %d\n",
926 hw_p->devnum,
927 hw_p->stats.pkts_tx,
928 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
929
930 hw_p->stats.pkts_tx = 0;
931 hw_p->stats.pkts_rx = 0;
932 hw_p->stats.pkts_handled = 0;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200933 hw_p->print_speed = 1; /* print speed message again next time */
wdenkba56f622004-02-06 23:19:44 +0000934#endif
935
Wolfgang Denk265817c2005-09-25 00:53:22 +0200936 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
937 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
wdenkba56f622004-02-06 23:19:44 +0000938
939 hw_p->rx_slot = 0; /* MAL Receive Slot */
940 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
941 hw_p->rx_u_index = 0; /* Receive User Queue Index */
942
943 hw_p->tx_slot = 0; /* MAL Transmit Slot */
944 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
945 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
946
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200947#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +0000948 /* set RMII mode */
949 /* NOTE: 440GX spec states that mode is mutually exclusive */
950 /* NOTE: Therefore, disable all other EMACS, since we handle */
951 /* NOTE: only one emac at a time */
952 reg = 0;
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200953 out_be32((void *)ZMII0_FER, 0);
wdenkba56f622004-02-06 23:19:44 +0000954 udelay (100);
wdenkba56f622004-02-06 23:19:44 +0000955
Stefan Roese8ac41e32008-03-11 15:05:26 +0100956#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200957 out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
Stefan Roese8ac41e32008-03-11 15:05:26 +0100958#elif defined(CONFIG_440GX) || \
959 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
960 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200961 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
wdenk0e6d7982004-03-14 00:07:33 +0000962#endif
Stefan Roesec57c7982005-08-11 17:56:56 +0200963
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200964 out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100965#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200966#if defined(CONFIG_405EX)
967 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
968#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200969
Stefan Roese8ac41e32008-03-11 15:05:26 +0100970 sync();
wdenk0e6d7982004-03-14 00:07:33 +0000971
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200972 /* provide clocks for EMAC internal loopback */
Stefan Roese8ac41e32008-03-11 15:05:26 +0100973 emac_loopback_enable(hw_p);
wdenk0e6d7982004-03-14 00:07:33 +0000974
Stefan Roese8ac41e32008-03-11 15:05:26 +0100975 /* EMAC RESET */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200976 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
wdenkba56f622004-02-06 23:19:44 +0000977
Stefan Roese8ac41e32008-03-11 15:05:26 +0100978 /* remove clocks for EMAC internal loopback */
979 emac_loopback_disable(hw_p);
980
wdenkba56f622004-02-06 23:19:44 +0000981 failsafe = 1000;
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200982 while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
wdenkba56f622004-02-06 23:19:44 +0000983 udelay (1000);
984 failsafe--;
985 }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200986 if (failsafe <= 0)
987 printf("\nProblem resetting EMAC!\n");
wdenkba56f622004-02-06 23:19:44 +0000988
Stefan Roese887e2ec2006-09-07 11:51:23 +0200989#if defined(CONFIG_440GX) || \
990 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200991 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100992 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200993 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000994 /* Whack the M1 register */
995 mode_reg = 0x0;
996 mode_reg &= ~0x00000038;
Felix Radensky0c24dec2009-05-31 20:44:15 +0300997 opbfreq = sysinfo.freqOPB / 1000000;
998 if (opbfreq <= 50);
999 else if (opbfreq <= 66)
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001000 mode_reg |= EMAC_MR1_OBCI_66;
Felix Radensky0c24dec2009-05-31 20:44:15 +03001001 else if (opbfreq <= 83)
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001002 mode_reg |= EMAC_MR1_OBCI_83;
Felix Radensky0c24dec2009-05-31 20:44:15 +03001003 else if (opbfreq <= 100)
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001004 mode_reg |= EMAC_MR1_OBCI_100;
wdenkba56f622004-02-06 23:19:44 +00001005 else
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001006 mode_reg |= EMAC_MR1_OBCI_GT100;
wdenkba56f622004-02-06 23:19:44 +00001007
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001008 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001009#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
wdenkba56f622004-02-06 23:19:44 +00001010
Victor Gallardo78d78232008-09-04 23:49:36 -07001011#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
1012 defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
1013 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
1014 /*
1015 * In SGMII mode, GPCS access is needed for
1016 * communication with the internal SGMII SerDes.
1017 */
1018 switch (devnum) {
1019#if defined(CONFIG_GPCS_PHY_ADDR)
1020 case 0:
1021 reg = CONFIG_GPCS_PHY_ADDR;
1022 break;
1023#endif
1024#if defined(CONFIG_GPCS_PHY1_ADDR)
1025 case 1:
1026 reg = CONFIG_GPCS_PHY1_ADDR;
1027 break;
1028#endif
1029#if defined(CONFIG_GPCS_PHY2_ADDR)
1030 case 2:
1031 reg = CONFIG_GPCS_PHY2_ADDR;
1032 break;
1033#endif
1034#if defined(CONFIG_GPCS_PHY3_ADDR)
1035 case 3:
1036 reg = CONFIG_GPCS_PHY3_ADDR;
1037 break;
1038#endif
1039 }
1040
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001041 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
1042 mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
1043 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
Victor Gallardo78d78232008-09-04 23:49:36 -07001044
1045 /* Configure GPCS interface to recommended setting for SGMII */
1046 miiphy_reset(dev->name, reg);
1047 miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
1048 miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
1049 miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
1050 }
1051#endif /* defined(CONFIG_GPCS_PHY_ADDR) */
1052
wdenkba56f622004-02-06 23:19:44 +00001053 /* wait for PHY to complete auto negotiation */
1054 reg_short = 0;
wdenkba56f622004-02-06 23:19:44 +00001055 switch (devnum) {
1056 case 0:
1057 reg = CONFIG_PHY_ADDR;
1058 break;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001059#if defined (CONFIG_PHY1_ADDR)
wdenkba56f622004-02-06 23:19:44 +00001060 case 1:
1061 reg = CONFIG_PHY1_ADDR;
1062 break;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001063#endif
Stefan Roese4c9e8552008-03-19 16:20:49 +01001064#if defined (CONFIG_PHY2_ADDR)
wdenkba56f622004-02-06 23:19:44 +00001065 case 2:
1066 reg = CONFIG_PHY2_ADDR;
1067 break;
Stefan Roese4c9e8552008-03-19 16:20:49 +01001068#endif
1069#if defined (CONFIG_PHY3_ADDR)
wdenkba56f622004-02-06 23:19:44 +00001070 case 3:
1071 reg = CONFIG_PHY3_ADDR;
1072 break;
1073#endif
1074 default:
1075 reg = CONFIG_PHY_ADDR;
1076 break;
1077 }
1078
wdenk3c74e322004-02-22 23:46:08 +00001079 bis->bi_phynum[devnum] = reg;
1080
Victor Gallardo78d78232008-09-04 23:49:36 -07001081 if (reg == CONFIG_FIXED_PHY)
1082 goto get_speed;
1083
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001084#if defined(CONFIG_PHY_RESET)
wdenka06752e2004-09-29 22:43:59 +00001085 /*
1086 * Reset the phy, only if its the first time through
1087 * otherwise, just check the speeds & feeds
1088 */
1089 if (hw_p->first_init == 0) {
Stefan Roeseec0c2ec2006-11-27 14:46:06 +01001090#if defined(CONFIG_M88E1111_PHY)
Stefan Roese887e2ec2006-09-07 11:51:23 +02001091 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
1092 miiphy_write (dev->name, reg, 0x18, 0x4101);
1093 miiphy_write (dev->name, reg, 0x09, 0x0e00);
1094 miiphy_write (dev->name, reg, 0x04, 0x01e1);
Stefan Roeseca080542010-06-29 09:23:53 +02001095#if defined(CONFIG_M88E1111_DISABLE_FIBER)
1096 miiphy_read(dev->name, reg, 0x1b, &reg_short);
1097 reg_short |= 0x8000;
1098 miiphy_write(dev->name, reg, 0x1b, reg_short);
1099#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +02001100#endif
Victor Gallardo78d78232008-09-04 23:49:36 -07001101#if defined(CONFIG_M88E1112_PHY)
1102 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
1103 /*
1104 * Marvell 88E1112 PHY needs to have the SGMII MAC
1105 * interace (page 2) properly configured to
1106 * communicate with the 460EX/GT GPCS interface.
1107 */
1108
1109 /* Set access to Page 2 */
1110 miiphy_write(dev->name, reg, 0x16, 0x0002);
1111
1112 miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
1113 miiphy_read(dev->name, reg, 0x1a, &reg_short);
1114 reg_short |= 0x8000; /* bypass Auto-Negotiation */
1115 miiphy_write(dev->name, reg, 0x1a, reg_short);
1116 miiphy_reset(dev->name, reg); /* reset MAC interface */
1117
1118 /* Reset access to Page 0 */
1119 miiphy_write(dev->name, reg, 0x16, 0x0000);
1120 }
1121#endif /* defined(CONFIG_M88E1112_PHY) */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001122 miiphy_reset (dev->name, reg);
wdenkba56f622004-02-06 23:19:44 +00001123
Stefan Roese887e2ec2006-09-07 11:51:23 +02001124#if defined(CONFIG_440GX) || \
1125 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01001126 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001127 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +02001128
wdenk0e6d7982004-03-14 00:07:33 +00001129#if defined(CONFIG_CIS8201_PHY)
wdenkfc1cfcd2004-04-25 15:41:35 +00001130 /*
Stefan Roese17f50f222005-08-04 17:09:16 +02001131 * Cicada 8201 PHY needs to have an extended register whacked
1132 * for RGMII mode.
wdenkfc1cfcd2004-04-25 15:41:35 +00001133 */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001134 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
Stefan Roeseb79316f2005-08-15 12:31:23 +02001135#if defined(CONFIG_CIS8201_SHORT_ETCH)
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001136 miiphy_write (dev->name, reg, 23, 0x1300);
Stefan Roeseb79316f2005-08-15 12:31:23 +02001137#else
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001138 miiphy_write (dev->name, reg, 23, 0x1000);
Stefan Roeseb79316f2005-08-15 12:31:23 +02001139#endif
Stefan Roese17f50f222005-08-04 17:09:16 +02001140 /*
1141 * Vitesse VSC8201/Cicada CIS8201 errata:
1142 * Interoperability problem with Intel 82547EI phys
1143 * This work around (provided by Vitesse) changes
1144 * the default timer convergence from 8ms to 12ms
1145 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001146 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1147 miiphy_write (dev->name, reg, 0x08, 0x0200);
1148 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
1149 miiphy_write (dev->name, reg, 0x02, 0x0004);
1150 miiphy_write (dev->name, reg, 0x01, 0x0671);
1151 miiphy_write (dev->name, reg, 0x00, 0x8fae);
1152 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1153 miiphy_write (dev->name, reg, 0x08, 0x0000);
1154 miiphy_write (dev->name, reg, 0x1f, 0x0000);
Stefan Roese17f50f222005-08-04 17:09:16 +02001155 /* end Vitesse/Cicada errata */
1156 }
Stefan Roese6ca86462008-09-05 14:11:40 +02001157#endif /* defined(CONFIG_CIS8201_PHY) */
Stefan Roese5fb692c2007-01-18 10:25:34 +01001158
1159#if defined(CONFIG_ET1011C_PHY)
1160 /*
1161 * Agere ET1011c PHY needs to have an extended register whacked
1162 * for RGMII mode.
1163 */
1164 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
1165 miiphy_read (dev->name, reg, 0x16, &reg_short);
1166 reg_short &= ~(0x7);
1167 reg_short |= 0x6; /* RGMII DLL Delay*/
1168 miiphy_write (dev->name, reg, 0x16, reg_short);
1169
1170 miiphy_read (dev->name, reg, 0x17, &reg_short);
1171 reg_short &= ~(0x40);
1172 miiphy_write (dev->name, reg, 0x17, reg_short);
1173
1174 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
1175 }
Stefan Roese6ca86462008-09-05 14:11:40 +02001176#endif /* defined(CONFIG_ET1011C_PHY) */
Stefan Roese5fb692c2007-01-18 10:25:34 +01001177
Stefan Roese6ca86462008-09-05 14:11:40 +02001178#endif /* defined(CONFIG_440GX) ... */
wdenka06752e2004-09-29 22:43:59 +00001179 /* Start/Restart autonegotiation */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001180 phy_setup_aneg (dev->name, reg);
wdenka06752e2004-09-29 22:43:59 +00001181 udelay (1000);
1182 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001183#endif /* defined(CONFIG_PHY_RESET) */
wdenkba56f622004-02-06 23:19:44 +00001184
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001185 miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
wdenkba56f622004-02-06 23:19:44 +00001186
1187 /*
wdenk0e6d7982004-03-14 00:07:33 +00001188 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
wdenkba56f622004-02-06 23:19:44 +00001189 */
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001190 if ((reg_short & BMSR_ANEGCAPABLE)
1191 && !(reg_short & BMSR_ANEGCOMPLETE)) {
wdenkba56f622004-02-06 23:19:44 +00001192 puts ("Waiting for PHY auto negotiation to complete");
1193 i = 0;
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001194 while (!(reg_short & BMSR_ANEGCOMPLETE)) {
wdenkba56f622004-02-06 23:19:44 +00001195 /*
1196 * Timeout reached ?
1197 */
1198 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
1199 puts (" TIMEOUT !\n");
1200 break;
1201 }
1202
1203 if ((i++ % 1000) == 0) {
1204 putc ('.');
1205 }
1206 udelay (1000); /* 1 ms */
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001207 miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
wdenkba56f622004-02-06 23:19:44 +00001208 }
1209 puts (" done\n");
1210 udelay (500000); /* another 500 ms (results in faster booting) */
1211 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001212
Victor Gallardo78d78232008-09-04 23:49:36 -07001213get_speed:
1214 if (reg == CONFIG_FIXED_PHY) {
1215 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
1216 if (devnum == fixed_phy_port[i].devnum) {
1217 speed = fixed_phy_port[i].speed;
1218 duplex = fixed_phy_port[i].duplex;
1219 break;
1220 }
1221 }
1222
1223 if (i == ARRAY_SIZE(fixed_phy_port)) {
1224 printf("ERROR: PHY (%s) not configured correctly!\n",
1225 dev->name);
1226 return -1;
1227 }
1228 } else {
1229 speed = miiphy_speed(dev->name, reg);
1230 duplex = miiphy_duplex(dev->name, reg);
1231 }
wdenkba56f622004-02-06 23:19:44 +00001232
1233 if (hw_p->print_speed) {
1234 hw_p->print_speed = 0;
Stefan Roese5fb692c2007-01-18 10:25:34 +01001235 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
1236 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
1237 hw_p->devnum);
wdenkba56f622004-02-06 23:19:44 +00001238 }
1239
Stefan Roese8ac41e32008-03-11 15:05:26 +01001240#if defined(CONFIG_440) && \
1241 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
1242 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1243 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
Stefan Roese846b0dd2005-08-08 12:42:22 +02001244#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001245 mfsdr(SDR0_MFR, reg);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001246 if (speed == 100) {
1247 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
1248 } else {
1249 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1250 }
Stefan Roesed1c3b272009-09-09 16:25:29 +02001251 mtsdr(SDR0_MFR, reg);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001252#endif
Stefan Roesec57c7982005-08-11 17:56:56 +02001253
wdenkba56f622004-02-06 23:19:44 +00001254 /* Set ZMII/RGMII speed according to the phy link speed */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001255 reg = in_be32((void *)ZMII0_SSR);
wdenk855a4962004-03-14 18:23:55 +00001256 if ( (speed == 100) || (speed == 1000) )
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001257 out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
wdenkba56f622004-02-06 23:19:44 +00001258 else
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001259 out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
wdenkba56f622004-02-06 23:19:44 +00001260
1261 if ((devnum == 2) || (devnum == 3)) {
1262 if (speed == 1000)
1263 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1264 else if (speed == 100)
1265 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001266 else if (speed == 10)
wdenkba56f622004-02-06 23:19:44 +00001267 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001268 else {
1269 printf("Error in RGMII Speed\n");
1270 return -1;
1271 }
Stefan Roeseff768cb2007-10-31 18:01:24 +01001272 out_be32((void *)RGMII_SSR, reg);
wdenkba56f622004-02-06 23:19:44 +00001273 }
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001274#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
wdenkba56f622004-02-06 23:19:44 +00001275
Stefan Roesedbbd1252007-10-05 17:10:59 +02001276#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01001277 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001278 defined(CONFIG_405EX)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001279 if (devnum >= 2)
1280 rgmii_channel = devnum - 2;
1281 else
1282 rgmii_channel = devnum;
1283
Stefan Roese887e2ec2006-09-07 11:51:23 +02001284 if (speed == 1000)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001285 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001286 else if (speed == 100)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001287 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001288 else if (speed == 10)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001289 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001290 else {
1291 printf("Error in RGMII Speed\n");
1292 return -1;
1293 }
Stefan Roese2d834762007-10-23 14:03:17 +02001294 out_be32((void *)RGMII_SSR, reg);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001295#if defined(CONFIG_460GT)
1296 if ((devnum == 2) || (devnum == 3))
1297 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1298#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +02001299#endif
1300
wdenkba56f622004-02-06 23:19:44 +00001301 /* set the Mal configuration reg */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001302#if defined(CONFIG_440GX) || \
1303 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001304 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01001305 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001306 defined(CONFIG_405EX)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001307 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
Stefan Roese17f50f222005-08-04 17:09:16 +02001308 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1309#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001310 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
wdenkba56f622004-02-06 23:19:44 +00001311 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
Stefan Roese17f50f222005-08-04 17:09:16 +02001312 if (get_pvr() == PVR_440GP_RB) {
Stefan Roesed1c3b272009-09-09 16:25:29 +02001313 mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
Stefan Roese17f50f222005-08-04 17:09:16 +02001314 }
1315#endif
wdenkba56f622004-02-06 23:19:44 +00001316
wdenkba56f622004-02-06 23:19:44 +00001317 /*
1318 * Malloc MAL buffer desciptors, make sure they are
1319 * aligned on cache line boundary size
1320 * (401/403/IOP480 = 16, 405 = 32)
1321 * and doesn't cross cache block boundaries.
1322 */
Stefan Roeseff768cb2007-10-31 18:01:24 +01001323 if (hw_p->first_init == 0) {
1324 debug("*** Allocating descriptor memory ***\n");
wdenkba56f622004-02-06 23:19:44 +00001325
Stefan Roeseff768cb2007-10-31 18:01:24 +01001326 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1327 if (!bd_cached) {
Stefan Roeseb0021442008-07-10 09:58:06 +02001328 printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
Stefan Roeseff768cb2007-10-31 18:01:24 +01001329 return -1;
1330 }
Stefan Roeseb79316f2005-08-15 12:31:23 +02001331
Stefan Roeseff768cb2007-10-31 18:01:24 +01001332#ifdef CONFIG_4xx_DCACHE
Matthias Fuchsba79fde2007-12-14 11:19:56 +01001333 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +01001334 if (!last_used_ea)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001335#if defined(CONFIG_SYS_MEM_TOP_HIDE)
1336 bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
Anatolij Gustschin5e3dca52008-04-17 18:18:00 +02001337#else
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +01001338 bd_uncached = bis->bi_memsize;
Anatolij Gustschin5e3dca52008-04-17 18:18:00 +02001339#endif
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +01001340 else
1341 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1342
1343 last_used_ea = bd_uncached;
Stefan Roeseff768cb2007-10-31 18:01:24 +01001344 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1345 TLB_WORD2_I_ENABLE);
1346#else
1347 bd_uncached = bd_cached;
1348#endif
1349 hw_p->tx_phys = bd_cached;
1350 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1351 hw_p->tx = (mal_desc_t *)(bd_uncached);
1352 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
Marek Vasutc97e74a2011-10-21 14:17:13 +00001353 debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
wdenkba56f622004-02-06 23:19:44 +00001354 }
1355
1356 for (i = 0; i < NUM_TX_BUFF; i++) {
1357 hw_p->tx[i].ctrl = 0;
1358 hw_p->tx[i].data_len = 0;
Stefan Roeseff768cb2007-10-31 18:01:24 +01001359 if (hw_p->first_init == 0)
1360 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1361 L1_CACHE_BYTES);
wdenkba56f622004-02-06 23:19:44 +00001362 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1363 if ((NUM_TX_BUFF - 1) == i)
1364 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1365 hw_p->tx_run[i] = -1;
Marek Vasutc97e74a2011-10-21 14:17:13 +00001366 debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
wdenkba56f622004-02-06 23:19:44 +00001367 }
1368
1369 for (i = 0; i < NUM_RX_BUFF; i++) {
1370 hw_p->rx[i].ctrl = 0;
1371 hw_p->rx[i].data_len = 0;
Stefan Roeseff768cb2007-10-31 18:01:24 +01001372 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
wdenkba56f622004-02-06 23:19:44 +00001373 if ((NUM_RX_BUFF - 1) == i)
1374 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1375 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1376 hw_p->rx_ready[i] = -1;
Marek Vasutc97e74a2011-10-21 14:17:13 +00001377 debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
wdenkba56f622004-02-06 23:19:44 +00001378 }
1379
1380 reg = 0x00000000;
1381
1382 reg |= dev->enetaddr[0]; /* set high address */
1383 reg = reg << 8;
1384 reg |= dev->enetaddr[1];
1385
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001386 out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
wdenkba56f622004-02-06 23:19:44 +00001387
1388 reg = 0x00000000;
1389 reg |= dev->enetaddr[2]; /* set low address */
1390 reg = reg << 8;
1391 reg |= dev->enetaddr[3];
1392 reg = reg << 8;
1393 reg |= dev->enetaddr[4];
1394 reg = reg << 8;
1395 reg |= dev->enetaddr[5];
1396
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001397 out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
wdenkba56f622004-02-06 23:19:44 +00001398
1399 switch (devnum) {
1400 case 1:
1401 /* setup MAL tx & rx channel pointers */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001402#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001403 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001404#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001405 mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001406#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001407#if defined(CONFIG_440)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001408 mtdcr (MAL0_TXBADDR, 0x0);
1409 mtdcr (MAL0_RXBADDR, 0x0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001410#endif
Stefan Roese8ac41e32008-03-11 15:05:26 +01001411
1412#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001413 mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001414 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001415 mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001416#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001417 mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001418 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001419 mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001420#endif
wdenkba56f622004-02-06 23:19:44 +00001421 break;
Stefan Roese846b0dd2005-08-08 12:42:22 +02001422#if defined (CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001423 case 2:
1424 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001425 mtdcr (MAL0_TXBADDR, 0x0);
1426 mtdcr (MAL0_RXBADDR, 0x0);
1427 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
1428 mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001429 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001430 mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
wdenkba56f622004-02-06 23:19:44 +00001431 break;
1432 case 3:
1433 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001434 mtdcr (MAL0_TXBADDR, 0x0);
1435 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
1436 mtdcr (MAL0_RXBADDR, 0x0);
1437 mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001438 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001439 mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
wdenkba56f622004-02-06 23:19:44 +00001440 break;
Stefan Roesec57c7982005-08-11 17:56:56 +02001441#endif /* CONFIG_440GX */
Stefan Roese4c9e8552008-03-19 16:20:49 +01001442#if defined (CONFIG_460GT)
1443 case 2:
1444 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001445 mtdcr (MAL0_TXBADDR, 0x0);
1446 mtdcr (MAL0_RXBADDR, 0x0);
1447 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
1448 mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001449 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001450 mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001451 break;
1452 case 3:
1453 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001454 mtdcr (MAL0_TXBADDR, 0x0);
1455 mtdcr (MAL0_RXBADDR, 0x0);
1456 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
1457 mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001458 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001459 mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001460 break;
1461#endif /* CONFIG_460GT */
wdenkba56f622004-02-06 23:19:44 +00001462 case 0:
1463 default:
1464 /* setup MAL tx & rx channel pointers */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001465#if defined(CONFIG_440)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001466 mtdcr (MAL0_TXBADDR, 0x0);
1467 mtdcr (MAL0_RXBADDR, 0x0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001468#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +02001469 mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
1470 mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001471 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001472 mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
wdenkba56f622004-02-06 23:19:44 +00001473 break;
1474 }
1475
1476 /* Enable MAL transmit and receive channels */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001477#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001478 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
Stefan Roesec157d8e2005-08-01 16:41:48 +02001479#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001480 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
Stefan Roesec157d8e2005-08-01 16:41:48 +02001481#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +02001482 mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
wdenkba56f622004-02-06 23:19:44 +00001483
1484 /* set transmit enable & receive enable */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001485 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
wdenkba56f622004-02-06 23:19:44 +00001486
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001487 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
Stefan Roese76957cb2008-03-01 12:11:40 +01001488
1489 /* set rx-/tx-fifo size */
1490 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
wdenkba56f622004-02-06 23:19:44 +00001491
1492 /* set speed */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001493 if (speed == _1000BASET) {
Stefan Roese5e7abce2010-09-11 09:31:43 +02001494#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001495 unsigned long pfc1;
Stefan Roese887e2ec2006-09-07 11:51:23 +02001496
Stefan Roesed1c3b272009-09-09 16:25:29 +02001497 mfsdr (SDR0_PFC1, pfc1);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001498 pfc1 |= SDR0_PFC1_EM_1000;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001499 mtsdr (SDR0_PFC1, pfc1);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001500#endif
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001501 mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001502 } else if (speed == _100BASET)
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001503 mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
wdenkba56f622004-02-06 23:19:44 +00001504 else
1505 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1506 if (duplex == FULL)
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001507 mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
wdenkba56f622004-02-06 23:19:44 +00001508
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001509 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
wdenkba56f622004-02-06 23:19:44 +00001510
1511 /* Enable broadcast and indvidual address */
1512 /* TBS: enabling runts as some misbehaved nics will send runts */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001513 out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
wdenkba56f622004-02-06 23:19:44 +00001514
1515 /* we probably need to set the tx mode1 reg? maybe at tx time */
1516
1517 /* set transmit request threshold register */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001518 out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
wdenkba56f622004-02-06 23:19:44 +00001519
Wolfgang Denk265817c2005-09-25 00:53:22 +02001520 /* set receive low/high water mark register */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001521#if defined(CONFIG_440)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001522 /* 440s has a 64 byte burst length */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001523 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001524#else
1525 /* 405s have a 16 byte burst length */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001526 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001527#endif /* defined(CONFIG_440) */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001528 out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
wdenkba56f622004-02-06 23:19:44 +00001529
1530 /* Set fifo limit entry in tx mode 0 */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001531 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
wdenkba56f622004-02-06 23:19:44 +00001532 /* Frame gap set */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001533 out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
wdenkba56f622004-02-06 23:19:44 +00001534
1535 /* Set EMAC IER */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001536 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
wdenkba56f622004-02-06 23:19:44 +00001537 if (speed == _100BASET)
1538 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1539
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001540 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1541 out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
wdenkba56f622004-02-06 23:19:44 +00001542
1543 if (hw_p->first_init == 0) {
1544 /*
1545 * Connect interrupt service routines
1546 */
Stefan Roesedbbd1252007-10-05 17:10:59 +02001547 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1548 (interrupt_handler_t *) enetInt, dev);
wdenkba56f622004-02-06 23:19:44 +00001549 }
wdenkba56f622004-02-06 23:19:44 +00001550
1551 mtmsr (msr); /* enable interrupts again */
1552
1553 hw_p->bis = bis;
1554 hw_p->first_init = 1;
1555
Stefan Roese802b7692008-01-08 18:39:30 +01001556 return 0;
wdenkba56f622004-02-06 23:19:44 +00001557}
1558
1559
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001560static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
wdenkba56f622004-02-06 23:19:44 +00001561 int len)
1562{
1563 struct enet_frame *ef_ptr;
1564 ulong time_start, time_now;
1565 unsigned long temp_txm0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001566 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001567
1568 ef_ptr = (struct enet_frame *) ptr;
1569
1570 /*-----------------------------------------------------------------------+
1571 * Copy in our address into the frame.
1572 *-----------------------------------------------------------------------*/
1573 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1574
1575 /*-----------------------------------------------------------------------+
1576 * If frame is too long or too short, modify length.
1577 *-----------------------------------------------------------------------*/
1578 /* TBS: where does the fragment go???? */
1579 if (len > ENET_MAX_MTU)
1580 len = ENET_MAX_MTU;
1581
1582 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1583 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
Matthias Fuchsba79fde2007-12-14 11:19:56 +01001584 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
wdenkba56f622004-02-06 23:19:44 +00001585
1586 /*-----------------------------------------------------------------------+
1587 * set TX Buffer busy, and send it
1588 *-----------------------------------------------------------------------*/
1589 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1590 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1591 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1592 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1593 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1594
1595 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1596 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1597
Stefan Roese8ac41e32008-03-11 15:05:26 +01001598 sync();
wdenkba56f622004-02-06 23:19:44 +00001599
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001600 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
1601 in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001602#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001603 hw_p->stats.pkts_tx++;
1604#endif
1605
1606 /*-----------------------------------------------------------------------+
1607 * poll unitl the packet is sent and then make sure it is OK
1608 *-----------------------------------------------------------------------*/
1609 time_start = get_timer (0);
1610 while (1) {
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001611 temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +00001612 /* loop until either TINT turns on or 3 seconds elapse */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001613 if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
wdenkba56f622004-02-06 23:19:44 +00001614 /* transmit is done, so now check for errors
1615 * If there is an error, an interrupt should
1616 * happen when we return
1617 */
1618 time_now = get_timer (0);
1619 if ((time_now - time_start) > 3000) {
1620 return (-1);
1621 }
1622 } else {
1623 return (len);
1624 }
1625 }
1626}
1627
wdenkba56f622004-02-06 23:19:44 +00001628int enetInt (struct eth_device *dev)
1629{
1630 int serviced;
1631 int rc = -1; /* default to not us */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001632 u32 mal_isr;
1633 u32 emac_isr = 0;
1634 u32 mal_eob;
1635 u32 uic_mal;
1636 u32 uic_mal_err;
1637 u32 uic_emac;
1638 u32 uic_emac_b;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001639 EMAC_4XX_HW_PST hw_p;
wdenkba56f622004-02-06 23:19:44 +00001640
1641 /*
1642 * Because the mal is generic, we need to get the current
1643 * eth device
1644 */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001645 dev = eth_get_dev();
wdenkba56f622004-02-06 23:19:44 +00001646
1647 hw_p = dev->priv;
1648
wdenkba56f622004-02-06 23:19:44 +00001649 /* enter loop that stays in interrupt code until nothing to service */
1650 do {
1651 serviced = 0;
1652
Stefan Roesed1631fe2008-06-26 13:40:57 +02001653 uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
1654 uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
1655 uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
1656 uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
Stefan Roese887e2ec2006-09-07 11:51:23 +02001657
Stefan Roesed1631fe2008-06-26 13:40:57 +02001658 if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
1659 && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
1660 && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
wdenkba56f622004-02-06 23:19:44 +00001661 /* not for us */
1662 return (rc);
1663 }
Stefan Roesed1631fe2008-06-26 13:40:57 +02001664
wdenkba56f622004-02-06 23:19:44 +00001665 /* get and clear controller status interrupts */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001666 /* look at MAL and EMAC error interrupts */
1667 if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
1668 /* we have a MAL error interrupt */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001669 mal_isr = mfdcr(MAL0_ESR);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001670 mal_err(dev, mal_isr, uic_mal_err,
1671 MAL_UIC_DEF, MAL_UIC_ERR);
1672
1673 /* clear MAL error interrupt status bits */
1674 mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
1675 UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
1676
1677 return -1;
wdenkba56f622004-02-06 23:19:44 +00001678 }
1679
Stefan Roesed1631fe2008-06-26 13:40:57 +02001680 /* look for EMAC errors */
1681 if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001682 emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001683 emac_err(dev, emac_isr);
wdenkba56f622004-02-06 23:19:44 +00001684
Stefan Roesed1631fe2008-06-26 13:40:57 +02001685 /* clear EMAC error interrupt status bits */
1686 mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
1687 mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
wdenkba56f622004-02-06 23:19:44 +00001688
Stefan Roesed1631fe2008-06-26 13:40:57 +02001689 return -1;
wdenkba56f622004-02-06 23:19:44 +00001690 }
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001691
wdenkba56f622004-02-06 23:19:44 +00001692 /* handle MAX TX EOB interrupt from a tx */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001693 if (uic_mal & UIC_MAL_TXEOB) {
1694 /* clear MAL interrupt status bits */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001695 mal_eob = mfdcr(MAL0_TXEOBISR);
1696 mtdcr(MAL0_TXEOBISR, mal_eob);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001697 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
1698
1699 /* indicate that we serviced an interrupt */
1700 serviced = 1;
1701 rc = 0;
wdenkba56f622004-02-06 23:19:44 +00001702 }
Stefan Roesed1631fe2008-06-26 13:40:57 +02001703
Mike Williams16263082011-07-22 04:01:30 +00001704 /* handle MAL RX EOB interrupt from a receive */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001705 /* check for EOB on valid channels */
1706 if (uic_mal & UIC_MAL_RXEOB) {
Stefan Roesed1c3b272009-09-09 16:25:29 +02001707 mal_eob = mfdcr(MAL0_RXEOBISR);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001708 if (mal_eob &
1709 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
1710 /* push packet to upper layer */
1711 enet_rcv(dev, emac_isr);
1712
1713 /* clear MAL interrupt status bits */
1714 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
1715
wdenkba56f622004-02-06 23:19:44 +00001716 /* indicate that we serviced an interrupt */
1717 serviced = 1;
1718 rc = 0;
1719 }
1720 }
James Cloughc0b46d82009-09-10 09:11:50 +02001721#if defined(CONFIG_405EZ)
1722 /*
1723 * On 405EZ the RX-/TX-interrupts are coalesced into
1724 * one IRQ bit in the UIC. We need to acknowledge the
1725 * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
1726 */
1727 mtsdr(SDR0_ICINTSTAT,
1728 SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1729#endif /* defined(CONFIG_405EZ) */
wdenkba56f622004-02-06 23:19:44 +00001730 } while (serviced);
1731
1732 return (rc);
1733}
1734
1735/*-----------------------------------------------------------------------------+
1736 * MAL Error Routine
1737 *-----------------------------------------------------------------------------*/
1738static void mal_err (struct eth_device *dev, unsigned long isr,
1739 unsigned long uic, unsigned long maldef,
1740 unsigned long mal_errr)
1741{
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001742 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001743
Stefan Roesed1c3b272009-09-09 16:25:29 +02001744 mtdcr (MAL0_ESR, isr); /* clear interrupt */
wdenkba56f622004-02-06 23:19:44 +00001745
1746 /* clear DE interrupt */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001747 mtdcr (MAL0_TXDEIR, 0xC0000000);
1748 mtdcr (MAL0_RXDEIR, 0x80000000);
wdenkba56f622004-02-06 23:19:44 +00001749
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001750#ifdef INFO_4XX_ENET
Wolfgang Denk265817c2005-09-25 00:53:22 +02001751 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
wdenkba56f622004-02-06 23:19:44 +00001752#endif
1753
1754 eth_init (hw_p->bis); /* start again... */
1755}
1756
1757/*-----------------------------------------------------------------------------+
1758 * EMAC Error Routine
1759 *-----------------------------------------------------------------------------*/
1760static void emac_err (struct eth_device *dev, unsigned long isr)
1761{
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001762 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001763
1764 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001765 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
wdenkba56f622004-02-06 23:19:44 +00001766}
1767
1768/*-----------------------------------------------------------------------------+
1769 * enet_rcv() handles the ethernet receive data
1770 *-----------------------------------------------------------------------------*/
1771static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1772{
wdenkba56f622004-02-06 23:19:44 +00001773 unsigned long data_len;
1774 unsigned long rx_eob_isr;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001775 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001776
1777 int handled = 0;
1778 int i;
1779 int loop_count = 0;
1780
Stefan Roesed1c3b272009-09-09 16:25:29 +02001781 rx_eob_isr = mfdcr (MAL0_RXEOBISR);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001782 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
wdenkba56f622004-02-06 23:19:44 +00001783 /* clear EOB */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001784 mtdcr (MAL0_RXEOBISR, rx_eob_isr);
wdenkba56f622004-02-06 23:19:44 +00001785
1786 /* EMAC RX done */
1787 while (1) { /* do all */
1788 i = hw_p->rx_slot;
1789
1790 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1791 || (loop_count >= NUM_RX_BUFF))
1792 break;
Stefan Roesea2e1c702007-07-12 16:32:08 +02001793
wdenkba56f622004-02-06 23:19:44 +00001794 loop_count++;
wdenkba56f622004-02-06 23:19:44 +00001795 handled++;
Stefan Roese8ac41e32008-03-11 15:05:26 +01001796 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
wdenkba56f622004-02-06 23:19:44 +00001797 if (data_len) {
1798 if (data_len > ENET_MAX_MTU) /* Check len */
1799 data_len = 0;
1800 else {
1801 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1802 data_len = 0;
1803 hw_p->stats.rx_err_log[hw_p->
1804 rx_err_index]
1805 = hw_p->rx[i].ctrl;
1806 hw_p->rx_err_index++;
1807 if (hw_p->rx_err_index ==
1808 MAX_ERR_LOG)
1809 hw_p->rx_err_index =
1810 0;
wdenkfc1cfcd2004-04-25 15:41:35 +00001811 } /* emac_erros */
wdenkba56f622004-02-06 23:19:44 +00001812 } /* data_len < max mtu */
wdenkfc1cfcd2004-04-25 15:41:35 +00001813 } /* if data_len */
wdenkba56f622004-02-06 23:19:44 +00001814 if (!data_len) { /* no data */
1815 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1816
1817 hw_p->stats.data_len_err++; /* Error at Rx */
1818 }
1819
1820 /* !data_len */
1821 /* AS.HARNOIS */
1822 /* Check if user has already eaten buffer */
1823 /* if not => ERROR */
1824 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1825 if (hw_p->is_receiving)
1826 printf ("ERROR : Receive buffers are full!\n");
1827 break;
1828 } else {
1829 hw_p->stats.rx_frames++;
1830 hw_p->stats.rx += data_len;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001831#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001832 hw_p->stats.pkts_rx++;
1833#endif
1834 /* AS.HARNOIS
1835 * use ring buffer
1836 */
1837 hw_p->rx_ready[hw_p->rx_i_index] = i;
1838 hw_p->rx_i_index++;
1839 if (NUM_RX_BUFF == hw_p->rx_i_index)
1840 hw_p->rx_i_index = 0;
1841
Stefan Roesea2e1c702007-07-12 16:32:08 +02001842 hw_p->rx_slot++;
1843 if (NUM_RX_BUFF == hw_p->rx_slot)
1844 hw_p->rx_slot = 0;
1845
wdenkba56f622004-02-06 23:19:44 +00001846 /* AS.HARNOIS
1847 * free receive buffer only when
1848 * buffer has been handled (eth_rx)
1849 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1850 */
1851 } /* if data_len */
1852 } /* while */
1853 } /* if EMACK_RXCHL */
1854}
1855
1856
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001857static int ppc_4xx_eth_rx (struct eth_device *dev)
wdenkba56f622004-02-06 23:19:44 +00001858{
1859 int length;
1860 int user_index;
1861 unsigned long msr;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001862 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001863
Wolfgang Denk265817c2005-09-25 00:53:22 +02001864 hw_p->is_receiving = 1; /* tell driver */
wdenkba56f622004-02-06 23:19:44 +00001865
1866 for (;;) {
1867 /* AS.HARNOIS
1868 * use ring buffer and
1869 * get index from rx buffer desciptor queue
1870 */
1871 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1872 if (user_index == -1) {
1873 length = -1;
1874 break; /* nothing received - leave for() loop */
1875 }
1876
1877 msr = mfmsr ();
1878 mtmsr (msr & ~(MSR_EE));
1879
Stefan Roese8ac41e32008-03-11 15:05:26 +01001880 length = hw_p->rx[user_index].data_len & 0x0fff;
wdenkba56f622004-02-06 23:19:44 +00001881
1882 /* Pass the packet up to the protocol layers. */
Wolfgang Denk265817c2005-09-25 00:53:22 +02001883 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1884 /* NetReceive(NetRxPackets[i], length); */
Stefan Roeseff768cb2007-10-31 18:01:24 +01001885 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1886 (u32)hw_p->rx[user_index].data_ptr +
Matthias Fuchsba79fde2007-12-14 11:19:56 +01001887 length - 4);
wdenkba56f622004-02-06 23:19:44 +00001888 NetReceive (NetRxPackets[user_index], length - 4);
1889 /* Free Recv Buffer */
1890 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1891 /* Free rx buffer descriptor queue */
1892 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1893 hw_p->rx_u_index++;
1894 if (NUM_RX_BUFF == hw_p->rx_u_index)
1895 hw_p->rx_u_index = 0;
1896
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001897#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001898 hw_p->stats.pkts_handled++;
1899#endif
1900
1901 mtmsr (msr); /* Enable IRQ's */
1902 }
1903
Wolfgang Denk265817c2005-09-25 00:53:22 +02001904 hw_p->is_receiving = 0; /* tell driver */
wdenkba56f622004-02-06 23:19:44 +00001905
1906 return length;
1907}
1908
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001909int ppc_4xx_eth_initialize (bd_t * bis)
wdenkba56f622004-02-06 23:19:44 +00001910{
1911 static int virgin = 0;
wdenkba56f622004-02-06 23:19:44 +00001912 struct eth_device *dev;
1913 int eth_num = 0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001914 EMAC_4XX_HW_PST hw = NULL;
Stefan Roese5fb692c2007-01-18 10:25:34 +01001915 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1916 u32 hw_addr[4];
Stefan Roesed1631fe2008-06-26 13:40:57 +02001917 u32 mal_ier;
wdenkba56f622004-02-06 23:19:44 +00001918
Stefan Roese846b0dd2005-08-08 12:42:22 +02001919#if defined(CONFIG_440GX)
Stefan Roesec157d8e2005-08-01 16:41:48 +02001920 unsigned long pfc1;
1921
Stefan Roesed1c3b272009-09-09 16:25:29 +02001922 mfsdr (SDR0_PFC1, pfc1);
wdenkba56f622004-02-06 23:19:44 +00001923 pfc1 &= ~(0x01e00000);
1924 pfc1 |= 0x01200000;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001925 mtsdr (SDR0_PFC1, pfc1);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001926#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +01001927
1928 /* first clear all mac-addresses */
1929 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1930 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1931
1932 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
Mike Frysingerd3f87142009-02-11 19:01:26 -05001933 int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
Stefan Roese5fb692c2007-01-18 10:25:34 +01001934 switch (eth_num) {
1935 default: /* fall through */
1936 case 0:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001937 eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
Stefan Roese5fb692c2007-01-18 10:25:34 +01001938 hw_addr[eth_num] = 0x0;
1939 break;
1940#ifdef CONFIG_HAS_ETH1
1941 case 1:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001942 eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
Stefan Roese5fb692c2007-01-18 10:25:34 +01001943 hw_addr[eth_num] = 0x100;
1944 break;
1945#endif
1946#ifdef CONFIG_HAS_ETH2
1947 case 2:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001948 eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001949#if defined(CONFIG_460GT)
1950 hw_addr[eth_num] = 0x300;
1951#else
Stefan Roese5fb692c2007-01-18 10:25:34 +01001952 hw_addr[eth_num] = 0x400;
Stefan Roese4c9e8552008-03-19 16:20:49 +01001953#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +01001954 break;
1955#endif
1956#ifdef CONFIG_HAS_ETH3
1957 case 3:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001958 eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001959#if defined(CONFIG_460GT)
1960 hw_addr[eth_num] = 0x400;
1961#else
Stefan Roese5fb692c2007-01-18 10:25:34 +01001962 hw_addr[eth_num] = 0x600;
Stefan Roese4c9e8552008-03-19 16:20:49 +01001963#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +01001964 break;
1965#endif
1966 }
1967 }
1968
wdenk3c74e322004-02-22 23:46:08 +00001969 /* set phy num and mode */
1970 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001971 bis->bi_phymode[0] = 0;
1972
Stefan Roesec157d8e2005-08-01 16:41:48 +02001973#if defined(CONFIG_PHY1_ADDR)
wdenk3c74e322004-02-22 23:46:08 +00001974 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001975 bis->bi_phymode[1] = 0;
Stefan Roesec157d8e2005-08-01 16:41:48 +02001976#endif
Stefan Roese846b0dd2005-08-08 12:42:22 +02001977#if defined(CONFIG_440GX)
wdenk3c74e322004-02-22 23:46:08 +00001978 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1979 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
wdenk3c74e322004-02-22 23:46:08 +00001980 bis->bi_phymode[2] = 2;
1981 bis->bi_phymode[3] = 2;
Stefan Roesedbbd1252007-10-05 17:10:59 +02001982#endif
wdenkba56f622004-02-06 23:19:44 +00001983
Stefan Roesedbbd1252007-10-05 17:10:59 +02001984#if defined(CONFIG_440GX) || \
1985 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1986 defined(CONFIG_405EX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001987 ppc_4xx_eth_setup_bridge(0, bis);
wdenka06752e2004-09-29 22:43:59 +00001988#endif
1989
Stefan Roese1e25f952005-10-20 16:34:28 +02001990 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
Stefan Roese5fb692c2007-01-18 10:25:34 +01001991 /*
1992 * See if we can actually bring up the interface,
1993 * otherwise, skip it
1994 */
1995 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1996 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1997 continue;
wdenkba56f622004-02-06 23:19:44 +00001998 }
1999
2000 /* Allocate device structure */
2001 dev = (struct eth_device *) malloc (sizeof (*dev));
2002 if (dev == NULL) {
Stefan Roesed6c61aa2005-08-16 18:18:00 +02002003 printf ("ppc_4xx_eth_initialize: "
wdenk3f85ce22004-02-23 16:11:30 +00002004 "Cannot allocate eth_device %d\n", eth_num);
wdenkba56f622004-02-06 23:19:44 +00002005 return (-1);
2006 }
wdenkb2532ef2005-06-20 10:17:34 +00002007 memset(dev, 0, sizeof(*dev));
wdenkba56f622004-02-06 23:19:44 +00002008
2009 /* Allocate our private use data */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02002010 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
wdenkba56f622004-02-06 23:19:44 +00002011 if (hw == NULL) {
Stefan Roesed6c61aa2005-08-16 18:18:00 +02002012 printf ("ppc_4xx_eth_initialize: "
wdenk3f85ce22004-02-23 16:11:30 +00002013 "Cannot allocate private hw data for eth_device %d",
wdenkba56f622004-02-06 23:19:44 +00002014 eth_num);
2015 free (dev);
2016 return (-1);
2017 }
wdenkb2532ef2005-06-20 10:17:34 +00002018 memset(hw, 0, sizeof(*hw));
wdenkba56f622004-02-06 23:19:44 +00002019
Stefan Roese5fb692c2007-01-18 10:25:34 +01002020 hw->hw_addr = hw_addr[eth_num];
2021 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
wdenkba56f622004-02-06 23:19:44 +00002022 hw->devnum = eth_num;
Stefan Roesec157d8e2005-08-01 16:41:48 +02002023 hw->print_speed = 1;
wdenkba56f622004-02-06 23:19:44 +00002024
Stefan Roese5fb692c2007-01-18 10:25:34 +01002025 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
wdenkba56f622004-02-06 23:19:44 +00002026 dev->priv = (void *) hw;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02002027 dev->init = ppc_4xx_eth_init;
2028 dev->halt = ppc_4xx_eth_halt;
2029 dev->send = ppc_4xx_eth_send;
2030 dev->recv = ppc_4xx_eth_rx;
wdenkba56f622004-02-06 23:19:44 +00002031
Stefan Roese3ce04d92011-07-12 13:26:47 +02002032 eth_register(dev);
2033
2034#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2035 miiphy_register(dev->name,
2036 emac4xx_miiphy_read, emac4xx_miiphy_write);
2037#endif
2038
wdenkba56f622004-02-06 23:19:44 +00002039 if (0 == virgin) {
2040 /* set the MAL IER ??? names may change with new spec ??? */
Stefan Roesedbbd1252007-10-05 17:10:59 +02002041#if defined(CONFIG_440SPE) || \
2042 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01002043 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02002044 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02002045 mal_ier =
2046 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
2047 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
2048#else
wdenkba56f622004-02-06 23:19:44 +00002049 mal_ier =
2050 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
2051 MAL_IER_OPBE | MAL_IER_PLBE;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02002052#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +02002053 mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
2054 mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
2055 mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
2056 mtdcr (MAL0_IER, mal_ier);
wdenkba56f622004-02-06 23:19:44 +00002057
2058 /* install MAL interrupt handler */
Stefan Roesed1631fe2008-06-26 13:40:57 +02002059 irq_install_handler (VECNUM_MAL_SERR,
wdenkba56f622004-02-06 23:19:44 +00002060 (interrupt_handler_t *) enetInt,
2061 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002062 irq_install_handler (VECNUM_MAL_TXEOB,
wdenkba56f622004-02-06 23:19:44 +00002063 (interrupt_handler_t *) enetInt,
2064 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002065 irq_install_handler (VECNUM_MAL_RXEOB,
wdenkba56f622004-02-06 23:19:44 +00002066 (interrupt_handler_t *) enetInt,
2067 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002068 irq_install_handler (VECNUM_MAL_TXDE,
wdenkba56f622004-02-06 23:19:44 +00002069 (interrupt_handler_t *) enetInt,
2070 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002071 irq_install_handler (VECNUM_MAL_RXDE,
wdenkba56f622004-02-06 23:19:44 +00002072 (interrupt_handler_t *) enetInt,
2073 dev);
2074 virgin = 1;
2075 }
wdenkba56f622004-02-06 23:19:44 +00002076 } /* end for each supported device */
Stefan Roese802b7692008-01-08 18:39:30 +01002077
2078 return 0;
wdenkba56f622004-02-06 23:19:44 +00002079}