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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Michal Simek5ed063d2018-07-23 15:55:13 +020017 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010018 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010019 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +010021 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Michal Simek5ed063d2018-07-23 15:55:13 +020023 select SUPPORTS_LITTLE_ENDIAN
Masahiro Yamadadd840582014-07-30 14:08:14 +090024
25config TARGET_MALTA
26 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +010027 select DM
28 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +000029 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +010030 select MIPS_CM
Michal Simek5ed063d2018-07-23 15:55:13 +020031 select MIPS_L1_CACHE_SHIFT_6
Paul Burton566ce04d2016-09-21 11:18:56 +010032 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +010033 select OF_CONTROL
34 select OF_ISA_BUS
Michal Simek5ed063d2018-07-23 15:55:13 +020035 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010036 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010037 select SUPPORTS_CPU_MIPS32_R1
38 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010039 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010040 select SUPPORTS_CPU_MIPS64_R1
41 select SUPPORTS_CPU_MIPS64_R2
42 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +020043 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010044 select SWAP_IO_SPACE
Masahiro Yamadadd840582014-07-30 14:08:14 +090045
46config TARGET_VCT
47 bool "Support vct"
Michal Simek5ed063d2018-07-23 15:55:13 +020048 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010049 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010050 select SUPPORTS_CPU_MIPS32_R1
51 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000052 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090053
54config TARGET_DBAU1X00
55 bool "Support dbau1x00"
Michal Simek5ed063d2018-07-23 15:55:13 +020056 select MIPS_TUNE_4KC
57 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010058 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010059 select SUPPORTS_CPU_MIPS32_R1
60 select SUPPORTS_CPU_MIPS32_R2
Michal Simek5ed063d2018-07-23 15:55:13 +020061 select SUPPORTS_LITTLE_ENDIAN
Paul Burtondd7c7202015-01-29 01:28:02 +000062 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090063
64config TARGET_PB1X00
65 bool "Support pb1x00"
Michal Simek5ed063d2018-07-23 15:55:13 +020066 select MIPS_TUNE_4KC
67 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010068 select SUPPORTS_CPU_MIPS32_R1
69 select SUPPORTS_CPU_MIPS32_R2
Michal Simek5ed063d2018-07-23 15:55:13 +020070 select SUPPORTS_LITTLE_ENDIAN
Paul Burtondd7c7202015-01-29 01:28:02 +000071 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090072
Wills Wang1d3d0f12016-03-16 16:59:52 +080073config ARCH_ATH79
74 bool "Support QCA/Atheros ath79"
Wills Wang1d3d0f12016-03-16 16:59:52 +080075 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +020076 select OF_CONTROL
Wills Wang1d3d0f12016-03-16 16:59:52 +080077
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020078config ARCH_BMIPS
79 bool "Support BMIPS SoCs"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020080 select CLK
81 select CPU
Michal Simek5ed063d2018-07-23 15:55:13 +020082 select DM
83 select OF_CONTROL
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020084 select RAM
85 select SYSRESET
86
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053087config MACH_PIC32
88 bool "Support Microchip PIC32"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053089 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +020090 select OF_CONTROL
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053091
Paul Burtonad8783c2016-09-08 07:47:39 +010092config TARGET_BOSTON
93 bool "Support Boston"
94 select DM
95 select DM_SERIAL
Paul Burtonad8783c2016-09-08 07:47:39 +010096 select MIPS_CM
97 select MIPS_L1_CACHE_SHIFT_6
98 select MIPS_L2_CACHE
Paul Burtond2b12a52017-04-30 21:22:42 +020099 select OF_BOARD_SETUP
Michal Simek5ed063d2018-07-23 15:55:13 +0200100 select OF_CONTROL
101 select ROM_EXCEPTION_VECTORS
Paul Burtonad8783c2016-09-08 07:47:39 +0100102 select SUPPORTS_BIG_ENDIAN
Paul Burtonad8783c2016-09-08 07:47:39 +0100103 select SUPPORTS_CPU_MIPS32_R1
104 select SUPPORTS_CPU_MIPS32_R2
105 select SUPPORTS_CPU_MIPS32_R6
106 select SUPPORTS_CPU_MIPS64_R1
107 select SUPPORTS_CPU_MIPS64_R2
108 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +0200109 select SUPPORTS_LITTLE_ENDIAN
Paul Burtonad8783c2016-09-08 07:47:39 +0100110
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100111config TARGET_XILFPGA
112 bool "Support Imagination Xilfpga"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100113 select DM
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100114 select DM_ETH
Michal Simek5ed063d2018-07-23 15:55:13 +0200115 select DM_GPIO
116 select DM_SERIAL
117 select MIPS_L1_CACHE_SHIFT_4
118 select OF_CONTROL
119 select ROM_EXCEPTION_VECTORS
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100120 select SUPPORTS_CPU_MIPS32_R1
121 select SUPPORTS_CPU_MIPS32_R2
Michal Simek5ed063d2018-07-23 15:55:13 +0200122 select SUPPORTS_LITTLE_ENDIAN
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100123 help
124 This supports IMGTEC MIPSfpga platform
125
Masahiro Yamadadd840582014-07-30 14:08:14 +0900126endchoice
127
128source "board/dbau1x00/Kconfig"
Paul Burtonad8783c2016-09-08 07:47:39 +0100129source "board/imgtec/boston/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900130source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100131source "board/imgtec/xilfpga/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900132source "board/micronas/vct/Kconfig"
133source "board/pb1x00/Kconfig"
134source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800135source "arch/mips/mach-ath79/Kconfig"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +0200136source "arch/mips/mach-bmips/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530137source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900138
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100139if MIPS
140
141choice
142 prompt "Endianness selection"
143 help
144 Some MIPS boards can be configured for either little or big endian
145 byte order. These modes require different U-Boot images. In general there
146 is one preferred byteorder for a particular system but some systems are
147 just as commonly used in the one or the other endianness.
148
149config SYS_BIG_ENDIAN
150 bool "Big endian"
151 depends on SUPPORTS_BIG_ENDIAN
152
153config SYS_LITTLE_ENDIAN
154 bool "Little endian"
155 depends on SUPPORTS_LITTLE_ENDIAN
156
157endchoice
158
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100159choice
160 prompt "CPU selection"
161 default CPU_MIPS32_R2
162
163config CPU_MIPS32_R1
164 bool "MIPS32 Release 1"
165 depends on SUPPORTS_CPU_MIPS32_R1
166 select 32BIT
167 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100168 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100169 MIPS32 architecture.
170
171config CPU_MIPS32_R2
172 bool "MIPS32 Release 2"
173 depends on SUPPORTS_CPU_MIPS32_R2
174 select 32BIT
175 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100176 Choose this option to build an U-Boot for release 2 through 5 of the
177 MIPS32 architecture.
178
179config CPU_MIPS32_R6
180 bool "MIPS32 Release 6"
181 depends on SUPPORTS_CPU_MIPS32_R6
182 select 32BIT
183 help
184 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100185 MIPS32 architecture.
186
187config CPU_MIPS64_R1
188 bool "MIPS64 Release 1"
189 depends on SUPPORTS_CPU_MIPS64_R1
190 select 64BIT
191 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100192 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100193 MIPS64 architecture.
194
195config CPU_MIPS64_R2
196 bool "MIPS64 Release 2"
197 depends on SUPPORTS_CPU_MIPS64_R2
198 select 64BIT
199 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100200 Choose this option to build a kernel for release 2 through 5 of the
201 MIPS64 architecture.
202
203config CPU_MIPS64_R6
204 bool "MIPS64 Release 6"
205 depends on SUPPORTS_CPU_MIPS64_R6
206 select 64BIT
207 help
208 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100209 MIPS64 architecture.
210
211endchoice
212
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100213menu "General setup"
214
215config ROM_EXCEPTION_VECTORS
216 bool "Build U-Boot image with exception vectors"
217 help
218 Enable this to include exception vectors in the U-Boot image. This is
219 required if the U-Boot entry point is equal to the address of the
220 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
221 U-Boot booted from parallel NOR flash).
222 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
223 In that case the image size will be reduced by 0x500 bytes.
224
Paul Burton939a2552017-05-12 13:26:11 +0200225config MIPS_CM_BASE
226 hex "MIPS CM GCR Base Address"
227 depends on MIPS_CM
Paul Burtoned048e72017-04-30 21:22:41 +0200228 default 0x16100000 if TARGET_BOSTON
Paul Burton939a2552017-05-12 13:26:11 +0200229 default 0x1fbf8000
230 help
231 The physical base address at which to map the MIPS Coherence Manager
232 Global Configuration Registers (GCRs). This should be set such that
233 the GCRs occupy a region of the physical address space which is
234 otherwise unused, or at minimum that software doesn't need to access.
235
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100236endmenu
237
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100238menu "OS boot interface"
239
240config MIPS_BOOT_CMDLINE_LEGACY
241 bool "Hand over legacy command line to Linux kernel"
242 default y
243 help
244 Enable this option if you want U-Boot to hand over the Yamon-style
245 command line to the kernel. All bootargs will be prepared as argc/argv
246 compatible list. The argument count (argc) is stored in register $a0.
247 The address of the argument list (argv) is stored in register $a1.
248
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100249config MIPS_BOOT_ENV_LEGACY
250 bool "Hand over legacy environment to Linux kernel"
251 default y
252 help
253 Enable this option if you want U-Boot to hand over the Yamon-style
254 environment to the kernel. Information like memory size, initrd
255 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400256 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100257
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100258config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100259 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100260 default n
261 help
262 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100263 device tree to the kernel. According to UHI register $a0 will be set
264 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100265
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100266endmenu
267
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100268config SUPPORTS_BIG_ENDIAN
269 bool
270
271config SUPPORTS_LITTLE_ENDIAN
272 bool
273
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100274config SUPPORTS_CPU_MIPS32_R1
275 bool
276
277config SUPPORTS_CPU_MIPS32_R2
278 bool
279
Paul Burtonc52ebea2016-05-16 10:52:12 +0100280config SUPPORTS_CPU_MIPS32_R6
281 bool
282
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100283config SUPPORTS_CPU_MIPS64_R1
284 bool
285
286config SUPPORTS_CPU_MIPS64_R2
287 bool
288
Paul Burtonc52ebea2016-05-16 10:52:12 +0100289config SUPPORTS_CPU_MIPS64_R6
290 bool
291
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100292config CPU_MIPS32
293 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100294 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100295
296config CPU_MIPS64
297 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100298 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100299
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100300config MIPS_TUNE_4KC
301 bool
302
303config MIPS_TUNE_14KC
304 bool
305
306config MIPS_TUNE_24KC
307 bool
308
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200309config MIPS_TUNE_34KC
310 bool
311
Marek Vasut0a0a9582016-05-06 20:10:33 +0200312config MIPS_TUNE_74KC
313 bool
314
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100315config 32BIT
316 bool
317
318config 64BIT
319 bool
320
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100321config SWAP_IO_SPACE
322 bool
323
Paul Burtondd7c7202015-01-29 01:28:02 +0000324config SYS_MIPS_CACHE_INIT_RAM_LOAD
325 bool
326
Daniel Schwierzeck924ad862016-06-04 16:13:21 +0200327config MIPS_INIT_STACK_IN_SRAM
328 bool
329 default n
330 help
331 Select this if the initial stack frame could be setup in SRAM.
332 Normally the initial stack frame is set up in DRAM which is often
333 only available after lowlevel_init. With this option the initial
334 stack frame and the early C environment is set up before
335 lowlevel_init. Thus lowlevel_init does not need to be implemented
336 in assembler.
337
Paul Burtonace3be42016-05-27 14:28:04 +0100338config SYS_DCACHE_SIZE
339 int
340 default 0
341 help
342 The total size of the L1 Dcache, if known at compile time.
343
Paul Burton37228622016-05-27 14:28:05 +0100344config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100345 int
Paul Burton37228622016-05-27 14:28:05 +0100346 default 0
347 help
348 The size of L1 Dcache lines, if known at compile time.
349
Paul Burtonace3be42016-05-27 14:28:04 +0100350config SYS_ICACHE_SIZE
351 int
352 default 0
353 help
354 The total size of the L1 ICache, if known at compile time.
355
Paul Burton37228622016-05-27 14:28:05 +0100356config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100357 int
358 default 0
359 help
Paul Burton37228622016-05-27 14:28:05 +0100360 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100361
362config SYS_CACHE_SIZE_AUTO
363 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton37228622016-05-27 14:28:05 +0100364 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100365 help
366 Select this (or let it be auto-selected by not defining any cache
367 sizes) in order to allow U-Boot to automatically detect the sizes
368 of caches at runtime. This has a small cost in code size & runtime
369 so if you know the cache configuration for your system at compile
370 time it would be beneficial to configure it.
371
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100372config MIPS_L1_CACHE_SHIFT_4
373 bool
374
375config MIPS_L1_CACHE_SHIFT_5
376 bool
377
378config MIPS_L1_CACHE_SHIFT_6
379 bool
380
381config MIPS_L1_CACHE_SHIFT_7
382 bool
383
384config MIPS_L1_CACHE_SHIFT
385 int
386 default "7" if MIPS_L1_CACHE_SHIFT_7
387 default "6" if MIPS_L1_CACHE_SHIFT_6
388 default "5" if MIPS_L1_CACHE_SHIFT_5
389 default "4" if MIPS_L1_CACHE_SHIFT_4
390 default "5"
391
Paul Burton4baa0ab2016-09-21 11:18:54 +0100392config MIPS_L2_CACHE
393 bool
394 help
395 Select this if your system includes an L2 cache and you want U-Boot
396 to initialise & maintain it.
397
Paul Burton05e34252016-01-29 13:54:52 +0000398config DYNAMIC_IO_PORT_BASE
399 bool
400
Paul Burtonb2b135d2016-09-21 11:18:53 +0100401config MIPS_CM
402 bool
403 help
404 Select this if your system contains a MIPS Coherence Manager and you
405 wish U-Boot to configure it or make use of it to retrieve system
406 information such as cache configuration.
407
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100408endif
409
Masahiro Yamadadd840582014-07-30 14:08:14 +0900410endmenu