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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010017 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010019 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeckaa45f752014-10-26 14:14:07 +010021 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Masahiro Yamadadd840582014-07-30 14:08:14 +090023
24config TARGET_MALTA
25 bool "Support malta"
Paul Burton6242aa12016-05-17 07:43:28 +010026 select DM
27 select DM_SERIAL
Paul Burton05e34252016-01-29 13:54:52 +000028 select DYNAMIC_IO_PORT_BASE
Paul Burton6242aa12016-05-17 07:43:28 +010029 select OF_CONTROL
30 select OF_ISA_BUS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010031 select SUPPORTS_BIG_ENDIAN
32 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010033 select SUPPORTS_CPU_MIPS32_R1
34 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010035 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010036 select SUPPORTS_CPU_MIPS64_R1
37 select SUPPORTS_CPU_MIPS64_R2
38 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010039 select SWAP_IO_SPACE
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +010040 select MIPS_L1_CACHE_SHIFT_6
Masahiro Yamadadd840582014-07-30 14:08:14 +090041
42config TARGET_VCT
43 bool "Support vct"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010044 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010045 select SUPPORTS_CPU_MIPS32_R1
46 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000047 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090048
49config TARGET_DBAU1X00
50 bool "Support dbau1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010051 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010053 select SUPPORTS_CPU_MIPS32_R1
54 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000055 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010056 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090057
58config TARGET_PB1X00
59 bool "Support pb1x00"
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010060 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010061 select SUPPORTS_CPU_MIPS32_R1
62 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000063 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeck0315a282015-12-26 19:55:37 +010064 select MIPS_TUNE_4KC
Masahiro Yamadadd840582014-07-30 14:08:14 +090065
Wills Wang1d3d0f12016-03-16 16:59:52 +080066config ARCH_ATH79
67 bool "Support QCA/Atheros ath79"
68 select OF_CONTROL
69 select DM
70
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053071config MACH_PIC32
72 bool "Support Microchip PIC32"
73 select OF_CONTROL
74 select DM
75
Masahiro Yamadadd840582014-07-30 14:08:14 +090076endchoice
77
78source "board/dbau1x00/Kconfig"
79source "board/imgtec/malta/Kconfig"
80source "board/micronas/vct/Kconfig"
81source "board/pb1x00/Kconfig"
82source "board/qemu-mips/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +080083source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +053084source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +090085
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010086if MIPS
87
88choice
89 prompt "Endianness selection"
90 help
91 Some MIPS boards can be configured for either little or big endian
92 byte order. These modes require different U-Boot images. In general there
93 is one preferred byteorder for a particular system but some systems are
94 just as commonly used in the one or the other endianness.
95
96config SYS_BIG_ENDIAN
97 bool "Big endian"
98 depends on SUPPORTS_BIG_ENDIAN
99
100config SYS_LITTLE_ENDIAN
101 bool "Little endian"
102 depends on SUPPORTS_LITTLE_ENDIAN
103
104endchoice
105
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100106choice
107 prompt "CPU selection"
108 default CPU_MIPS32_R2
109
110config CPU_MIPS32_R1
111 bool "MIPS32 Release 1"
112 depends on SUPPORTS_CPU_MIPS32_R1
113 select 32BIT
114 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100115 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100116 MIPS32 architecture.
117
118config CPU_MIPS32_R2
119 bool "MIPS32 Release 2"
120 depends on SUPPORTS_CPU_MIPS32_R2
121 select 32BIT
122 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100123 Choose this option to build an U-Boot for release 2 through 5 of the
124 MIPS32 architecture.
125
126config CPU_MIPS32_R6
127 bool "MIPS32 Release 6"
128 depends on SUPPORTS_CPU_MIPS32_R6
129 select 32BIT
130 help
131 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100132 MIPS32 architecture.
133
134config CPU_MIPS64_R1
135 bool "MIPS64 Release 1"
136 depends on SUPPORTS_CPU_MIPS64_R1
137 select 64BIT
138 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100139 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100140 MIPS64 architecture.
141
142config CPU_MIPS64_R2
143 bool "MIPS64 Release 2"
144 depends on SUPPORTS_CPU_MIPS64_R2
145 select 64BIT
146 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100147 Choose this option to build a kernel for release 2 through 5 of the
148 MIPS64 architecture.
149
150config CPU_MIPS64_R6
151 bool "MIPS64 Release 6"
152 depends on SUPPORTS_CPU_MIPS64_R6
153 select 64BIT
154 help
155 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100156 MIPS64 architecture.
157
158endchoice
159
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100160menu "OS boot interface"
161
162config MIPS_BOOT_CMDLINE_LEGACY
163 bool "Hand over legacy command line to Linux kernel"
164 default y
165 help
166 Enable this option if you want U-Boot to hand over the Yamon-style
167 command line to the kernel. All bootargs will be prepared as argc/argv
168 compatible list. The argument count (argc) is stored in register $a0.
169 The address of the argument list (argv) is stored in register $a1.
170
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100171config MIPS_BOOT_ENV_LEGACY
172 bool "Hand over legacy environment to Linux kernel"
173 default y
174 help
175 Enable this option if you want U-Boot to hand over the Yamon-style
176 environment to the kernel. Information like memory size, initrd
177 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400178 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100179
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100180config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100181 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100182 default n
183 help
184 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100185 device tree to the kernel. According to UHI register $a0 will be set
186 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100187
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100188endmenu
189
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100190config SUPPORTS_BIG_ENDIAN
191 bool
192
193config SUPPORTS_LITTLE_ENDIAN
194 bool
195
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100196config SUPPORTS_CPU_MIPS32_R1
197 bool
198
199config SUPPORTS_CPU_MIPS32_R2
200 bool
201
Paul Burtonc52ebea2016-05-16 10:52:12 +0100202config SUPPORTS_CPU_MIPS32_R6
203 bool
204
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100205config SUPPORTS_CPU_MIPS64_R1
206 bool
207
208config SUPPORTS_CPU_MIPS64_R2
209 bool
210
Paul Burtonc52ebea2016-05-16 10:52:12 +0100211config SUPPORTS_CPU_MIPS64_R6
212 bool
213
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100214config CPU_MIPS32
215 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100216 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100217
218config CPU_MIPS64
219 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100220 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100221
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100222config MIPS_TUNE_4KC
223 bool
224
225config MIPS_TUNE_14KC
226 bool
227
228config MIPS_TUNE_24KC
229 bool
230
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200231config MIPS_TUNE_34KC
232 bool
233
Marek Vasut0a0a9582016-05-06 20:10:33 +0200234config MIPS_TUNE_74KC
235 bool
236
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100237config 32BIT
238 bool
239
240config 64BIT
241 bool
242
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100243config SWAP_IO_SPACE
244 bool
245
Paul Burtondd7c7202015-01-29 01:28:02 +0000246config SYS_MIPS_CACHE_INIT_RAM_LOAD
247 bool
248
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100249config MIPS_L1_CACHE_SHIFT_4
250 bool
251
252config MIPS_L1_CACHE_SHIFT_5
253 bool
254
255config MIPS_L1_CACHE_SHIFT_6
256 bool
257
258config MIPS_L1_CACHE_SHIFT_7
259 bool
260
261config MIPS_L1_CACHE_SHIFT
262 int
263 default "7" if MIPS_L1_CACHE_SHIFT_7
264 default "6" if MIPS_L1_CACHE_SHIFT_6
265 default "5" if MIPS_L1_CACHE_SHIFT_5
266 default "4" if MIPS_L1_CACHE_SHIFT_4
267 default "5"
268
Paul Burton05e34252016-01-29 13:54:52 +0000269config DYNAMIC_IO_PORT_BASE
270 bool
271
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100272endif
273
Masahiro Yamadadd840582014-07-30 14:08:14 +0900274endmenu