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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Vipin KUMAR2403f8f2010-01-15 19:15:44 +05302/*
3 * (C) Copyright 2009
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
Vipin KUMAR2403f8f2010-01-15 19:15:44 +05305 */
6
Vipin KUMAR031ed2f2012-02-26 23:13:29 +00007#ifndef __DW_I2C_H_
8#define __DW_I2C_H_
Vipin KUMAR2403f8f2010-01-15 19:15:44 +05309
Simon Glassafb88652020-01-23 11:48:06 -070010#include <clk.h>
Simon Glass23ad52e2020-01-23 11:48:25 -070011#include <i2c.h>
Simon Glass457df232019-12-06 21:41:40 -070012#include <reset.h>
Simon Glasscd93d622020-05-10 11:40:13 -060013#include <linux/bitops.h>
Simon Glass457df232019-12-06 21:41:40 -070014
Vipin KUMAR2403f8f2010-01-15 19:15:44 +053015struct i2c_regs {
Stefan Roesee2098282016-04-21 08:19:37 +020016 u32 ic_con; /* 0x00 */
17 u32 ic_tar; /* 0x04 */
18 u32 ic_sar; /* 0x08 */
19 u32 ic_hs_maddr; /* 0x0c */
20 u32 ic_cmd_data; /* 0x10 */
21 u32 ic_ss_scl_hcnt; /* 0x14 */
22 u32 ic_ss_scl_lcnt; /* 0x18 */
23 u32 ic_fs_scl_hcnt; /* 0x1c */
24 u32 ic_fs_scl_lcnt; /* 0x20 */
25 u32 ic_hs_scl_hcnt; /* 0x24 */
26 u32 ic_hs_scl_lcnt; /* 0x28 */
27 u32 ic_intr_stat; /* 0x2c */
28 u32 ic_intr_mask; /* 0x30 */
29 u32 ic_raw_intr_stat; /* 0x34 */
30 u32 ic_rx_tl; /* 0x38 */
31 u32 ic_tx_tl; /* 0x3c */
32 u32 ic_clr_intr; /* 0x40 */
33 u32 ic_clr_rx_under; /* 0x44 */
34 u32 ic_clr_rx_over; /* 0x48 */
35 u32 ic_clr_tx_over; /* 0x4c */
36 u32 ic_clr_rd_req; /* 0x50 */
37 u32 ic_clr_tx_abrt; /* 0x54 */
38 u32 ic_clr_rx_done; /* 0x58 */
39 u32 ic_clr_activity; /* 0x5c */
40 u32 ic_clr_stop_det; /* 0x60 */
41 u32 ic_clr_start_det; /* 0x64 */
42 u32 ic_clr_gen_call; /* 0x68 */
43 u32 ic_enable; /* 0x6c */
44 u32 ic_status; /* 0x70 */
45 u32 ic_txflr; /* 0x74 */
46 u32 ic_rxflr; /* 0x78 */
47 u32 ic_sda_hold; /* 0x7c */
48 u32 ic_tx_abrt_source; /* 0x80 */
Simon Glass0fd05c92020-01-23 11:48:04 -070049 u32 slv_data_nak_only;
50 u32 dma_cr;
51 u32 dma_tdlr;
52 u32 dma_rdlr;
53 u32 sda_setup;
54 u32 ack_general_call;
Stefan Roesee2098282016-04-21 08:19:37 +020055 u32 ic_enable_status; /* 0x9c */
Simon Glass0fd05c92020-01-23 11:48:04 -070056 u32 fs_spklen;
57 u32 hs_spklen;
58 u32 clr_restart_det;
59 u8 reserved[0xf4 - 0xac];
60 u32 comp_param1; /* 0xf4 */
61 u32 comp_version;
62 u32 comp_type;
Vipin KUMAR2403f8f2010-01-15 19:15:44 +053063};
64
Simon Glassdd3c1602020-01-23 11:48:09 -070065#define IC_CLK 166666666
66#define NANO_TO_KILO 1000000
Vipin KUMAR2403f8f2010-01-15 19:15:44 +053067
68/* High and low times in different speed modes (in ns) */
69#define MIN_SS_SCL_HIGHTIME 4000
Armando Viscontiea31b7a2012-12-06 00:04:18 +000070#define MIN_SS_SCL_LOWTIME 4700
71#define MIN_FS_SCL_HIGHTIME 600
72#define MIN_FS_SCL_LOWTIME 1300
Simon Glassd96440d2020-01-23 11:48:23 -070073#define MIN_FP_SCL_HIGHTIME 260
74#define MIN_FP_SCL_LOWTIME 500
Vipin KUMAR2403f8f2010-01-15 19:15:44 +053075#define MIN_HS_SCL_HIGHTIME 60
76#define MIN_HS_SCL_LOWTIME 160
77
78/* Worst case timeout for 1 byte is kept as 2ms */
79#define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
80#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
81#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
82
83/* i2c control register definitions */
84#define IC_CON_SD 0x0040
85#define IC_CON_RE 0x0020
86#define IC_CON_10BITADDRMASTER 0x0010
87#define IC_CON_10BITADDR_SLAVE 0x0008
88#define IC_CON_SPD_MSK 0x0006
89#define IC_CON_SPD_SS 0x0002
90#define IC_CON_SPD_FS 0x0004
91#define IC_CON_SPD_HS 0x0006
92#define IC_CON_MM 0x0001
93
94/* i2c target address register definitions */
95#define TAR_ADDR 0x0050
96
97/* i2c slave address register definitions */
98#define IC_SLAVE_ADDR 0x0002
99
100/* i2c data buffer and command register definitions */
101#define IC_CMD 0x0100
Armando Visconti491739b2012-12-06 00:04:16 +0000102#define IC_STOP 0x0200
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530103
104/* i2c interrupt status register definitions */
105#define IC_GEN_CALL 0x0800
106#define IC_START_DET 0x0400
107#define IC_STOP_DET 0x0200
108#define IC_ACTIVITY 0x0100
109#define IC_RX_DONE 0x0080
110#define IC_TX_ABRT 0x0040
111#define IC_RD_REQ 0x0020
112#define IC_TX_EMPTY 0x0010
113#define IC_TX_OVER 0x0008
114#define IC_RX_FULL 0x0004
Wolfgang Denk0cf207e2021-09-27 17:42:39 +0200115#define IC_RX_OVER 0x0002
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530116#define IC_RX_UNDER 0x0001
117
118/* fifo threshold register definitions */
119#define IC_TL0 0x00
120#define IC_TL1 0x01
121#define IC_TL2 0x02
122#define IC_TL3 0x03
123#define IC_TL4 0x04
124#define IC_TL5 0x05
125#define IC_TL6 0x06
126#define IC_TL7 0x07
127#define IC_RX_TL IC_TL0
128#define IC_TX_TL IC_TL0
129
130/* i2c enable register definitions */
131#define IC_ENABLE_0B 0x0001
132
133/* i2c status register definitions */
134#define IC_STATUS_SA 0x0040
135#define IC_STATUS_MA 0x0020
136#define IC_STATUS_RFF 0x0010
137#define IC_STATUS_RFNE 0x0008
138#define IC_STATUS_TFE 0x0004
139#define IC_STATUS_TFNF 0x0002
140#define IC_STATUS_ACT 0x0001
141
Jun Chen565e3282020-03-02 16:58:55 +0800142#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
143#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK (BIT(2) | BIT(3))
144
Simon Glass457df232019-12-06 21:41:40 -0700145/**
146 * struct dw_scl_sda_cfg - I2C timing configuration
147 *
Simon Glass457df232019-12-06 21:41:40 -0700148 * @ss_hcnt: Standard speed high time in ns
149 * @fs_hcnt: Fast speed high time in ns
Jun Chen27d483b2020-03-02 16:58:57 +0800150 * @hs_hcnt: High speed high time in ns
Simon Glass457df232019-12-06 21:41:40 -0700151 * @ss_lcnt: Standard speed low time in ns
152 * @fs_lcnt: Fast speed low time in ns
Jun Chen27d483b2020-03-02 16:58:57 +0800153 * @hs_lcnt: High speed low time in ns
Simon Glass457df232019-12-06 21:41:40 -0700154 * @sda_hold: SDA hold time
155 */
156struct dw_scl_sda_cfg {
Simon Glass457df232019-12-06 21:41:40 -0700157 u32 ss_hcnt;
158 u32 fs_hcnt;
Jun Chen27d483b2020-03-02 16:58:57 +0800159 u32 hs_hcnt;
Simon Glass457df232019-12-06 21:41:40 -0700160 u32 ss_lcnt;
161 u32 fs_lcnt;
Jun Chen27d483b2020-03-02 16:58:57 +0800162 u32 hs_lcnt;
Simon Glass457df232019-12-06 21:41:40 -0700163 u32 sda_hold;
164};
165
Simon Glass80a03db2020-01-23 11:48:11 -0700166/**
Simon Glassa8d2b512020-01-23 11:48:24 -0700167 * struct dw_i2c_speed_config - timings to use for a particular speed
168 *
169 * This holds calculated values to be written to the I2C controller. Each value
170 * is represented as a number of IC clock cycles.
171 *
172 * @scl_lcnt: Low count value for SCL
173 * @scl_hcnt: High count value for SCL
174 * @sda_hold: Data hold count
Simon Glass23ad52e2020-01-23 11:48:25 -0700175 * @speed_mode: Speed mode being used
Simon Glassa8d2b512020-01-23 11:48:24 -0700176 */
177struct dw_i2c_speed_config {
178 /* SCL high and low period count */
179 u16 scl_lcnt;
180 u16 scl_hcnt;
181 u32 sda_hold;
Simon Glass23ad52e2020-01-23 11:48:25 -0700182 enum i2c_speed_mode speed_mode;
Simon Glassa8d2b512020-01-23 11:48:24 -0700183};
184
185/**
Simon Glass80a03db2020-01-23 11:48:11 -0700186 * struct dw_i2c - private information for the bus
187 *
188 * @regs: Registers pointer
189 * @scl_sda_cfg: Deprecated information for x86 (should move to device tree)
190 * @resets: Resets for the I2C controller
191 * @scl_rise_time_ns: Configured SCL rise time in nanoseconds
192 * @scl_fall_time_ns: Configured SCL fall time in nanoseconds
193 * @sda_hold_time_ns: Configured SDA hold time in nanoseconds
Simon Glass96fe11c2020-01-23 11:48:15 -0700194 * @has_spk_cnt: true if the spike-count register is present
Simon Glass80a03db2020-01-23 11:48:11 -0700195 * @clk: Clock input to the I2C controller
196 */
Simon Glass457df232019-12-06 21:41:40 -0700197struct dw_i2c {
198 struct i2c_regs *regs;
199 struct dw_scl_sda_cfg *scl_sda_cfg;
200 struct reset_ctl_bulk resets;
Simon Glass80a03db2020-01-23 11:48:11 -0700201 u32 scl_rise_time_ns;
202 u32 scl_fall_time_ns;
203 u32 sda_hold_time_ns;
Simon Glass96fe11c2020-01-23 11:48:15 -0700204 bool has_spk_cnt;
Simon Glass457df232019-12-06 21:41:40 -0700205#if CONFIG_IS_ENABLED(CLK)
206 struct clk clk;
207#endif
Simon Glass4b0ec522020-07-07 21:32:29 -0600208 struct dw_i2c_speed_config config;
Simon Glass457df232019-12-06 21:41:40 -0700209};
210
211extern const struct dm_i2c_ops designware_i2c_ops;
212
213int designware_i2c_probe(struct udevice *bus);
214int designware_i2c_remove(struct udevice *dev);
Simon Glassd1998a92020-12-03 16:55:21 -0700215int designware_i2c_of_to_plat(struct udevice *bus);
Simon Glass457df232019-12-06 21:41:40 -0700216
Simon Glass4b0ec522020-07-07 21:32:29 -0600217/**
218 * dw_i2c_gen_speed_config() - Calculate config info from requested speed
219 *
220 * Calculate the speed config from the given @speed_hz and return it so that
221 * it can be incorporated in ACPI tables
222 *
223 * @dev: I2C bus to check
224 * @speed_hz: Requested speed in Hz
225 * @config: Returns config to use for that speed
226 * @return 0 if OK, -ve on error
227 */
228int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
229 struct dw_i2c_speed_config *config);
230
Vipin KUMAR031ed2f2012-02-26 23:13:29 +0000231#endif /* __DW_I2C_H_ */