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wdenk7ebf7442002-11-02 23:17:16 +00001/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk7ebf7442002-11-02 23:17:16 +00006 */
7
8#include <common.h>
9#include <command.h>
10#include <mpc106.h>
11#include <video_fb.h>
Ben Warren10efa022008-08-31 20:37:00 -070012#include <netdev.h>
wdenk7ebf7442002-11-02 23:17:16 +000013
Wolfgang Denkd87080b2006-03-31 18:32:53 +020014DECLARE_GLOBAL_DATA_PTR;
15
wdenk7ebf7442002-11-02 23:17:16 +000016/* ------------------------------------------------------------------------- */
17
18int checkboard (void)
19{
wdenk8bde7f72003-06-27 21:31:46 +000020 puts ("Board: ELTEC PowerPC\n");
21 return (0);
wdenk7ebf7442002-11-02 23:17:16 +000022}
23
24/* ------------------------------------------------------------------------- */
25
26int checkflash (void)
27{
wdenk8bde7f72003-06-27 21:31:46 +000028 /* TODO */
29 printf ("Test not implemented !\n");
30 return (0);
wdenk7ebf7442002-11-02 23:17:16 +000031}
32
33/* ------------------------------------------------------------------------- */
34
35static unsigned int mpc106_read_cfg_dword (unsigned int reg)
36{
wdenk8bde7f72003-06-27 21:31:46 +000037 unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
wdenk7ebf7442002-11-02 23:17:16 +000038
wdenk8bde7f72003-06-27 21:31:46 +000039 out32r (MPC106_REG_ADDR, reg_addr);
wdenk7ebf7442002-11-02 23:17:16 +000040
wdenk8bde7f72003-06-27 21:31:46 +000041 return (in32r (MPC106_REG_DATA | (reg & 0x3)));
wdenk7ebf7442002-11-02 23:17:16 +000042}
43
44/* ------------------------------------------------------------------------- */
45
46long int dram_size (int board_type)
47{
wdenk8bde7f72003-06-27 21:31:46 +000048 /*
49 * No actual initialisation to do - done when setting up
50 * PICRs MCCRs ME/SARs etc in asm_init.S.
51 */
wdenk7ebf7442002-11-02 23:17:16 +000052
wdenk8bde7f72003-06-27 21:31:46 +000053 register unsigned long i, msar1, mear1, memSize;
wdenk7ebf7442002-11-02 23:17:16 +000054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#if defined(CONFIG_SYS_MEMTEST)
wdenk8bde7f72003-06-27 21:31:46 +000056 register unsigned long reg;
wdenk7ebf7442002-11-02 23:17:16 +000057
wdenk8bde7f72003-06-27 21:31:46 +000058 printf ("Testing DRAM\n");
wdenk7ebf7442002-11-02 23:17:16 +000059
wdenk8bde7f72003-06-27 21:31:46 +000060 /* write each mem addr with it's address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061 for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
wdenk8bde7f72003-06-27 21:31:46 +000062 *reg = reg;
wdenk7ebf7442002-11-02 23:17:16 +000063
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
wdenk8bde7f72003-06-27 21:31:46 +000065 if (*reg != reg)
66 return -1;
67 }
wdenk7ebf7442002-11-02 23:17:16 +000068#endif
69
wdenk8bde7f72003-06-27 21:31:46 +000070 /*
71 * Since MPC107 memory controller chip has already been set to
72 * control all memory, just read and interpret its memory boundery register.
73 */
74 memSize = 0;
75 msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
76 mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
77 i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
wdenk7ebf7442002-11-02 23:17:16 +000078
wdenk8bde7f72003-06-27 21:31:46 +000079 do {
80 if (i & 0x01) /* is bank enabled ? */
81 memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
82 msar1 >>= 8;
83 mear1 >>= 8;
84 i >>= 1;
85 } while (i);
wdenk7ebf7442002-11-02 23:17:16 +000086
wdenk8bde7f72003-06-27 21:31:46 +000087 return (memSize * 0x100000);
wdenk7ebf7442002-11-02 23:17:16 +000088}
wdenk8bde7f72003-06-27 21:31:46 +000089
wdenk7ebf7442002-11-02 23:17:16 +000090/* ------------------------------------------------------------------------- */
91
Becky Bruce9973e3c2008-06-09 16:03:40 -050092phys_size_t initdram (int board_type)
wdenk7ebf7442002-11-02 23:17:16 +000093{
wdenk8bde7f72003-06-27 21:31:46 +000094 return dram_size (board_type);
wdenk7ebf7442002-11-02 23:17:16 +000095}
96
97/* ------------------------------------------------------------------------- */
98
99/*
100 * The BAB 911 can be reset by writing bit 0 of the Processor Initialization
101 * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities
102 * Memory Block).
103 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200104int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
wdenk7ebf7442002-11-02 23:17:16 +0000105{
wdenk8bde7f72003-06-27 21:31:46 +0000106 out8 (MPC107_EUMB_PI, 1);
107 return (0);
wdenk7ebf7442002-11-02 23:17:16 +0000108}
109
110/* ------------------------------------------------------------------------- */
111
112#if defined(CONFIG_WATCHDOG)
113
114/*
115 * Since the 7xx CPUs don't have an internal watchdog, this function is
116 * board specific.
117 */
wdenk8bde7f72003-06-27 21:31:46 +0000118void watchdog_reset (void)
wdenk7ebf7442002-11-02 23:17:16 +0000119{
120}
wdenk8bde7f72003-06-27 21:31:46 +0000121#endif /* CONFIG_WATCHDOG */
wdenk7ebf7442002-11-02 23:17:16 +0000122
123/* ------------------------------------------------------------------------- */
124
125void after_reloc (ulong dest_addr)
126{
wdenk8bde7f72003-06-27 21:31:46 +0000127 /*
128 * Jump to the main U-Boot board init code
129 */
wdenk27b207f2003-07-24 23:38:38 +0000130 board_init_r ((gd_t *)gd, dest_addr);
wdenk7ebf7442002-11-02 23:17:16 +0000131}
132
133/* ------------------------------------------------------------------------- */
134
135#ifdef CONFIG_CONSOLE_EXTRA_INFO
136extern GraphicDevice smi;
137
138void video_get_info_str (int line_number, char *info)
139{
wdenk8bde7f72003-06-27 21:31:46 +0000140 /* init video info strings for graphic console */
141 switch (line_number) {
142 case 1:
143 sprintf (info, " MPC7xx V%d.%d at %d / %d MHz",
144 (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100);
145 return;
146 case 2:
147 sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH",
148 dram_size (0) / 0x100000, flash_init () / 0x100000);
149 return;
150 case 3:
151 sprintf (info, " %s", smi.modeIdent);
152 return;
153 }
wdenk7ebf7442002-11-02 23:17:16 +0000154
wdenk8bde7f72003-06-27 21:31:46 +0000155 /* no more info lines */
156 *info = 0;
157 return;
wdenk7ebf7442002-11-02 23:17:16 +0000158}
159#endif
Ben Warren10efa022008-08-31 20:37:00 -0700160
161int board_eth_init(bd_t *bis)
162{
163 return pci_eth_init(bis);
164}