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wdenk3bac3512003-03-12 10:41:04 +00001/*
2**=====================================================================
3**
4** Copyright (C) 2000, 2001, 2002, 2003
5** The LEOX team <team@leox.org>, http://www.leox.org
6**
7** LEOX.org is about the development of free hardware and software resources
8** for system on chip.
9**
10** Description: U-Boot port on the LEOX's ELPT860 CPU board
11** ~~~~~~~~~~~
12**
13**=====================================================================
14**
15** This program is free software; you can redistribute it and/or
16** modify it under the terms of the GNU General Public License as
17** published by the Free Software Foundation; either version 2 of
18** the License, or (at your option) any later version.
19**
20** This program is distributed in the hope that it will be useful,
21** but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc837dcb2004-01-20 23:12:12 +000022** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk3bac3512003-03-12 10:41:04 +000023** GNU General Public License for more details.
24**
25** You should have received a copy of the GNU General Public License
26** along with this program; if not, write to the Free Software
27** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28** MA 02111-1307 USA
29**
30**=====================================================================
31*/
32
33/*
34 * board/config.h - configuration options, board specific
35 */
36
37#ifndef __CONFIG_H
38#define __CONFIG_H
39
40
41/*
42 * High Level Configuration Options
43 * (easy to change)
44 */
45
46#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */
47#define CONFIG_MPC860T 1
48#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
49
wdenkc837dcb2004-01-20 23:12:12 +000050#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenk3bac3512003-03-12 10:41:04 +000051#undef CONFIG_8xx_CONS_SMC2
52#undef CONFIG_8xx_CONS_NONE
53
wdenkc837dcb2004-01-20 23:12:12 +000054#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
55#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
wdenk3bac3512003-03-12 10:41:04 +000056
57#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
58
wdenkc837dcb2004-01-20 23:12:12 +000059#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk3bac3512003-03-12 10:41:04 +000060
61/* BOOT arguments */
wdenkc837dcb2004-01-20 23:12:12 +000062#define CONFIG_PREBOOT \
63 "echo;" \
64 "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
wdenk3bac3512003-03-12 10:41:04 +000065 "echo"
66
wdenk8bde7f72003-06-27 21:31:46 +000067#undef CONFIG_BOOTARGS
wdenk3bac3512003-03-12 10:41:04 +000068
wdenkc837dcb2004-01-20 23:12:12 +000069#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk3bac3512003-03-12 10:41:04 +000070 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "rootargs=setenv rootpath /tftp/${ipaddr}\0" \
wdenk3bac3512003-03-12 10:41:04 +000072 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073 "nfsroot=${serverip}:${rootpath}\0" \
74 "addip=setenv bootargs ${bootargs} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
76 ":${hostname}:eth0:off panic=1\0" \
wdenk3bac3512003-03-12 10:41:04 +000077 "ramboot=tftp 400000 /home/paugaml/pMulti;" \
wdenk8bde7f72003-06-27 21:31:46 +000078 "run ramargs;bootm\0" \
wdenk3bac3512003-03-12 10:41:04 +000079 "nfsboot=tftp 400000 /home/paugaml/uImage;" \
wdenk8bde7f72003-06-27 21:31:46 +000080 "run rootargs;run nfsargs;run addip;bootm\0" \
wdenk3bac3512003-03-12 10:41:04 +000081 ""
82#define CONFIG_BOOTCOMMAND "run ramboot"
83
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050084/*
85 * BOOTP options
86 */
87#define CONFIG_BOOTP_SUBNETMASK
88#define CONFIG_BOOTP_GATEWAY
89#define CONFIG_BOOTP_HOSTNAME
90#define CONFIG_BOOTP_BOOTPATH
91#define CONFIG_BOOTP_BOOTFILESIZE
92
wdenk3bac3512003-03-12 10:41:04 +000093
94#undef CONFIG_WATCHDOG /* watchdog disabled */
95#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
96#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
wdenkc837dcb2004-01-20 23:12:12 +000097#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
wdenk3bac3512003-03-12 10:41:04 +000098
99#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
100#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
101
wdenk3bac3512003-03-12 10:41:04 +0000102
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500103/*
104 * Command line configuration.
105 */
106#include <config_cmd_default.h>
107
108#define CONFIG_CMD_ASKENV
109#define CONFIG_CMD_DATE
110
wdenk3bac3512003-03-12 10:41:04 +0000111
112/*
113 * Miscellaneous configurable options
114 */
wdenkc837dcb2004-01-20 23:12:12 +0000115#define CFG_LONGHELP /* undef to save memory */
116#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
wdenk3bac3512003-03-12 10:41:04 +0000117
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500118#if defined(CONFIG_CMD_KGDB)
wdenk3bac3512003-03-12 10:41:04 +0000119# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
120#else
121# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
122#endif
123
wdenkc837dcb2004-01-20 23:12:12 +0000124#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
125#define CFG_MAXARGS 16 /* max number of command args */
wdenk3bac3512003-03-12 10:41:04 +0000126#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
127
128#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
129#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
130
wdenkc837dcb2004-01-20 23:12:12 +0000131#define CFG_LOAD_ADDR 0x00100000 /* default load address */
wdenk3bac3512003-03-12 10:41:04 +0000132
wdenkc837dcb2004-01-20 23:12:12 +0000133#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk3bac3512003-03-12 10:41:04 +0000134
135/*
136 * Environment Variables and Storages
137 */
wdenkc837dcb2004-01-20 23:12:12 +0000138#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
wdenk3bac3512003-03-12 10:41:04 +0000139
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200140#undef CONFIG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200141#undef CONFIG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200142#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
wdenk3bac3512003-03-12 10:41:04 +0000143
wdenkc837dcb2004-01-20 23:12:12 +0000144#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
wdenk3bac3512003-03-12 10:41:04 +0000145#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
146
wdenkc837dcb2004-01-20 23:12:12 +0000147#define CONFIG_ETHADDR 00:01:77:00:60:40
148#define CONFIG_IPADDR 192.168.0.30
149#define CONFIG_NETMASK 255.255.255.0
wdenk3bac3512003-03-12 10:41:04 +0000150
wdenkc837dcb2004-01-20 23:12:12 +0000151#define CONFIG_SERVERIP 192.168.0.1
152#define CONFIG_GATEWAYIP 192.168.0.1
wdenk3bac3512003-03-12 10:41:04 +0000153
154/*
155 * Low Level Configuration Settings
156 * (address mappings, register initial values, etc.)
157 * You should know what you are doing if you make changes here.
158 */
159
160/*-----------------------------------------------------------------------
161 * Internal Memory Mapped Register
162 */
163#define CFG_IMMR 0xFF000000
164
165/*-----------------------------------------------------------------------
166 * Definitions for initial stack pointer and data area (in DPRAM)
167 */
168#define CFG_INIT_RAM_ADDR CFG_IMMR
wdenkc837dcb2004-01-20 23:12:12 +0000169#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
170#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
wdenk3bac3512003-03-12 10:41:04 +0000171#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000172#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenk3bac3512003-03-12 10:41:04 +0000173
174/*-----------------------------------------------------------------------
175 * Start addresses for the final memory configuration
176 * (Set up by the startup code)
177 * Please note that CFG_SDRAM_BASE _must_ start at 0
178 */
wdenkc837dcb2004-01-20 23:12:12 +0000179#define CFG_SDRAM_BASE 0x00000000
wdenk3bac3512003-03-12 10:41:04 +0000180#define CFG_FLASH_BASE 0x02000000
wdenkc837dcb2004-01-20 23:12:12 +0000181#define CFG_NVRAM_BASE 0x03000000
wdenk3bac3512003-03-12 10:41:04 +0000182
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200183#if defined(CONFIG_ENV_IS_IN_FLASH)
wdenk3bac3512003-03-12 10:41:04 +0000184# if defined(DEBUG)
185# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */
186# else
187# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
188# endif
189#else
190# if defined(DEBUG)
191# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
192# else
193# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
194# endif
195#endif
196
197#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenkc837dcb2004-01-20 23:12:12 +0000198#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk3bac3512003-03-12 10:41:04 +0000199
200/*
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization.
204 */
wdenkc837dcb2004-01-20 23:12:12 +0000205#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk3bac3512003-03-12 10:41:04 +0000206
207/*-----------------------------------------------------------------------
208 * FLASH organization
209 */
wdenkc837dcb2004-01-20 23:12:12 +0000210#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk3bac3512003-03-12 10:41:04 +0000211#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
212
213#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
214#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
215
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200216#if defined(CONFIG_ENV_IS_IN_FLASH)
wdenkc837dcb2004-01-20 23:12:12 +0000217# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
218# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
wdenk3bac3512003-03-12 10:41:04 +0000219#endif
220
221/*-----------------------------------------------------------------------
222 * NVRAM organization
223 */
wdenkc837dcb2004-01-20 23:12:12 +0000224#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
225#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
wdenk8bde7f72003-06-27 21:31:46 +0000226 /* 8 top NVRAM locations */
wdenk3bac3512003-03-12 10:41:04 +0000227
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200228#if defined(CONFIG_ENV_IS_IN_NVRAM)
wdenkc837dcb2004-01-20 23:12:12 +0000229# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
230# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk3bac3512003-03-12 10:41:04 +0000231#endif
232
233/*-----------------------------------------------------------------------
234 * Cache Configuration
235 */
wdenkc837dcb2004-01-20 23:12:12 +0000236#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
wdenk3bac3512003-03-12 10:41:04 +0000237
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500238#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000239# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk3bac3512003-03-12 10:41:04 +0000240#endif
241
242/*-----------------------------------------------------------------------
243 * SYPCR - System Protection Control 11-9
244 * SYPCR can only be written once after reset!
245 *-----------------------------------------------------------------------
246 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
247 */
248#if defined(CONFIG_WATCHDOG)
wdenkc837dcb2004-01-20 23:12:12 +0000249# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000250 SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
wdenk3bac3512003-03-12 10:41:04 +0000251#else
wdenkc837dcb2004-01-20 23:12:12 +0000252# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000253 SYPCR_SWP)
wdenk3bac3512003-03-12 10:41:04 +0000254#endif
255
256/*-----------------------------------------------------------------------
257 * SUMCR - SIU Module Configuration 11-6
258 *-----------------------------------------------------------------------
259 * PCMCIA config., multi-function pin tri-state
260 */
261#define CFG_SIUMCR (SIUMCR_DBGC11)
262
263/*-----------------------------------------------------------------------
264 * TBSCR - Time Base Status and Control 11-26
265 *-----------------------------------------------------------------------
266 * Clear Reference Interrupt Status, Timebase freezing enabled
267 */
268#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
269
270/*-----------------------------------------------------------------------
271 * RTCSC - Real-Time Clock Status and Control Register 11-27
272 *-----------------------------------------------------------------------
273 * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
274 * enabled
275 */
276#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
277
278/*-----------------------------------------------------------------------
279 * PISCR - Periodic Interrupt Status and Control 11-31
280 *-----------------------------------------------------------------------
281 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
282 */
283#define CFG_PISCR (PISCR_PS | PISCR_PITF)
284
285/*-----------------------------------------------------------------------
286 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
287 *-----------------------------------------------------------------------
288 * Reset PLL lock status sticky bit, timer expired status bit and timer
289 * interrupt status bit - leave PLL multiplication factor unchanged !
290 */
291#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
292
293/*-----------------------------------------------------------------------
294 * SCCR - System Clock and reset Control Register 15-27
295 *-----------------------------------------------------------------------
296 * Set clock output, timebase and RTC source and divider,
297 * power management and some other internal clocks
298 */
299#define SCCR_MASK SCCR_EBDF11
300#define CFG_SCCR (SCCR_TBS | \
301 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
302 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
303 SCCR_DFALCD00)
304
305/*-----------------------------------------------------------------------
306 * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
307 *-----------------------------------------------------------------------
308 *
309 */
310#ifdef DEBUG
311# define CFG_DER 0xFFE7400F /* Debug Enable Register */
312#else
313# define CFG_DER 0
314#endif
315
316/*
317 * Init Memory Controller:
318 * ~~~~~~~~~~~~~~~~~~~~~~
319 *
320 * BR0 and OR0 (FLASH)
321 */
322
wdenkc837dcb2004-01-20 23:12:12 +0000323#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
wdenk3bac3512003-03-12 10:41:04 +0000324
325/* used to re-map FLASH both when starting from SRAM or FLASH:
326 * restrict access enough to keep SRAM working (if any)
327 * but not too much to meddle with FLASH accesses
328 */
329#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */
330
331/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */
332#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
333
334#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
335#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
336
337/*
338 * BR1 and OR1 (SDRAM)
339 *
340 */
wdenkc837dcb2004-01-20 23:12:12 +0000341#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */
342#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
wdenk3bac3512003-03-12 10:41:04 +0000343
wdenkc837dcb2004-01-20 23:12:12 +0000344/* SDRAM timing: */
wdenk3bac3512003-03-12 10:41:04 +0000345#define CFG_OR_TIMING_SDRAM 0x00000000
346
347#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
348#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
349
350/*
351 * BR2 and OR2 (NVRAM)
352 *
353 */
wdenkc837dcb2004-01-20 23:12:12 +0000354#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */
355#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
wdenk3bac3512003-03-12 10:41:04 +0000356
wdenkc837dcb2004-01-20 23:12:12 +0000357#define CFG_OR2_PRELIM 0xFFF80160
wdenk3bac3512003-03-12 10:41:04 +0000358#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
359
360/*
361 * Memory Periodic Timer Prescaler
362 */
363
364/* periodic timer for refresh */
wdenkc837dcb2004-01-20 23:12:12 +0000365#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk3bac3512003-03-12 10:41:04 +0000366
367/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
368#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
wdenkc837dcb2004-01-20 23:12:12 +0000369#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk3bac3512003-03-12 10:41:04 +0000370
wdenkc837dcb2004-01-20 23:12:12 +0000371/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
372#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
373#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk3bac3512003-03-12 10:41:04 +0000374
375/*
376 * MAMR settings for SDRAM
377 */
378
379/* 8 column SDRAM */
380#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
381 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
382 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
383/* 9 column SDRAM */
384#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
385 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
386 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
387
388/*-----------------------------------------------------------------------
389 * Internal Definitions
390 *-----------------------------------------------------------------------
391 *
392 */
393
394/*
395 * Boot Flags
396 */
wdenkc837dcb2004-01-20 23:12:12 +0000397#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
398#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenk3bac3512003-03-12 10:41:04 +0000399
400
401#endif /* __CONFIG_H */