* The PS/2 mux on the BMS2003 board needs 450 ms after power on
before we can access it; add delay in case we are faster (with no
CF card inserted)
* Cleanup of some init functions
* Make sure SCC Ethernet is always stopped by the time we boot Linux
to avoid Linux crashes by early packets coming in.
* Accelerate flash accesses on LWMON board by using buffered writes
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index 2f253b9..5bfdc9b 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -19,7 +19,7 @@
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
-** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
@@ -47,26 +47,26 @@
#define CONFIG_MPC860T 1
#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
-#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
+#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
+#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* BOOT arguments */
-#define CONFIG_PREBOOT \
- "echo;" \
- "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
+#define CONFIG_PREBOOT \
+ "echo;" \
+ "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"rootargs=setenv rootpath /tftp/$(ipaddr)\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -86,14 +86,14 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
-#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
+#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
- CFG_CMD_DATE )
+ CFG_CMD_DATE )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -101,8 +101,8 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
@@ -110,35 +110,35 @@
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Environment Variables and Storages
*/
-#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
+#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
-#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
-#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
-#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
+#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
+#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
+#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
+#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_ETHADDR 00:01:77:00:60:40
-#define CONFIG_IPADDR 192.168.0.30
-#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_ETHADDR 00:01:77:00:60:40
+#define CONFIG_IPADDR 192.168.0.30
+#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.0.1
-#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.1
+#define CONFIG_GATEWAYIP 192.168.0.1
/*
* Low Level Configuration Settings
@@ -155,19 +155,19 @@
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x02000000
-#define CFG_NVRAM_BASE 0x03000000
+#define CFG_NVRAM_BASE 0x03000000
#if defined(CFG_ENV_IS_IN_FLASH)
# if defined(DEBUG)
@@ -184,48 +184,48 @@
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#if defined(CFG_ENV_IS_IN_FLASH)
-# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
-# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
+# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* NVRAM organization
*/
-#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
-#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
+#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
+#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
/* 8 top NVRAM locations */
#if defined(CFG_ENV_IS_IN_NVRAM)
-# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
-# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
+# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
@@ -235,10 +235,10 @@
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
-# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
#else
-# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWP)
#endif
@@ -309,7 +309,7 @@
* BR0 and OR0 (FLASH)
*/
-#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
@@ -327,10 +327,10 @@
* BR1 and OR1 (SDRAM)
*
*/
-#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
+#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
-/* SDRAM timing: */
+/* SDRAM timing: */
#define CFG_OR_TIMING_SDRAM 0x00000000
#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
@@ -340,10 +340,10 @@
* BR2 and OR2 (NVRAM)
*
*/
-#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */
-#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
+#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */
+#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
-#define CFG_OR2_PRELIM 0xFFF80160
+#define CFG_OR2_PRELIM 0xFFF80160
#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
/*
@@ -351,15 +351,15 @@
*/
/* periodic timer for refresh */
-#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
+#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
@@ -383,8 +383,8 @@
/*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */