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wdenkc15f3122004-10-10 22:44:24 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8540 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
Paul Gortmaker928435d2009-09-21 17:19:17 -040027/*
28 * sbc8540 board configuration file.
wdenkc15f3122004-10-10 22:44:24 +000029 */
wdenk8b74bf32004-10-11 23:10:30 +000030
wdenkc15f3122004-10-10 22:44:24 +000031#ifndef __CONFIG_H
32#define __CONFIG_H
33
Paul Gortmaker928435d2009-09-21 17:19:17 -040034/*
35 * Top level Makefile configuration choices
36 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020037#ifdef CONFIG_66
Paul Gortmaker928435d2009-09-21 17:19:17 -040038#define CONFIG_PCI_66
wdenkc15f3122004-10-10 22:44:24 +000039#endif
Paul Gortmaker928435d2009-09-21 17:19:17 -040040
wdenkc15f3122004-10-10 22:44:24 +000041#define TSEC_DEBUG
42
Paul Gortmaker928435d2009-09-21 17:19:17 -040043/*
44 * High Level Configuration Options
45 */
wdenkc15f3122004-10-10 22:44:24 +000046#define CONFIG_BOOKE 1 /* BOOKE */
47#define CONFIG_E500 1 /* BOOKE e500 family */
48#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
49#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
50
Wolfgang Denk2ae18242010-10-06 09:05:45 +020051#define CONFIG_SYS_TEXT_BASE 0xfffc0000
52
wdenkc15f3122004-10-10 22:44:24 +000053
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050054#define CONFIG_CPM2 1 /* has CPM2 */
wdenkc15f3122004-10-10 22:44:24 +000055
Wolfgang Denk53677ef2008-05-20 16:00:29 +020056#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
Kumar Galaf0600542008-06-11 00:44:10 -050057#define CONFIG_MPC8540 1
wdenkc15f3122004-10-10 22:44:24 +000058
59#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
60
61#define CONFIG_TSEC_ENET /* tsec ethernet support */
62#undef CONFIG_PCI /* pci ethernet support */
63#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
64
Kumar Galae2b159d2008-01-16 09:05:27 -060065#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenkc15f3122004-10-10 22:44:24 +000066
67#define CONFIG_ENV_OVERWRITE
68
69/* Using Localbus SDRAM to emulate flash before we can program the flash,
70 * normally you need a flash-boot image(u-boot.bin), if so undef this.
71 */
72#undef CONFIG_RAM_AS_FLASH
73
74#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
75 #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
76#else
77 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
78#endif
79
80/* below can be toggled for performance analysis. otherwise use default */
81#define CONFIG_L2_CACHE /* toggle L2 cache */
82#undef CONFIG_BTB /* toggle branch predition */
wdenkc15f3122004-10-10 22:44:24 +000083
84#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050085#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenkc15f3122004-10-10 22:44:24 +000086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
88#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
89#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenkc15f3122004-10-10 22:44:24 +000090
91#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
92 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
93 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
94#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
95#endif
96
97/*
98 * Base addresses -- Note these are effective addresses where the
99 * actual resources get mapped (not physical addresses)
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
wdenkc15f3122004-10-10 22:44:24 +0000102
103#if XXX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
wdenkc15f3122004-10-10 22:44:24 +0000105#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
wdenkc15f3122004-10-10 22:44:24 +0000107#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
109#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenkc15f3122004-10-10 22:44:24 +0000110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
wdenkc15f3122004-10-10 22:44:24 +0000112
Kumar Gala8e553132008-08-26 23:52:58 -0500113/* DDR Setup */
114#define CONFIG_FSL_DDR1
115#undef CONFIG_FSL_DDR_INTERACTIVE
wdenkc15f3122004-10-10 22:44:24 +0000116#undef CONFIG_DDR_ECC /* only for ECC DDR module */
117#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
Kumar Gala8e553132008-08-26 23:52:58 -0500118#undef CONFIG_DDR_SPD
wdenkc15f3122004-10-10 22:44:24 +0000119
120#if defined(CONFIG_MPC85xx_REV1)
121 #define CONFIG_DDR_DLL /* possible DLL fix needed */
122#endif
123
Kumar Gala8e553132008-08-26 23:52:58 -0500124#undef CONFIG_DDR_ECC /* only for ECC DDR module */
125#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
126#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
129#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala8e553132008-08-26 23:52:58 -0500130#define CONFIG_VERY_BIG_RAM
131
132#define CONFIG_NUM_DDR_CONTROLLERS 1
133#define CONFIG_DIMM_SLOTS_PER_CTLR 1
134#define CONFIG_CHIP_SELECTS_PER_CTRL 2
135
136/* I2C addresses of SPD EEPROMs */
137#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
138
wdenkc15f3122004-10-10 22:44:24 +0000139#undef CONFIG_CLOCKS_IN_MHZ
140
141#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
143 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
144 #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
145 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
wdenkc15f3122004-10-10 22:44:24 +0000146#else /* Boot from real Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
148 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
149 #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
150 #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
wdenkc15f3122004-10-10 22:44:24 +0000151#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenkc15f3122004-10-10 22:44:24 +0000153
154/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
156#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
wdenkc15f3122004-10-10 22:44:24 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
159#define CONFIG_SYS_OR2_PRELIM 0x00000000
wdenkc15f3122004-10-10 22:44:24 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
162#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
wdenkc15f3122004-10-10 22:44:24 +0000163
164#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
wdenkc15f3122004-10-10 22:44:24 +0000166#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167 #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
wdenkc15f3122004-10-10 22:44:24 +0000168#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
wdenkc15f3122004-10-10 22:44:24 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
wdenkc15f3122004-10-10 22:44:24 +0000172#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
wdenkc15f3122004-10-10 22:44:24 +0000174#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
wdenkc15f3122004-10-10 22:44:24 +0000176#endif
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
179#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
180#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
181#define CONFIG_SYS_LBC_LBCR 0x00000000
182#define CONFIG_SYS_LBC_LSRT 0x20000000
183#define CONFIG_SYS_LBC_MRTPR 0x20000000
184#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
185#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
186#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
187#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
188#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenkc15f3122004-10-10 22:44:24 +0000189
190/* just hijack the MOT BCSR def for SBC8560 misc devices */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
wdenkc15f3122004-10-10 22:44:24 +0000192/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_INIT_RAM_LOCK 1
195#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
196#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenkc15f3122004-10-10 22:44:24 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc15f3122004-10-10 22:44:24 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
203#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenkc15f3122004-10-10 22:44:24 +0000204
205/* Serial Port */
206#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
207#undef CONFIG_CONS_NONE /* define if console on something else */
208
209#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_NS16550
211#define CONFIG_SYS_NS16550_SERIAL
212#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkc15f3122004-10-10 22:44:24 +0000213#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
wdenkc15f3122004-10-10 22:44:24 +0000215#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */
wdenkc15f3122004-10-10 22:44:24 +0000217#endif
218
219#define CONFIG_BAUDRATE 9600
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc15f3122004-10-10 22:44:24 +0000222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
223
224#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
226#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
wdenkc15f3122004-10-10 22:44:24 +0000227#else
wdenk8b74bf32004-10-11 23:10:30 +0000228/* SBC8540 uses internal COMM controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
230#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
wdenkc15f3122004-10-10 22:44:24 +0000231#endif
232
233/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_HUSH_PARSER
235#ifdef CONFIG_SYS_HUSH_PARSER
236#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc15f3122004-10-10 22:44:24 +0000237#endif
238
Jon Loeliger20476722006-10-20 15:50:15 -0500239/*
240 * I2C
241 */
242#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
243#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenkc15f3122004-10-10 22:44:24 +0000244#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
246#define CONFIG_SYS_I2C_SLAVE 0x7F
247#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
248#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenkc15f3122004-10-10 22:44:24 +0000249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
251#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
252#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
wdenkc15f3122004-10-10 22:44:24 +0000253
254#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
255
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500256# define CONFIG_NET_MULTI 1
257# define CONFIG_MPC85xx_TSEC1
258# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
259# define CONFIG_MII 1 /* MII PHY management */
260# define TSEC1_PHY_ADDR 25
261# define TSEC1_PHYIDX 0
262/* Options are: TSEC0 */
263# define CONFIG_ETHPRIME "TSEC0"
wdenkc15f3122004-10-10 22:44:24 +0000264
wdenk8b74bf32004-10-11 23:10:30 +0000265
wdenkc15f3122004-10-10 22:44:24 +0000266#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
267
268 #undef CONFIG_ETHER_NONE /* define if ether on something else */
269 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
270 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk8b74bf32004-10-11 23:10:30 +0000271
wdenkc15f3122004-10-10 22:44:24 +0000272 #if (CONFIG_ETHER_INDEX == 2)
273 /*
274 * - Rx-CLK is CLK13
275 * - Tx-CLK is CLK14
276 * - Select bus for bd/buffers
277 * - Full duplex
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
280 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
281 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
282 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk8b74bf32004-10-11 23:10:30 +0000283
wdenkc15f3122004-10-10 22:44:24 +0000284 #elif (CONFIG_ETHER_INDEX == 3)
285 /* need more definitions here for FE3 */
286 #endif /* CONFIG_ETHER_INDEX */
wdenk8b74bf32004-10-11 23:10:30 +0000287
wdenkc15f3122004-10-10 22:44:24 +0000288 #define CONFIG_MII /* MII PHY management */
289 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
290 /*
291 * GPIO pins used for bit-banged MII communications
292 */
293 #define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200294 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
295 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
296 #define MDC_DECLARE MDIO_DECLARE
297
wdenkc15f3122004-10-10 22:44:24 +0000298 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
299 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
300 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
301
302 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
303 else iop->pdat &= ~0x00400000
304
305 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
306 else iop->pdat &= ~0x00200000
307
308 #define MIIDELAY udelay(1)
wdenk8b74bf32004-10-11 23:10:30 +0000309
wdenkc15f3122004-10-10 22:44:24 +0000310#endif
311
312/*-----------------------------------------------------------------------
313 * FLASH and environment organization
314 */
315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200317#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenkc15f3122004-10-10 22:44:24 +0000318#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
320#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
wdenkc15f3122004-10-10 22:44:24 +0000321#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
323#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenkc15f3122004-10-10 22:44:24 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#undef CONFIG_SYS_FLASH_CHECKSUM
326#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
327#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
wdenkc15f3122004-10-10 22:44:24 +0000328
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200329#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenkc15f3122004-10-10 22:44:24 +0000330
331#if 0
332/* XXX This doesn't work and I don't want to fix it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
334 #define CONFIG_SYS_RAMBOOT
wdenkc15f3122004-10-10 22:44:24 +0000335#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336 #undef CONFIG_SYS_RAMBOOT
wdenkc15f3122004-10-10 22:44:24 +0000337#endif
338#endif
339
340/* Environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#if !defined(CONFIG_SYS_RAMBOOT)
wdenkc15f3122004-10-10 22:44:24 +0000342 #if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200343 #define CONFIG_ENV_IS_NOWHERE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200345 #define CONFIG_ENV_SIZE 0x2000
wdenkc15f3122004-10-10 22:44:24 +0000346 #else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200347 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200348 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200350 #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
wdenkc15f3122004-10-10 22:44:24 +0000351 #endif
352#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200354 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200356 #define CONFIG_ENV_SIZE 0x2000
wdenkc15f3122004-10-10 22:44:24 +0000357#endif
358
359#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
360/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
361#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
362#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
363
364#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc15f3122004-10-10 22:44:24 +0000366
Jon Loeliger2835e512007-06-13 13:22:08 -0500367
368/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500369 * BOOTP options
370 */
371#define CONFIG_BOOTP_BOOTFILESIZE
372#define CONFIG_BOOTP_BOOTPATH
373#define CONFIG_BOOTP_GATEWAY
374#define CONFIG_BOOTP_HOSTNAME
375
376
377/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500378 * Command line configuration.
379 */
380#include <config_cmd_default.h>
381
382#define CONFIG_CMD_PING
383#define CONFIG_CMD_I2C
Becky Bruce199e2622010-06-17 11:37:25 -0500384#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500385
386#if defined(CONFIG_PCI)
387 #define CONFIG_CMD_PCI
wdenkc15f3122004-10-10 22:44:24 +0000388#endif
389
Jon Loeliger2835e512007-06-13 13:22:08 -0500390#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
391 #define CONFIG_CMD_MII
392#endif
393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500395 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500396 #undef CONFIG_CMD_LOADS
397#endif
398
wdenkc15f3122004-10-10 22:44:24 +0000399
400#undef CONFIG_WATCHDOG /* watchdog disabled */
401
402/*
403 * Miscellaneous configurable options
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_LONGHELP /* undef to save memory */
406#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500407#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc15f3122004-10-10 22:44:24 +0000409#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc15f3122004-10-10 22:44:24 +0000411#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
413#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
414#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
415#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
416#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc15f3122004-10-10 22:44:24 +0000417
418/*
419 * For booting Linux, the board info and command line data
420 * have to be in the first 8 MB of memory, since this is
421 * the maximum mapped by the Linux kernel during initialization.
422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc15f3122004-10-10 22:44:24 +0000424
Jon Loeliger2835e512007-06-13 13:22:08 -0500425#if defined(CONFIG_CMD_KGDB)
wdenkc15f3122004-10-10 22:44:24 +0000426 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
427 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
428#endif
429
430/*Note: change below for your network setting!!! */
431#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000432# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
433# define CONFIG_HAS_ETH1
434# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
435# define CONFIG_HAS_ETH2
436# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
wdenkc15f3122004-10-10 22:44:24 +0000437#endif
438
439#define CONFIG_SERVERIP YourServerIP
440#define CONFIG_IPADDR YourTargetIP
441#define CONFIG_GATEWAYIP YourGatewayIP
442#define CONFIG_NETMASK 255.255.255.0
443#define CONFIG_HOSTNAME SBC8560
444#define CONFIG_ROOTPATH YourRootPath
445#define CONFIG_BOOTFILE YourImageName
446
447#endif /* __CONFIG_H */