wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002,2003 Motorola,Inc. |
| 3 | * Xianghua Xiao <X.Xiao@motorola.com> |
| 4 | * |
| 5 | * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. |
| 6 | * Added support for Wind River SBC8540 board |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
Paul Gortmaker | 928435d | 2009-09-21 17:19:17 -0400 | [diff] [blame] | 27 | /* |
| 28 | * sbc8540 board configuration file. |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 29 | */ |
wdenk | 8b74bf3 | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 30 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 31 | #ifndef __CONFIG_H |
| 32 | #define __CONFIG_H |
| 33 | |
Paul Gortmaker | 928435d | 2009-09-21 17:19:17 -0400 | [diff] [blame] | 34 | /* |
| 35 | * Top level Makefile configuration choices |
| 36 | */ |
| 37 | #ifdef CONFIG_MK_66 |
| 38 | #define CONFIG_PCI_66 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 39 | #endif |
Paul Gortmaker | 928435d | 2009-09-21 17:19:17 -0400 | [diff] [blame] | 40 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 41 | #define TSEC_DEBUG |
| 42 | |
Paul Gortmaker | 928435d | 2009-09-21 17:19:17 -0400 | [diff] [blame] | 43 | /* |
| 44 | * High Level Configuration Options |
| 45 | */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 46 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 47 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 48 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
| 49 | #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ |
| 50 | |
| 51 | |
Jon Loeliger | 9c4c5ae | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 52 | #define CONFIG_CPM2 1 /* has CPM2 */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 53 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 54 | #define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ |
Kumar Gala | f060054 | 2008-06-11 00:44:10 -0500 | [diff] [blame] | 55 | #define CONFIG_MPC8540 1 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 56 | |
| 57 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ |
| 58 | |
| 59 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 60 | #undef CONFIG_PCI /* pci ethernet support */ |
| 61 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
| 62 | |
Kumar Gala | e2b159d | 2008-01-16 09:05:27 -0600 | [diff] [blame] | 63 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 64 | |
| 65 | #define CONFIG_ENV_OVERWRITE |
| 66 | |
| 67 | /* Using Localbus SDRAM to emulate flash before we can program the flash, |
| 68 | * normally you need a flash-boot image(u-boot.bin), if so undef this. |
| 69 | */ |
| 70 | #undef CONFIG_RAM_AS_FLASH |
| 71 | |
| 72 | #if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ |
| 73 | #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ |
| 74 | #else |
| 75 | #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ |
| 76 | #endif |
| 77 | |
| 78 | /* below can be toggled for performance analysis. otherwise use default */ |
| 79 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 80 | #undef CONFIG_BTB /* toggle branch predition */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 81 | |
| 82 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
Peter Tyser | 004eca0 | 2009-09-16 22:03:08 -0500 | [diff] [blame] | 83 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 84 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 86 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 87 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 88 | |
| 89 | #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ |
| 90 | defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ |
| 91 | defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) |
| 92 | #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." |
| 93 | #endif |
| 94 | |
| 95 | /* |
| 96 | * Base addresses -- Note these are effective addresses where the |
| 97 | * actual resources get mapped (not physical addresses) |
| 98 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 100 | |
| 101 | #if XXX |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 103 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 104 | #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 105 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
| 107 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 108 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 110 | |
Kumar Gala | 8e55313 | 2008-08-26 23:52:58 -0500 | [diff] [blame] | 111 | /* DDR Setup */ |
| 112 | #define CONFIG_FSL_DDR1 |
| 113 | #undef CONFIG_FSL_DDR_INTERACTIVE |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 114 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 115 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
Kumar Gala | 8e55313 | 2008-08-26 23:52:58 -0500 | [diff] [blame] | 116 | #undef CONFIG_DDR_SPD |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 117 | |
| 118 | #if defined(CONFIG_MPC85xx_REV1) |
| 119 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
| 120 | #endif |
| 121 | |
Kumar Gala | 8e55313 | 2008-08-26 23:52:58 -0500 | [diff] [blame] | 122 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 123 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 124 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 127 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Kumar Gala | 8e55313 | 2008-08-26 23:52:58 -0500 | [diff] [blame] | 128 | #define CONFIG_VERY_BIG_RAM |
| 129 | |
| 130 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 131 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 132 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 133 | |
| 134 | /* I2C addresses of SPD EEPROMs */ |
| 135 | #define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ |
| 136 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 137 | #undef CONFIG_CLOCKS_IN_MHZ |
| 138 | |
| 139 | #if defined(CONFIG_RAM_AS_FLASH) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
| 141 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ |
| 142 | #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */ |
| 143 | #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 144 | #else /* Boot from real Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 145 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ |
| 146 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
| 147 | #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */ |
| 148 | #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 149 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 151 | |
| 152 | /* local bus definitions */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ |
| 154 | #define CONFIG_SYS_OR1_PRELIM 0xfc000ff7 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 155 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */ |
| 157 | #define CONFIG_SYS_OR2_PRELIM 0x00000000 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 158 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 159 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ |
| 160 | #define CONFIG_SYS_OR3_PRELIM 0xfc000cc1 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 161 | |
| 162 | #if defined(CONFIG_RAM_AS_FLASH) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 163 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 164 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 166 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_OR4_PRELIM 0xfc000cc1 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 168 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | #define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 170 | #if 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_OR5_PRELIM 0xff000ff7 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 172 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_OR5_PRELIM 0xff0000f0 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 174 | #endif |
| 175 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | #define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ |
| 177 | #define CONFIG_SYS_OR6_PRELIM 0xfc000ff7 |
| 178 | #define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */ |
| 179 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 180 | #define CONFIG_SYS_LBC_LSRT 0x20000000 |
| 181 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 |
| 182 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 |
| 183 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 |
| 184 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 |
| 185 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 |
| 186 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 187 | |
| 188 | /* just hijack the MOT BCSR def for SBC8560 misc devices */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | #define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 190 | /* the size of CS5 needs to be >= 16M for TLB and LAW setups */ |
| 191 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 193 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ |
| 194 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 195 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 197 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 198 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 199 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 201 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 202 | |
| 203 | /* Serial Port */ |
| 204 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
| 205 | #undef CONFIG_CONS_NONE /* define if console on something else */ |
| 206 | |
| 207 | #define CONFIG_CONS_INDEX 1 |
| 208 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_NS16550 |
| 210 | #define CONFIG_SYS_NS16550_SERIAL |
| 211 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 212 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 214 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 215 | #define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 216 | #endif |
| 217 | |
| 218 | #define CONFIG_BAUDRATE 9600 |
| 219 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 220 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 221 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 222 | |
| 223 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 224 | #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000) |
| 225 | #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000) |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 226 | #else |
wdenk | 8b74bf3 | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 227 | /* SBC8540 uses internal COMM controller */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 228 | #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500) |
| 229 | #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600) |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 230 | #endif |
| 231 | |
| 232 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 233 | #define CONFIG_SYS_HUSH_PARSER |
| 234 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 235 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 236 | #endif |
| 237 | |
Jon Loeliger | 2047672 | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 238 | /* |
| 239 | * I2C |
| 240 | */ |
| 241 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 242 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 243 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 244 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 245 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 246 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 247 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 248 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 |
| 250 | #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 |
| 251 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 252 | |
| 253 | #if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ |
| 254 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 255 | # define CONFIG_NET_MULTI 1 |
| 256 | # define CONFIG_MPC85xx_TSEC1 |
| 257 | # define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" |
| 258 | # define CONFIG_MII 1 /* MII PHY management */ |
| 259 | # define TSEC1_PHY_ADDR 25 |
| 260 | # define TSEC1_PHYIDX 0 |
| 261 | /* Options are: TSEC0 */ |
| 262 | # define CONFIG_ETHPRIME "TSEC0" |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 263 | |
wdenk | 8b74bf3 | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 264 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 265 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
| 266 | |
| 267 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
| 268 | #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ |
| 269 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
wdenk | 8b74bf3 | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 270 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 271 | #if (CONFIG_ETHER_INDEX == 2) |
| 272 | /* |
| 273 | * - Rx-CLK is CLK13 |
| 274 | * - Tx-CLK is CLK14 |
| 275 | * - Select bus for bd/buffers |
| 276 | * - Full duplex |
| 277 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
| 279 | #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
| 280 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
| 281 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) |
wdenk | 8b74bf3 | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 282 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 283 | #elif (CONFIG_ETHER_INDEX == 3) |
| 284 | /* need more definitions here for FE3 */ |
| 285 | #endif /* CONFIG_ETHER_INDEX */ |
wdenk | 8b74bf3 | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 286 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 287 | #define CONFIG_MII /* MII PHY management */ |
| 288 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
| 289 | /* |
| 290 | * GPIO pins used for bit-banged MII communications |
| 291 | */ |
| 292 | #define MDIO_PORT 2 /* Port C */ |
Luigi 'Comio' Mantellini | be22544 | 2009-10-10 12:42:22 +0200 | [diff] [blame] | 293 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
| 294 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) |
| 295 | #define MDC_DECLARE MDIO_DECLARE |
| 296 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 297 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
| 298 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) |
| 299 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) |
| 300 | |
| 301 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
| 302 | else iop->pdat &= ~0x00400000 |
| 303 | |
| 304 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ |
| 305 | else iop->pdat &= ~0x00200000 |
| 306 | |
| 307 | #define MIIDELAY udelay(1) |
wdenk | 8b74bf3 | 2004-10-11 23:10:30 +0000 | [diff] [blame] | 308 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 309 | #endif |
| 310 | |
| 311 | /*----------------------------------------------------------------------- |
| 312 | * FLASH and environment organization |
| 313 | */ |
| 314 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 316 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 317 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 318 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 319 | #define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 320 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 321 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ |
| 322 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 323 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 324 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 325 | #define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ |
| 326 | #define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 327 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 328 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 329 | |
| 330 | #if 0 |
| 331 | /* XXX This doesn't work and I don't want to fix it */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 332 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 333 | #define CONFIG_SYS_RAMBOOT |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 334 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 335 | #undef CONFIG_SYS_RAMBOOT |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 336 | #endif |
| 337 | #endif |
| 338 | |
| 339 | /* Environment */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 340 | #if !defined(CONFIG_SYS_RAMBOOT) |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 341 | #if defined(CONFIG_RAM_AS_FLASH) |
Jean-Christophe PLAGNIOL-VILLARD | 93f6d72 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 342 | #define CONFIG_ENV_IS_NOWHERE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 343 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 344 | #define CONFIG_ENV_SIZE 0x2000 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 345 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 346 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 347 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 348 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 349 | #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 350 | #endif |
| 351 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 352 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
Jean-Christophe PLAGNIOL-VILLARD | 93f6d72 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 353 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 354 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 355 | #define CONFIG_ENV_SIZE 0x2000 |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 356 | #endif |
| 357 | |
| 358 | #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" |
| 359 | /*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ |
| 360 | #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" |
| 361 | #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ |
| 362 | |
| 363 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 364 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 365 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 366 | |
| 367 | /* |
Jon Loeliger | a1aa0bb | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 368 | * BOOTP options |
| 369 | */ |
| 370 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 371 | #define CONFIG_BOOTP_BOOTPATH |
| 372 | #define CONFIG_BOOTP_GATEWAY |
| 373 | #define CONFIG_BOOTP_HOSTNAME |
| 374 | |
| 375 | |
| 376 | /* |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 377 | * Command line configuration. |
| 378 | */ |
| 379 | #include <config_cmd_default.h> |
| 380 | |
| 381 | #define CONFIG_CMD_PING |
| 382 | #define CONFIG_CMD_I2C |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame^] | 383 | #define CONFIG_CMD_REGINFO |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 384 | |
| 385 | #if defined(CONFIG_PCI) |
| 386 | #define CONFIG_CMD_PCI |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 387 | #endif |
| 388 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 389 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
| 390 | #define CONFIG_CMD_MII |
| 391 | #endif |
| 392 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 393 | #if defined(CONFIG_SYS_RAMBOOT) |
Mike Frysinger | bdab39d | 2009-01-28 19:08:14 -0500 | [diff] [blame] | 394 | #undef CONFIG_CMD_SAVEENV |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 395 | #undef CONFIG_CMD_LOADS |
| 396 | #endif |
| 397 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 398 | |
| 399 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 400 | |
| 401 | /* |
| 402 | * Miscellaneous configurable options |
| 403 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 404 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 405 | #define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */ |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 406 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 407 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 408 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 409 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 410 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 411 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 412 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 413 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 414 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
| 415 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 416 | |
| 417 | /* |
| 418 | * For booting Linux, the board info and command line data |
| 419 | * have to be in the first 8 MB of memory, since this is |
| 420 | * the maximum mapped by the Linux kernel during initialization. |
| 421 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 422 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 423 | |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 424 | /* |
| 425 | * Internal Definitions |
| 426 | * |
| 427 | * Boot Flags |
| 428 | */ |
| 429 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 430 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 431 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 432 | #if defined(CONFIG_CMD_KGDB) |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 433 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 434 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 435 | #endif |
| 436 | |
| 437 | /*Note: change below for your network setting!!! */ |
| 438 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
wdenk | e2ffd59 | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 439 | # define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a |
| 440 | # define CONFIG_HAS_ETH1 |
| 441 | # define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b |
| 442 | # define CONFIG_HAS_ETH2 |
| 443 | # define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c |
wdenk | c15f312 | 2004-10-10 22:44:24 +0000 | [diff] [blame] | 444 | #endif |
| 445 | |
| 446 | #define CONFIG_SERVERIP YourServerIP |
| 447 | #define CONFIG_IPADDR YourTargetIP |
| 448 | #define CONFIG_GATEWAYIP YourGatewayIP |
| 449 | #define CONFIG_NETMASK 255.255.255.0 |
| 450 | #define CONFIG_HOSTNAME SBC8560 |
| 451 | #define CONFIG_ROOTPATH YourRootPath |
| 452 | #define CONFIG_BOOTFILE YourImageName |
| 453 | |
| 454 | #endif /* __CONFIG_H */ |