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wdenkc15f3122004-10-10 22:44:24 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8540 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* mpc8560ads board configuration file */
28/* please refer to doc/README.mpc85xx for more info */
29/* make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
31 */
wdenk8b74bf32004-10-11 23:10:30 +000032
wdenkc15f3122004-10-10 22:44:24 +000033#ifndef __CONFIG_H
34#define __CONFIG_H
35
36#if XXX
37#define DEBUG /* General debug */
38#define ET_DEBUG
39#endif
40#define TSEC_DEBUG
41
42/* High Level Configuration Options */
43#define CONFIG_BOOKE 1 /* BOOKE */
44#define CONFIG_E500 1 /* BOOKE e500 family */
45#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
46#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
47
48
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050049#define CONFIG_CPM2 1 /* has CPM2 */
wdenkc15f3122004-10-10 22:44:24 +000050
Wolfgang Denk53677ef2008-05-20 16:00:29 +020051#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
Kumar Galaf0600542008-06-11 00:44:10 -050052#define CONFIG_MPC8540 1
wdenkc15f3122004-10-10 22:44:24 +000053
54#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
55
56#define CONFIG_TSEC_ENET /* tsec ethernet support */
57#undef CONFIG_PCI /* pci ethernet support */
58#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
59
Kumar Galae2b159d2008-01-16 09:05:27 -060060#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenkc15f3122004-10-10 22:44:24 +000061
62#define CONFIG_ENV_OVERWRITE
63
64/* Using Localbus SDRAM to emulate flash before we can program the flash,
65 * normally you need a flash-boot image(u-boot.bin), if so undef this.
66 */
67#undef CONFIG_RAM_AS_FLASH
68
69#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
70 #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
71#else
72 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
73#endif
74
75/* below can be toggled for performance analysis. otherwise use default */
76#define CONFIG_L2_CACHE /* toggle L2 cache */
77#undef CONFIG_BTB /* toggle branch predition */
78#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
79
80#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
83#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
84#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenkc15f3122004-10-10 22:44:24 +000085
86#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
87 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
88 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
89#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
90#endif
91
92/*
93 * Base addresses -- Note these are effective addresses where the
94 * actual resources get mapped (not physical addresses)
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
wdenkc15f3122004-10-10 22:44:24 +000097
98#if XXX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
wdenkc15f3122004-10-10 22:44:24 +0000100#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101 #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
wdenkc15f3122004-10-10 22:44:24 +0000102#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
104#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenkc15f3122004-10-10 22:44:24 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
wdenkc15f3122004-10-10 22:44:24 +0000107
Kumar Gala8e553132008-08-26 23:52:58 -0500108/* DDR Setup */
109#define CONFIG_FSL_DDR1
110#undef CONFIG_FSL_DDR_INTERACTIVE
wdenkc15f3122004-10-10 22:44:24 +0000111#undef CONFIG_DDR_ECC /* only for ECC DDR module */
112#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
Kumar Gala8e553132008-08-26 23:52:58 -0500113#undef CONFIG_DDR_SPD
wdenkc15f3122004-10-10 22:44:24 +0000114
115#if defined(CONFIG_MPC85xx_REV1)
116 #define CONFIG_DDR_DLL /* possible DLL fix needed */
117#endif
118
Kumar Gala8e553132008-08-26 23:52:58 -0500119#undef CONFIG_DDR_ECC /* only for ECC DDR module */
120#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
121#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala8e553132008-08-26 23:52:58 -0500125#define CONFIG_VERY_BIG_RAM
126
127#define CONFIG_NUM_DDR_CONTROLLERS 1
128#define CONFIG_DIMM_SLOTS_PER_CTLR 1
129#define CONFIG_CHIP_SELECTS_PER_CTRL 2
130
131/* I2C addresses of SPD EEPROMs */
132#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
133
wdenkc15f3122004-10-10 22:44:24 +0000134#undef CONFIG_CLOCKS_IN_MHZ
135
136#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
138 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
139 #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
140 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
wdenkc15f3122004-10-10 22:44:24 +0000141#else /* Boot from real Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
143 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
144 #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
145 #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
wdenkc15f3122004-10-10 22:44:24 +0000146#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenkc15f3122004-10-10 22:44:24 +0000148
149/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
151#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
wdenkc15f3122004-10-10 22:44:24 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
154#define CONFIG_SYS_OR2_PRELIM 0x00000000
wdenkc15f3122004-10-10 22:44:24 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
157#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
wdenkc15f3122004-10-10 22:44:24 +0000158
159#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
wdenkc15f3122004-10-10 22:44:24 +0000161#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162 #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
wdenkc15f3122004-10-10 22:44:24 +0000163#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
wdenkc15f3122004-10-10 22:44:24 +0000165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
wdenkc15f3122004-10-10 22:44:24 +0000167#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
wdenkc15f3122004-10-10 22:44:24 +0000169#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
wdenkc15f3122004-10-10 22:44:24 +0000171#endif
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
174#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
175#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
176#define CONFIG_SYS_LBC_LBCR 0x00000000
177#define CONFIG_SYS_LBC_LSRT 0x20000000
178#define CONFIG_SYS_LBC_MRTPR 0x20000000
179#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
180#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
181#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
182#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
183#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenkc15f3122004-10-10 22:44:24 +0000184
185/* just hijack the MOT BCSR def for SBC8560 misc devices */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
wdenkc15f3122004-10-10 22:44:24 +0000187/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
188
189#define CONFIG_L1_INIT_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_INIT_RAM_LOCK 1
191#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
192#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenkc15f3122004-10-10 22:44:24 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
195#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
196#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc15f3122004-10-10 22:44:24 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
199#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenkc15f3122004-10-10 22:44:24 +0000200
201/* Serial Port */
202#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
203#undef CONFIG_CONS_NONE /* define if console on something else */
204
205#define CONFIG_CONS_INDEX 1
206#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_NS16550
208#define CONFIG_SYS_NS16550_SERIAL
209#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkc15f3122004-10-10 22:44:24 +0000210#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
wdenkc15f3122004-10-10 22:44:24 +0000212#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */
wdenkc15f3122004-10-10 22:44:24 +0000214#endif
215
216#define CONFIG_BAUDRATE 9600
217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc15f3122004-10-10 22:44:24 +0000219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
220
221#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
223#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
wdenkc15f3122004-10-10 22:44:24 +0000224#else
wdenk8b74bf32004-10-11 23:10:30 +0000225/* SBC8540 uses internal COMM controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
227#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
wdenkc15f3122004-10-10 22:44:24 +0000228#endif
229
230/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_HUSH_PARSER
232#ifdef CONFIG_SYS_HUSH_PARSER
233#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc15f3122004-10-10 22:44:24 +0000234#endif
235
Jon Loeliger20476722006-10-20 15:50:15 -0500236/*
237 * I2C
238 */
239#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
240#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenkc15f3122004-10-10 22:44:24 +0000241#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
243#define CONFIG_SYS_I2C_SLAVE 0x7F
244#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
245#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenkc15f3122004-10-10 22:44:24 +0000246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
248#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
249#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
wdenkc15f3122004-10-10 22:44:24 +0000250
251#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
252
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500253# define CONFIG_NET_MULTI 1
254# define CONFIG_MPC85xx_TSEC1
255# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
256# define CONFIG_MII 1 /* MII PHY management */
257# define TSEC1_PHY_ADDR 25
258# define TSEC1_PHYIDX 0
259/* Options are: TSEC0 */
260# define CONFIG_ETHPRIME "TSEC0"
wdenkc15f3122004-10-10 22:44:24 +0000261
wdenk8b74bf32004-10-11 23:10:30 +0000262
wdenkc15f3122004-10-10 22:44:24 +0000263#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
264
265 #undef CONFIG_ETHER_NONE /* define if ether on something else */
266 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
267 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk8b74bf32004-10-11 23:10:30 +0000268
wdenkc15f3122004-10-10 22:44:24 +0000269 #if (CONFIG_ETHER_INDEX == 2)
270 /*
271 * - Rx-CLK is CLK13
272 * - Tx-CLK is CLK14
273 * - Select bus for bd/buffers
274 * - Full duplex
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
277 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
278 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
279 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk8b74bf32004-10-11 23:10:30 +0000280
wdenkc15f3122004-10-10 22:44:24 +0000281 #elif (CONFIG_ETHER_INDEX == 3)
282 /* need more definitions here for FE3 */
283 #endif /* CONFIG_ETHER_INDEX */
wdenk8b74bf32004-10-11 23:10:30 +0000284
wdenkc15f3122004-10-10 22:44:24 +0000285 #define CONFIG_MII /* MII PHY management */
286 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
287 /*
288 * GPIO pins used for bit-banged MII communications
289 */
290 #define MDIO_PORT 2 /* Port C */
291 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
292 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
293 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
294
295 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
296 else iop->pdat &= ~0x00400000
297
298 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
299 else iop->pdat &= ~0x00200000
300
301 #define MIIDELAY udelay(1)
wdenk8b74bf32004-10-11 23:10:30 +0000302
wdenkc15f3122004-10-10 22:44:24 +0000303#endif
304
305/*-----------------------------------------------------------------------
306 * FLASH and environment organization
307 */
308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200310#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenkc15f3122004-10-10 22:44:24 +0000311#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
313#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
wdenkc15f3122004-10-10 22:44:24 +0000314#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
316#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenkc15f3122004-10-10 22:44:24 +0000317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#undef CONFIG_SYS_FLASH_CHECKSUM
319#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
320#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
wdenkc15f3122004-10-10 22:44:24 +0000321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenkc15f3122004-10-10 22:44:24 +0000323
324#if 0
325/* XXX This doesn't work and I don't want to fix it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
327 #define CONFIG_SYS_RAMBOOT
wdenkc15f3122004-10-10 22:44:24 +0000328#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329 #undef CONFIG_SYS_RAMBOOT
wdenkc15f3122004-10-10 22:44:24 +0000330#endif
331#endif
332
333/* Environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#if !defined(CONFIG_SYS_RAMBOOT)
wdenkc15f3122004-10-10 22:44:24 +0000335 #if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200336 #define CONFIG_ENV_IS_NOWHERE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200338 #define CONFIG_ENV_SIZE 0x2000
wdenkc15f3122004-10-10 22:44:24 +0000339 #else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200340 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200341 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200343 #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
wdenkc15f3122004-10-10 22:44:24 +0000344 #endif
345#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200347 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200349 #define CONFIG_ENV_SIZE 0x2000
wdenkc15f3122004-10-10 22:44:24 +0000350#endif
351
352#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
353/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
354#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
355#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
356
357#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc15f3122004-10-10 22:44:24 +0000359
Jon Loeliger2835e512007-06-13 13:22:08 -0500360
361/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500362 * BOOTP options
363 */
364#define CONFIG_BOOTP_BOOTFILESIZE
365#define CONFIG_BOOTP_BOOTPATH
366#define CONFIG_BOOTP_GATEWAY
367#define CONFIG_BOOTP_HOSTNAME
368
369
370/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500371 * Command line configuration.
372 */
373#include <config_cmd_default.h>
374
375#define CONFIG_CMD_PING
376#define CONFIG_CMD_I2C
377
378#if defined(CONFIG_PCI)
379 #define CONFIG_CMD_PCI
wdenkc15f3122004-10-10 22:44:24 +0000380#endif
381
Jon Loeliger2835e512007-06-13 13:22:08 -0500382#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
383 #define CONFIG_CMD_MII
384#endif
385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger2835e512007-06-13 13:22:08 -0500387 #undef CONFIG_CMD_ENV
388 #undef CONFIG_CMD_LOADS
389#endif
390
wdenkc15f3122004-10-10 22:44:24 +0000391
392#undef CONFIG_WATCHDOG /* watchdog disabled */
393
394/*
395 * Miscellaneous configurable options
396 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_LONGHELP /* undef to save memory */
398#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500399#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc15f3122004-10-10 22:44:24 +0000401#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc15f3122004-10-10 22:44:24 +0000403#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
405#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
406#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
407#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
408#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc15f3122004-10-10 22:44:24 +0000409
410/*
411 * For booting Linux, the board info and command line data
412 * have to be in the first 8 MB of memory, since this is
413 * the maximum mapped by the Linux kernel during initialization.
414 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc15f3122004-10-10 22:44:24 +0000416
wdenkc15f3122004-10-10 22:44:24 +0000417/*
418 * Internal Definitions
419 *
420 * Boot Flags
421 */
422#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
423#define BOOTFLAG_WARM 0x02 /* Software reboot */
424
Jon Loeliger2835e512007-06-13 13:22:08 -0500425#if defined(CONFIG_CMD_KGDB)
wdenkc15f3122004-10-10 22:44:24 +0000426 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
427 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
428#endif
429
430/*Note: change below for your network setting!!! */
431#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000432# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
433# define CONFIG_HAS_ETH1
434# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
435# define CONFIG_HAS_ETH2
436# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
wdenkc15f3122004-10-10 22:44:24 +0000437#endif
438
439#define CONFIG_SERVERIP YourServerIP
440#define CONFIG_IPADDR YourTargetIP
441#define CONFIG_GATEWAYIP YourGatewayIP
442#define CONFIG_NETMASK 255.255.255.0
443#define CONFIG_HOSTNAME SBC8560
444#define CONFIG_ROOTPATH YourRootPath
445#define CONFIG_BOOTFILE YourImageName
446
447#endif /* __CONFIG_H */