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jason6af3a0e2013-11-06 22:59:08 +08001/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
TsiChung Liew6d33c6a2008-07-23 17:11:47 -05002 * Hayden Fraser (Hayden.Fraser@freescale.com)
3 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew6d33c6a2008-07-23 17:11:47 -05005 */
6
7#ifndef _M5253DEMO_H
8#define _M5253DEMO_H
9
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050010#define CONFIG_M5253DEMO /* define board type */
11
12#define CONFIG_MCFTMR
13
14#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020015#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050016
17#undef CONFIG_WATCHDOG /* disable watchdog */
18
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050019
20/* Configuration for environment
21 * Environment is embedded in u-boot in the second sector of the flash
22 */
23#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020024# define CONFIG_ENV_OFFSET 0x4000
25# define CONFIG_ENV_SECT_SIZE 0x1000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050026#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020028# define CONFIG_ENV_SECT_SIZE 0x1000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050029#endif
30
angelo@sysam.it5296cb12015-03-29 22:54:16 +020031#define LDS_BOARD_TEXT \
Simon Glass0649cd02017-08-03 12:21:49 -060032 . = DEFINED(env_offset) ? env_offset : .; \
33 env/embedded.o(.text*);
angelo@sysam.it5296cb12015-03-29 22:54:16 +020034
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050035/*
36 * Command line configuration.
37 */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050038
Simon Glassfc843a02017-05-17 03:25:30 -060039#ifdef CONFIG_IDE
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050040/* ATA */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050041# define CONFIG_IDE_RESET 1
42# define CONFIG_IDE_PREINIT 1
43# define CONFIG_ATAPI
44# undef CONFIG_LBA48
45
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046# define CONFIG_SYS_IDE_MAXBUS 1
47# define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050048
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
50# define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
53# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
54# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
55# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050056#endif
57
58#define CONFIG_DRIVER_DM9000
59#ifdef CONFIG_DRIVER_DM9000
TsiChung Liew012522f2008-10-21 10:03:07 +000060# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050061# define DM9000_IO CONFIG_DM9000_BASE
62# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
63# undef CONFIG_DM9000_DEBUG
Jason Jinf73e7d62011-08-19 10:18:15 +080064# define CONFIG_DM9000_BYTE_SWAPPED
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050065
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050066# define CONFIG_OVERWRITE_ETHADDR_ONCE
67
68# define CONFIG_EXTRA_ENV_SETTINGS \
69 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020070 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050071 "loadaddr=10000\0" \
72 "u-boot=u-boot.bin\0" \
73 "load=tftp ${loadaddr) ${u-boot}\0" \
74 "upd=run load; run prog\0" \
TsiChung Liewac265f72010-03-10 11:56:36 -060075 "prog=prot off 0xff800000 0xff82ffff;" \
76 "era 0xff800000 0xff82ffff;" \
TsiChung Liewf26a2472010-03-15 19:39:21 -050077 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050078 "save\0" \
79 ""
80#endif
81
82#define CONFIG_HOSTNAME M5253DEMO
83
TsiChung Lieweec567a2008-08-19 03:01:19 +060084/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020085#define CONFIG_SYS_I2C
86#define CONFIG_SYS_I2C_FSL
87#define CONFIG_SYS_FSL_I2C_SPEED 80000
88#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
89#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
91#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
92#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
93#define CONFIG_SYS_I2C_PINMUX_SET (0)
TsiChung Lieweec567a2008-08-19 03:01:19 +060094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_LOAD_ADDR 0x00100000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -050098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MEMTEST_START 0x400
100#define CONFIG_SYS_MEMTEST_END 0x380000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
103#define CONFIG_SYS_FAST_CLK
104#ifdef CONFIG_SYS_FAST_CLK
105# define CONFIG_SYS_PLLCR 0x1243E054
106# define CONFIG_SYS_CLK 140000000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500107#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108# define CONFIG_SYS_PLLCR 0x135a4140
109# define CONFIG_SYS_CLK 70000000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500110#endif
111
112/*
113 * Low Level Configuration Settings
114 * (address mappings, register initial values, etc.)
115 * You should know what you are doing if you make changes here.
116 */
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
119#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500120
121/*
122 * Definitions for initial stack pointer and data area (in DPRAM)
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200125#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200126#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500128
129/*
130 * Start addresses for the final memory configuration
131 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_SDRAM_BASE 0x00000000
135#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500136
137#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# define CONFIG_SYS_MONITOR_BASE 0x20000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500139#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500141#endif
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_MONITOR_LEN 0x40000
144#define CONFIG_SYS_MALLOC_LEN (256 << 10)
145#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500146
147/*
148 * For booting Linux, the board info and command line data
149 * have to be in the first 8 MB of memory, since this is
150 * the maximum mapped by the Linux kernel during initialization ??
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000153#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500154
155/* FLASH organization */
TsiChung Liew012522f2008-10-21 10:03:07 +0000156#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
158#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
159#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500160
161#define FLASH_SST6401B 0x200
162#define SST_ID_xF6401B 0x236D236D
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#undef CONFIG_SYS_FLASH_CFI
165#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500166/*
167 * Unable to use CFI driver, due to incompatible sector erase command by SST.
168 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
169 * 0x30 is block erase in SST
170 */
Jean-Christophe PLAGNIOL-VILLARD0de0afb2008-08-15 18:32:41 +0200171# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172# define CONFIG_SYS_FLASH_SIZE 0x800000
173# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500174# define CONFIG_FLASH_CFI_LEGACY
175#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176# define CONFIG_SYS_SST_SECT 2048
177# define CONFIG_SYS_SST_SECTSZ 0x1000
178# define CONFIG_SYS_FLASH_WRITE_TOUT 500
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500179#endif
180
181/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500183
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600184#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200185 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600186#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200187 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600188#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
189#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
190 CF_ADDRMASK(8) | \
191 CF_ACR_EN | CF_ACR_SM_ALL)
192#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
193 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
194 CF_ACR_EN | CF_ACR_SM_ALL)
195#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
196 CF_CACR_DBWE)
197
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500198/* Port configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_FECI2C 0xF0
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500200
TsiChung Liew012522f2008-10-21 10:03:07 +0000201#define CONFIG_SYS_CS0_BASE 0xFF800000
202#define CONFIG_SYS_CS0_MASK 0x007F0021
203#define CONFIG_SYS_CS0_CTRL 0x00001D80
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500204
TsiChung Liew012522f2008-10-21 10:03:07 +0000205#define CONFIG_SYS_CS1_BASE 0xE0000000
206#define CONFIG_SYS_CS1_MASK 0x00000001
207#define CONFIG_SYS_CS1_CTRL 0x00003DD8
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500208
209/*-----------------------------------------------------------------------
210 * Port configuration
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
213#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
214#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
215#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
216#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
217#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
218#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChung Liew6d33c6a2008-07-23 17:11:47 -0500219
220#endif /* _M5253DEMO_H */