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wdenka56bd922004-06-06 23:13:55 +00001/*
wdenk1eaeb582004-06-08 00:22:43 +00002 * (C) Copyright 2003-2004
wdenka56bd922004-06-06 23:13:55 +00003 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk1eaeb582004-06-08 00:22:43 +000018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenka56bd922004-06-06 23:13:55 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
wdenka56bd922004-06-06 23:13:55 +000030/* allow to overwrite serial and ethaddr */
31#define CONFIG_ENV_OVERWRITE
32
wdenka56bd922004-06-06 23:13:55 +000033/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
wdenk1eaeb582004-06-08 00:22:43 +000038#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP730 1 /* which is in a 730 */
41#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
wdenka56bd922004-06-06 23:13:55 +000042
wdenk1eaeb582004-06-08 00:22:43 +000043/*
44 * Input clock of PLL
45 * The OMAP730 Perseus 2 has 13MHz input clock
wdenka56bd922004-06-06 23:13:55 +000046 */
47
wdenk1eaeb582004-06-08 00:22:43 +000048#define CONFIG_SYS_CLK_FREQ 13000000
wdenka56bd922004-06-06 23:13:55 +000049
wdenk1eaeb582004-06-08 00:22:43 +000050#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenka56bd922004-06-06 23:13:55 +000051
52#define CONFIG_MISC_INIT_R
53
wdenk1eaeb582004-06-08 00:22:43 +000054#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenka56bd922004-06-06 23:13:55 +000055#define CONFIG_SETUP_MEMORY_TAGS 1
56
wdenka56bd922004-06-06 23:13:55 +000057/*
58 * Size of malloc() pool
59 */
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenka56bd922004-06-06 23:13:55 +000062
63/*
64 * Hardware drivers
65 */
66
Nishanth Menonac6b3622009-10-16 00:06:37 -050067#define CONFIG_LAN91C96
wdenk1eaeb582004-06-08 00:22:43 +000068#define CONFIG_LAN91C96_BASE 0x04000300
wdenka56bd922004-06-06 23:13:55 +000069#define CONFIG_LAN91C96_EXT_PHY
70
wdenka56bd922004-06-06 23:13:55 +000071/*
72 * NS16550 Configuration
73 */
74
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_NS16550
76#define CONFIG_SYS_NS16550_SERIAL
77#define CONFIG_SYS_NS16550_REG_SIZE (1)
78#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
79#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
wdenk1eaeb582004-06-08 00:22:43 +000080 * on perseus */
wdenka56bd922004-06-06 23:13:55 +000081
82/*
83 * select serial console configuration
84 */
85
wdenk1eaeb582004-06-08 00:22:43 +000086#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
wdenka56bd922004-06-06 23:13:55 +000087
wdenk1eaeb582004-06-08 00:22:43 +000088#define CONFIG_CONS_INDEX 1
89#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenka56bd922004-06-06 23:13:55 +000091
wdenka56bd922004-06-06 23:13:55 +000092
wdenk1eaeb582004-06-08 00:22:43 +000093/*
Jon Loeligera5cb2302007-07-04 22:33:13 -050094 * Command line configuration.
wdenka56bd922004-06-06 23:13:55 +000095 */
Jon Loeligera5cb2302007-07-04 22:33:13 -050096#include <config_cmd_default.h>
wdenka56bd922004-06-06 23:13:55 +000097
Jon Loeligera5cb2302007-07-04 22:33:13 -050098#define CONFIG_CMD_DHCP
99
100
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500101/*
102 * BOOTP options
103 */
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107#define CONFIG_BOOTP_BOOTPATH
108
Jon Loeligera5cb2302007-07-04 22:33:13 -0500109
wdenka56bd922004-06-06 23:13:55 +0000110#include <configs/omap730.h>
111#include <configs/h2_p2_dbg_board.h>
112
wdenk1eaeb582004-06-08 00:22:43 +0000113#define CONFIG_BOOTDELAY 3
114#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
wdenka56bd922004-06-06 23:13:55 +0000115
wdenk1eaeb582004-06-08 00:22:43 +0000116#define CONFIG_LOADADDR 0x10000000
wdenka56bd922004-06-06 23:13:55 +0000117
118#define CONFIG_ETHADDR
wdenk1eaeb582004-06-08 00:22:43 +0000119#define CONFIG_NETMASK 255.255.255.0
120#define CONFIG_IPADDR 192.168.0.23
121#define CONFIG_SERVERIP 192.150.0.100
122#define CONFIG_BOOTFILE "uImage" /* File to load */
wdenka56bd922004-06-06 23:13:55 +0000123
Jon Loeligera5cb2302007-07-04 22:33:13 -0500124#if defined(CONFIG_CMD_KGDB)
wdenk1eaeb582004-06-08 00:22:43 +0000125#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
126#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
wdenka56bd922004-06-06 23:13:55 +0000127#endif
128
wdenka56bd922004-06-06 23:13:55 +0000129/*
130 * Miscellaneous configurable options
131 */
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_LONGHELP /* undef to save memory */
134#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
135#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000136/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
138#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
142#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenka56bd922004-06-06 23:13:55 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenka56bd922004-06-06 23:13:55 +0000145
wdenk1eaeb582004-06-08 00:22:43 +0000146/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
147 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
wdenka56bd922004-06-06 23:13:55 +0000148 * local divisor.
149 */
Ladislav Michl81472d82009-03-30 18:58:41 +0200150#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
151#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
152#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
wdenka56bd922004-06-06 23:13:55 +0000153
154/*-----------------------------------------------------------------------
155 * Stack sizes
156 *
157 * The stack sizes are set up in start.S using the settings below
158 */
159
wdenk1eaeb582004-06-08 00:22:43 +0000160#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenka56bd922004-06-06 23:13:55 +0000161#ifdef CONFIG_USE_IRQ
wdenk1eaeb582004-06-08 00:22:43 +0000162#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
163#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenka56bd922004-06-06 23:13:55 +0000164#endif
165
wdenka56bd922004-06-06 23:13:55 +0000166/*-----------------------------------------------------------------------
167 * Physical Memory Map
168 */
169
wdenk1eaeb582004-06-08 00:22:43 +0000170#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
171#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
172#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
wdenka56bd922004-06-06 23:13:55 +0000173
174#if defined(CONFIG_CS0_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000175#define PHYS_FLASH_1 0x0C000000
wdenka56bd922004-06-06 23:13:55 +0000176#elif defined(CONFIG_CS3_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000177#define PHYS_FLASH_1 0x00000000
wdenka56bd922004-06-06 23:13:55 +0000178#else
179#error Unknown Boot Chip-Select number
180#endif
181
Aneesh V154f5342011-06-09 08:54:57 -0400182#define PHYS_SRAM 0x20000000
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenka56bd922004-06-06 23:13:55 +0000185
186/*-----------------------------------------------------------------------
187 * FLASH and environment organization
188 */
189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk1eaeb582004-06-08 00:22:43 +0000191#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
wdenka56bd922004-06-06 23:13:55 +0000193/* addr of environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
wdenka56bd922004-06-06 23:13:55 +0000195
196/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
198#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenka56bd922004-06-06 23:13:55 +0000199
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200200#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
202#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
wdenka56bd922004-06-06 23:13:55 +0000203
Aneesh V154f5342011-06-09 08:54:57 -0400204#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
205#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
206
wdenk1eaeb582004-06-08 00:22:43 +0000207#endif /* ! __CONFIG_H */