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wdenkd4ca31c2004-01-02 14:00:00 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc178d3d2004-01-24 20:25:54 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkd4ca31c2004-01-02 14:00:00 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
38
wdenk66ca92a2004-09-28 17:59:53 +000039#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
41#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
wdenk66ca92a2004-09-28 17:59:53 +000042#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
wdenkc178d3d2004-01-24 20:25:54 +000043 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
wdenkd4ca31c2004-01-02 14:00:00 +000045
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
wdenk75d1ea72004-01-31 20:06:54 +000047 /* (function measure_gclk() */
48 /* will be called) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#ifdef CONFIG_SYS_MEASURE_CPUCLK
50#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
wdenk75d1ea72004-01-31 20:06:54 +000051#endif
52
wdenkc178d3d2004-01-24 20:25:54 +000053#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenkd4ca31c2004-01-02 14:00:00 +000054
55#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56
wdenkc178d3d2004-01-24 20:25:54 +000057#define CONFIG_BOOTCOUNT_LIMIT
wdenkd4ca31c2004-01-02 14:00:00 +000058
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61#define CONFIG_BOARD_TYPES 1 /* support board types */
62
wdenkc178d3d2004-01-24 20:25:54 +000063#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010064 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +000065 "echo"
66
67#undef CONFIG_BOOTARGS
68
wdenkc178d3d2004-01-24 20:25:54 +000069#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkd4ca31c2004-01-02 14:00:00 +000070 "netdev=eth0\0" \
71 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010072 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000073 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010074 "addip=setenv bootargs ${bootargs} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
76 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000077 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010078 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000079 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010080 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000082 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020083 "hostname=TQM866M\0" \
84 "bootfile=TQM866M/uImage\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020085 "fdt_addr=400C0000\0" \
86 "kernel_addr=40100000\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020087 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020088 "u-boot=TQM866M/u-image.bin\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020089 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020090 "update=prot off 40000000 +${filesize};" \
91 "era 40000000 +${filesize};" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020092 "cp.b 200000 40000000 ${filesize};" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020093 "sete filesize;save\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000094 ""
95#define CONFIG_BOOTCOMMAND "run flash_self"
96
97#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkd4ca31c2004-01-02 14:00:00 +000099
100#undef CONFIG_WATCHDOG /* watchdog disabled */
101
wdenkc178d3d2004-01-24 20:25:54 +0000102#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenkd4ca31c2004-01-02 14:00:00 +0000103
104#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
105
106/* enable I2C and select the hardware/software driver */
107#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenkc178d3d2004-01-24 20:25:54 +0000108#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenkd4ca31c2004-01-02 14:00:00 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
111#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +0000112
113#ifdef CONFIG_SOFT_I2C
114/*
115 * Software (bit-bang) I2C driver configuration
116 */
117#define PB_SCL 0x00000020 /* PB 26 */
118#define PB_SDA 0x00000010 /* PB 27 */
119
120#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
121#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
122#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
123#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
124#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc178d3d2004-01-24 20:25:54 +0000125 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenkd4ca31c2004-01-02 14:00:00 +0000126#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc178d3d2004-01-24 20:25:54 +0000127 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenkd4ca31c2004-01-02 14:00:00 +0000128#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
129#endif /* CONFIG_SOFT_I2C */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
132#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
133#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
134#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkd4ca31c2004-01-02 14:00:00 +0000135
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500136/*
137 * BOOTP options
138 */
139#define CONFIG_BOOTP_SUBNETMASK
140#define CONFIG_BOOTP_GATEWAY
141#define CONFIG_BOOTP_HOSTNAME
142#define CONFIG_BOOTP_BOOTPATH
143#define CONFIG_BOOTP_BOOTFILESIZE
144
wdenkd4ca31c2004-01-02 14:00:00 +0000145
146#define CONFIG_MAC_PARTITION
147#define CONFIG_DOS_PARTITION
148
wdenka6cccae2004-02-06 21:48:22 +0000149#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
150
151#define CONFIG_TIMESTAMP /* but print image timestmps */
wdenkd4ca31c2004-01-02 14:00:00 +0000152
wdenkd4ca31c2004-01-02 14:00:00 +0000153
Jon Loeliger26946902007-07-04 22:30:50 -0500154/*
155 * Command line configuration.
156 */
157#include <config_cmd_default.h>
158
159#define CONFIG_CMD_ASKENV
160#define CONFIG_CMD_DHCP
161#define CONFIG_CMD_EEPROM
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200162#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100163#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500164#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200165#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500166#define CONFIG_CMD_NFS
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200167#define CONFIG_CMD_SNTP
168
169
170#define CONFIG_NETCONSOLE
Jon Loeliger26946902007-07-04 22:30:50 -0500171
wdenkd4ca31c2004-01-02 14:00:00 +0000172
173/*
174 * Miscellaneous configurable options
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LONGHELP /* undef to save memory */
177#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkd4ca31c2004-01-02 14:00:00 +0000178
Wolfgang Denk2751a952006-10-28 02:29:14 +0200179#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
181#ifdef CONFIG_SYS_HUSH_PARSER
182#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkd4ca31c2004-01-02 14:00:00 +0000183#endif
184
Jon Loeliger26946902007-07-04 22:30:50 -0500185#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000187#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000189#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
191#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
192#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
195#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkd4ca31c2004-01-02 14:00:00 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkd4ca31c2004-01-02 14:00:00 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkd4ca31c2004-01-02 14:00:00 +0000200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkd4ca31c2004-01-02 14:00:00 +0000202
203/*
204 * Low Level Configuration Settings
205 * (address mappings, register initial values, etc.)
206 * You should know what you are doing if you make changes here.
207 */
208/*-----------------------------------------------------------------------
209 * Internal Memory Mapped Register
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_IMMR 0xFFF00000
wdenkd4ca31c2004-01-02 14:00:00 +0000212
213/*-----------------------------------------------------------------------
214 * Definitions for initial stack pointer and data area (in DPRAM)
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
217#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
218#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
219#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
220#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkd4ca31c2004-01-02 14:00:00 +0000221
222/*-----------------------------------------------------------------------
223 * Start addresses for the final memory configuration
224 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkd4ca31c2004-01-02 14:00:00 +0000226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_SDRAM_BASE 0x00000000
228#define CONFIG_SYS_FLASH_BASE 0x40000000
229#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
230#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
231#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenkd4ca31c2004-01-02 14:00:00 +0000232
233/*
234 * For booting Linux, the board info and command line data
235 * have to be in the first 8 MB of memory, since this is
236 * the maximum mapped by the Linux kernel during initialization.
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd4ca31c2004-01-02 14:00:00 +0000239
240/*-----------------------------------------------------------------------
241 * FLASH organization
242 */
Martin Krausee318d9e2007-09-27 11:10:08 +0200243/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200245#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
247#define CONFIG_SYS_FLASH_EMPTY_INFO
248#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
249#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
250#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkd4ca31c2004-01-02 14:00:00 +0000251
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200252#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200253#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
254#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
255#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkd4ca31c2004-01-02 14:00:00 +0000256
257/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200258#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
259#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkd4ca31c2004-01-02 14:00:00 +0000260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200262
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200263#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
264
wdenkd4ca31c2004-01-02 14:00:00 +0000265/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200266 * Dynamic MTD partition support
267 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100268#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200269#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
270#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200271#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
272
273#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
274 "128k(dtb)," \
275 "1920k(kernel)," \
276 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200277 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200278
279/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000280 * Hardware Information Block
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
283#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
284#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkd4ca31c2004-01-02 14:00:00 +0000285
286/*-----------------------------------------------------------------------
287 * Cache Configuration
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500290#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkd4ca31c2004-01-02 14:00:00 +0000292#endif
293
294/*-----------------------------------------------------------------------
295 * SYPCR - System Protection Control 11-9
296 * SYPCR can only be written once after reset!
297 *-----------------------------------------------------------------------
298 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
299 */
300#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkd4ca31c2004-01-02 14:00:00 +0000302 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
303#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkd4ca31c2004-01-02 14:00:00 +0000305#endif
306
307/*-----------------------------------------------------------------------
308 * SIUMCR - SIU Module Configuration 11-6
309 *-----------------------------------------------------------------------
310 * PCMCIA config., multi-function pin tri-state
311 */
wdenkc178d3d2004-01-24 20:25:54 +0000312#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000314#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000316#endif /* CONFIG_CAN_DRIVER */
317
318/*-----------------------------------------------------------------------
319 * TBSCR - Time Base Status and Control 11-26
320 *-----------------------------------------------------------------------
321 * Clear Reference Interrupt Status, Timebase freezing enabled
322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkd4ca31c2004-01-02 14:00:00 +0000324
325/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000326 * PISCR - Periodic Interrupt Status and Control 11-31
327 *-----------------------------------------------------------------------
328 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkd4ca31c2004-01-02 14:00:00 +0000331
332/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000333 * SCCR - System Clock and reset Control Register 15-27
334 *-----------------------------------------------------------------------
335 * Set clock output, timebase and RTC source and divider,
336 * power management and some other internal clocks
337 */
338#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd4ca31c2004-01-02 14:00:00 +0000340 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
341 SCCR_DFALCD00)
wdenkd4ca31c2004-01-02 14:00:00 +0000342
343/*-----------------------------------------------------------------------
344 * PCMCIA stuff
345 *-----------------------------------------------------------------------
346 *
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
349#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
350#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
351#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
352#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
353#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
354#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
355#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkd4ca31c2004-01-02 14:00:00 +0000356
357/*-----------------------------------------------------------------------
358 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
359 *-----------------------------------------------------------------------
360 */
361
wdenkc178d3d2004-01-24 20:25:54 +0000362#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenkd4ca31c2004-01-02 14:00:00 +0000363
wdenkc178d3d2004-01-24 20:25:54 +0000364#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
365#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkd4ca31c2004-01-02 14:00:00 +0000366#undef CONFIG_IDE_RESET /* reset for ide not supported */
367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
369#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkd4ca31c2004-01-02 14:00:00 +0000370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkd4ca31c2004-01-02 14:00:00 +0000372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkd4ca31c2004-01-02 14:00:00 +0000374
375/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000377
378/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000380
381/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkd4ca31c2004-01-02 14:00:00 +0000383
384/*-----------------------------------------------------------------------
385 *
386 *-----------------------------------------------------------------------
387 *
388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_DER 0
wdenkd4ca31c2004-01-02 14:00:00 +0000390
391/*
392 * Init Memory Controller:
393 *
394 * BR0/1 and OR0/1 (FLASH)
395 */
396
397#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
398#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
399
400/* used to re-map FLASH both when starting from SRAM or FLASH:
401 * restrict access enough to keep SRAM working (if any)
402 * but not too much to meddle with FLASH accesses
403 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
405#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkd4ca31c2004-01-02 14:00:00 +0000406
407/*
wdenkc178d3d2004-01-24 20:25:54 +0000408 * FLASH timing: Default value of OR0 after reset
wdenkd4ca31c2004-01-02 14:00:00 +0000409 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
wdenkc178d3d2004-01-24 20:25:54 +0000411 OR_SCY_15_CLK | OR_TRLX)
wdenkd4ca31c2004-01-02 14:00:00 +0000412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
414#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
415#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
418#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
419#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000420
421/*
422 * BR2/3 and OR2/3 (SDRAM)
423 *
424 */
425#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
426#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenkc178d3d2004-01-24 20:25:54 +0000427#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
wdenkd4ca31c2004-01-02 14:00:00 +0000428
429/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkd4ca31c2004-01-02 14:00:00 +0000431
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
433#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000434
wdenkc178d3d2004-01-24 20:25:54 +0000435#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
437#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000438#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
440#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
441#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
442#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkd4ca31c2004-01-02 14:00:00 +0000443 BR_PS_8 | BR_MS_UPMB | BR_V )
444#endif /* CONFIG_CAN_DRIVER */
445
446/*
wdenkc178d3d2004-01-24 20:25:54 +0000447 * 4096 Rows from SDRAM example configuration
448 * 1000 factor s -> ms
449 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
450 * 4 Number of refresh cycles per period
451 * 64 Refresh cycle in ms per number of rows
wdenkd4ca31c2004-01-02 14:00:00 +0000452 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenkc178d3d2004-01-24 20:25:54 +0000454
455/*
Martin Kraused43e4892007-09-27 14:54:36 +0200456 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
457 *
458 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Martin Kraused43e4892007-09-27 14:54:36 +0200460 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
461 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
463 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
464 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
465 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Martin Kraused43e4892007-09-27 14:54:36 +0200466 *
467 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
468 * be met also in the default configuration, i.e. if environment variable
469 * 'cpuclk' is not set.
wdenkc178d3d2004-01-24 20:25:54 +0000470 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_MAMR_PTA 97
wdenkd4ca31c2004-01-02 14:00:00 +0000472
473/*
Martin Kraused43e4892007-09-27 14:54:36 +0200474 * Memory Periodic Timer Prescaler Register (MPTPR) values.
wdenkd4ca31c2004-01-02 14:00:00 +0000475 */
Martin Kraused43e4892007-09-27 14:54:36 +0200476/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Martin Kraused43e4892007-09-27 14:54:36 +0200478/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
wdenkd4ca31c2004-01-02 14:00:00 +0000480
481/*
482 * MAMR settings for SDRAM
483 */
484
485/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000487 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
488 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
489/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000491 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
492 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkc178d3d2004-01-24 20:25:54 +0000493/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc178d3d2004-01-24 20:25:54 +0000495 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
496 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkd4ca31c2004-01-02 14:00:00 +0000497
498/*
499 * Internal Definitions
500 *
501 * Boot Flags
502 */
wdenkc178d3d2004-01-24 20:25:54 +0000503#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenkd4ca31c2004-01-02 14:00:00 +0000504#define BOOTFLAG_WARM 0x02 /* Software reboot */
505
506#define CONFIG_SCC1_ENET
507#define CONFIG_FEC_ENET
508#define CONFIG_ETHPRIME "SCC ETHERNET"
509
510#endif /* __CONFIG_H */