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Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay067a4c02019-04-10 14:09:24 +02004 *
5 * STM32MP157C ED1 BOARD configuration
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01006 * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
7 * Reference used NT5CC256M16DP-DI from NANYA
8 *
9 * DDR type / Platform DDR3/3L
10 * freq 533MHz
11 * width 32
12 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
13 * DDR density 8
14 * timing mode optimized
15 * Scheduling/QoS options : type = 2
16 * address mapping : RBC
Patrick Delaunay067a4c02019-04-10 14:09:24 +020017 * Tc > + 85C : N
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010018 */
Patrick Delaunaybe16c412019-07-30 19:16:13 +020019#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
Patrick Delaunayc60fed12019-04-10 14:09:23 +020020#define DDR_MEM_SPEED 533000
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010021#define DDR_MEM_SIZE 0x40000000
22
23#define DDR_MSTR 0x00040401
24#define DDR_MRCTRL0 0x00000010
25#define DDR_MRCTRL1 0x00000000
26#define DDR_DERATEEN 0x00000000
27#define DDR_DERATEINT 0x00800000
28#define DDR_PWRCTL 0x00000000
29#define DDR_PWRTMG 0x00400010
30#define DDR_HWLPCTL 0x00000000
31#define DDR_RFSHCTL0 0x00210000
32#define DDR_RFSHCTL3 0x00000000
33#define DDR_RFSHTMG 0x0081008B
34#define DDR_CRCPARCTL0 0x00000000
35#define DDR_DRAMTMG0 0x121B2414
36#define DDR_DRAMTMG1 0x000A041C
37#define DDR_DRAMTMG2 0x0608090F
38#define DDR_DRAMTMG3 0x0050400C
39#define DDR_DRAMTMG4 0x08040608
40#define DDR_DRAMTMG5 0x06060403
41#define DDR_DRAMTMG6 0x02020002
42#define DDR_DRAMTMG7 0x00000202
43#define DDR_DRAMTMG8 0x00001005
44#define DDR_DRAMTMG14 0x000000A0
45#define DDR_ZQCTL0 0xC2000040
46#define DDR_DFITMG0 0x02060105
47#define DDR_DFITMG1 0x00000202
48#define DDR_DFILPCFG0 0x07000000
49#define DDR_DFIUPD0 0xC0400003
50#define DDR_DFIUPD1 0x00000000
51#define DDR_DFIUPD2 0x00000000
52#define DDR_DFIPHYMSTR 0x00000000
53#define DDR_ADDRMAP1 0x00080808
54#define DDR_ADDRMAP2 0x00000000
55#define DDR_ADDRMAP3 0x00000000
56#define DDR_ADDRMAP4 0x00001F1F
57#define DDR_ADDRMAP5 0x07070707
58#define DDR_ADDRMAP6 0x0F070707
59#define DDR_ADDRMAP9 0x00000000
60#define DDR_ADDRMAP10 0x00000000
61#define DDR_ADDRMAP11 0x00000000
62#define DDR_ODTCFG 0x06000600
63#define DDR_ODTMAP 0x00000001
Patrick Delaunay067a4c02019-04-10 14:09:24 +020064#define DDR_SCHED 0x00000C01
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010065#define DDR_SCHED1 0x00000000
66#define DDR_PERFHPR1 0x01000001
67#define DDR_PERFLPR1 0x08000200
68#define DDR_PERFWR1 0x08000400
69#define DDR_DBG0 0x00000000
70#define DDR_DBG1 0x00000000
71#define DDR_DBGCMD 0x00000000
72#define DDR_POISONCFG 0x00000000
73#define DDR_PCCFG 0x00000010
74#define DDR_PCFGR_0 0x00010000
75#define DDR_PCFGW_0 0x00000000
Patrick Delaunay067a4c02019-04-10 14:09:24 +020076#define DDR_PCFGQOS0_0 0x02100C03
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010077#define DDR_PCFGQOS1_0 0x00800100
Patrick Delaunay067a4c02019-04-10 14:09:24 +020078#define DDR_PCFGWQOS0_0 0x01100C03
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010079#define DDR_PCFGWQOS1_0 0x01000200
80#define DDR_PCFGR_1 0x00010000
81#define DDR_PCFGW_1 0x00000000
Patrick Delaunay067a4c02019-04-10 14:09:24 +020082#define DDR_PCFGQOS0_1 0x02100C03
83#define DDR_PCFGQOS1_1 0x00800040
84#define DDR_PCFGWQOS0_1 0x01100C03
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010085#define DDR_PCFGWQOS1_1 0x01000200
86#define DDR_PGCR 0x01442E02
87#define DDR_PTR0 0x0022AA5B
88#define DDR_PTR1 0x04841104
89#define DDR_PTR2 0x042DA068
90#define DDR_ACIOCR 0x10400812
91#define DDR_DXCCR 0x00000C40
Patrick Delaunaybe16c412019-07-30 19:16:13 +020092#define DDR_DSGCR 0xF200011F
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010093#define DDR_DCR 0x0000000B
94#define DDR_DTPR0 0x38D488D0
95#define DDR_DTPR1 0x098B00D8
96#define DDR_DTPR2 0x10023600
97#define DDR_MR0 0x00000840
98#define DDR_MR1 0x00000000
99#define DDR_MR2 0x00000208
100#define DDR_MR3 0x00000000
101#define DDR_ODTCR 0x00010000
Patrick Delaunay067a4c02019-04-10 14:09:24 +0200102#define DDR_ZQ0CR1 0x00000038
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100103#define DDR_DX0GCR 0x0000CE81
104#define DDR_DX0DLLCR 0x40000000
105#define DDR_DX0DQTR 0xFFFFFFFF
106#define DDR_DX0DQSTR 0x3DB02000
107#define DDR_DX1GCR 0x0000CE81
108#define DDR_DX1DLLCR 0x40000000
109#define DDR_DX1DQTR 0xFFFFFFFF
110#define DDR_DX1DQSTR 0x3DB02000
111#define DDR_DX2GCR 0x0000CE81
112#define DDR_DX2DLLCR 0x40000000
113#define DDR_DX2DQTR 0xFFFFFFFF
114#define DDR_DX2DQSTR 0x3DB02000
115#define DDR_DX3GCR 0x0000CE81
116#define DDR_DX3DLLCR 0x40000000
117#define DDR_DX3DQTR 0xFFFFFFFF
118#define DDR_DX3DQSTR 0x3DB02000
119
120#include "stm32mp15-ddr.dtsi"