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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +01002/*
3 * Copyright (C) 2004-2007 ARM Limited.
4 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Michal Simek966bfa72016-02-23 10:02:28 +01005 * Copyright (C) 2015 - 2016 Xilinx, Inc, Michal Simek
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +01006 *
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +01007 * As a special exception, if other files instantiate templates or use macros
8 * or inline functions from this file, or you compile this file and link it
9 * with other works to produce a work based on this file, this file does not
10 * by itself cause the resulting work to be covered by the GNU General Public
11 * License. However the source code for this file must still be made available
12 * in accordance with section (3) of the GNU General Public License.
13
14 * This exception does not invalidate any other reasons why a work based on
15 * this file might be covered by the GNU General Public License.
16 */
17
18#include <common.h>
Michal Simek966bfa72016-02-23 10:02:28 +010019#include <dm.h>
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +053020#include <serial.h>
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010021
Lokesh Vutla5f133bb2018-08-16 18:43:56 +053022#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7A) || defined(CONFIG_CPU_V7R)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010023/*
Alexander Merklefd602c52015-03-19 18:37:19 +010024 * ARMV6 & ARMV7
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010025 */
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020026#define DCC_RBIT (1 << 30)
27#define DCC_WBIT (1 << 29)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010028
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020029#define write_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010030 __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
31
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020032#define read_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010033 __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
34
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020035#define status_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010036 __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
37
Jean-Christophe PLAGNIOL-VILLARD65a76d42009-05-15 23:47:14 +020038#elif defined(CONFIG_CPU_XSCALE)
39/*
40 * XSCALE
41 */
42#define DCC_RBIT (1 << 31)
43#define DCC_WBIT (1 << 28)
44
45#define write_dcc(x) \
46 __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
47
48#define read_dcc(x) \
49 __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
50
51#define status_dcc(x) \
52 __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
53
Tom Rini6328f952021-12-17 18:08:39 -050054#elif defined(CONFIG_ARM64)
Siva Durga Prasad Paladugue05412f2015-05-29 09:54:37 +020055/*
56 * ARMV8
57 */
58#define DCC_RBIT (1 << 30)
59#define DCC_WBIT (1 << 29)
60
61#define write_dcc(x) \
62 __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x))
63
64#define read_dcc(x) \
65 __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x))
66
67#define status_dcc(x) \
68 __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x))
69
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020070#else
71#define DCC_RBIT (1 << 0)
72#define DCC_WBIT (1 << 1)
73
74#define write_dcc(x) \
75 __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
76
77#define read_dcc(x) \
78 __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
79
80#define status_dcc(x) \
81 __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
82
83#endif
84
85#define can_read_dcc(x) do { \
86 status_dcc(x); \
87 x &= DCC_RBIT; \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010088 } while (0);
89
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020090#define can_write_dcc(x) do { \
91 status_dcc(x); \
92 x &= DCC_WBIT; \
93 x = (x == 0); \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010094 } while (0);
95
96#define TIMEOUT_COUNT 0x4000000
97
Michal Simek966bfa72016-02-23 10:02:28 +010098static int arm_dcc_getc(struct udevice *dev)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010099{
100 int ch;
101 register unsigned int reg;
102
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200103 do {
104 can_read_dcc(reg);
105 } while (!reg);
106 read_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100107
108 return ch;
109}
110
Michal Simek966bfa72016-02-23 10:02:28 +0100111static int arm_dcc_putc(struct udevice *dev, char ch)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100112{
113 register unsigned int reg;
114 unsigned int timeout_count = TIMEOUT_COUNT;
115
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200116 while (--timeout_count) {
117 can_write_dcc(reg);
118 if (reg)
119 break;
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100120 }
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200121 if (timeout_count == 0)
Michal Simek966bfa72016-02-23 10:02:28 +0100122 return -EAGAIN;
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200123 else
124 write_dcc(ch);
Michal Simek966bfa72016-02-23 10:02:28 +0100125
126 return 0;
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100127}
128
Michal Simek966bfa72016-02-23 10:02:28 +0100129static int arm_dcc_pending(struct udevice *dev, bool input)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100130{
131 register unsigned int reg;
132
Michal Simek966bfa72016-02-23 10:02:28 +0100133 if (input) {
134 can_read_dcc(reg);
135 } else {
136 can_write_dcc(reg);
137 }
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100138
139 return reg;
140}
141
Michal Simek966bfa72016-02-23 10:02:28 +0100142static const struct dm_serial_ops arm_dcc_ops = {
143 .putc = arm_dcc_putc,
144 .pending = arm_dcc_pending,
145 .getc = arm_dcc_getc,
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530146};
147
Michal Simek966bfa72016-02-23 10:02:28 +0100148static const struct udevice_id arm_dcc_ids[] = {
149 { .compatible = "arm,dcc", },
150 { }
151};
152
153U_BOOT_DRIVER(serial_dcc) = {
154 .name = "arm_dcc",
155 .id = UCLASS_SERIAL,
156 .of_match = arm_dcc_ids,
157 .ops = &arm_dcc_ops,
Michal Simek966bfa72016-02-23 10:02:28 +0100158};
159
160#ifdef CONFIG_DEBUG_UART_ARM_DCC
161
162#include <debug_uart.h>
163
164static inline void _debug_uart_init(void)
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530165{
Jagannadha Sutradharudu Tekia168d3a2013-08-04 01:22:25 +0530166}
167
Michal Simek966bfa72016-02-23 10:02:28 +0100168static inline void _debug_uart_putc(int ch)
Michal Simeke70fb532013-01-22 23:40:06 +0000169{
Michal Simek966bfa72016-02-23 10:02:28 +0100170 arm_dcc_putc(NULL, ch);
Michal Simeke70fb532013-01-22 23:40:06 +0000171}
Michal Simek966bfa72016-02-23 10:02:28 +0100172
173DEBUG_UART_FUNCS
174#endif