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Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +01001/*
2 * Copyright (C) 2004-2007 ARM Limited.
3 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * As a special exception, if other files instantiate templates or use macros
19 * or inline functions from this file, or you compile this file and link it
20 * with other works to produce a work based on this file, this file does not
21 * by itself cause the resulting work to be covered by the GNU General Public
22 * License. However the source code for this file must still be made available
23 * in accordance with section (3) of the GNU General Public License.
24
25 * This exception does not invalidate any other reasons why a work based on
26 * this file might be covered by the GNU General Public License.
27 */
28
29#include <common.h>
30#include <devices.h>
31
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020032#if defined(CONFIG_CPU_V6)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010033/*
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020034 * ARMV6
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010035 */
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020036#define DCC_RBIT (1 << 30)
37#define DCC_WBIT (1 << 29)
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010038
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020039#define write_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010040 __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
41
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020042#define read_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010043 __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
44
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020045#define status_dcc(x) \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010046 __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
47
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020048#else
49#define DCC_RBIT (1 << 0)
50#define DCC_WBIT (1 << 1)
51
52#define write_dcc(x) \
53 __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
54
55#define read_dcc(x) \
56 __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
57
58#define status_dcc(x) \
59 __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
60
61#endif
62
63#define can_read_dcc(x) do { \
64 status_dcc(x); \
65 x &= DCC_RBIT; \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010066 } while (0);
67
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020068#define can_write_dcc(x) do { \
69 status_dcc(x); \
70 x &= DCC_WBIT; \
71 x = (x == 0); \
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010072 } while (0);
73
74#define TIMEOUT_COUNT 0x4000000
75
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010076#ifndef CONFIG_ARM_DCC_MULTI
77#define arm_dcc_init serial_init
78void serial_setbrg(void) {}
79#define arm_dcc_getc serial_getc
80#define arm_dcc_putc serial_putc
81#define arm_dcc_puts serial_puts
82#define arm_dcc_tstc serial_tstc
83#endif
84
85int arm_dcc_init(void)
86{
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010087 return 0;
88}
89
90int arm_dcc_getc(void)
91{
92 int ch;
93 register unsigned int reg;
94
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +020095 do {
96 can_read_dcc(reg);
97 } while (!reg);
98 read_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +010099
100 return ch;
101}
102
103void arm_dcc_putc(char ch)
104{
105 register unsigned int reg;
106 unsigned int timeout_count = TIMEOUT_COUNT;
107
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200108 while (--timeout_count) {
109 can_write_dcc(reg);
110 if (reg)
111 break;
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100112 }
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200113 if (timeout_count == 0)
114 return;
115 else
116 write_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100117}
118
119void arm_dcc_puts(const char *s)
120{
121 while (*s)
122 arm_dcc_putc(*s++);
123}
124
125int arm_dcc_tstc(void)
126{
127 register unsigned int reg;
128
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200129 can_read_dcc(reg);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100130
131 return reg;
132}
133
134#ifdef CONFIG_ARM_DCC_MULTI
135static device_t arm_dcc_dev;
136
137int drv_arm_dcc_init(void)
138{
139 int rc;
140
141 /* Device initialization */
142 memset(&arm_dcc_dev, 0, sizeof(arm_dcc_dev));
143
144 strcpy(arm_dcc_dev.name, "dcc");
145 arm_dcc_dev.ext = 0; /* No extensions */
146 arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT;
147 arm_dcc_dev.tstc = arm_dcc_tstc; /* 'tstc' function */
148 arm_dcc_dev.getc = arm_dcc_getc; /* 'getc' function */
149 arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */
150 arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */
151
Jean-Christophe PLAGNIOL-VILLARD66e8f9d2009-05-15 23:47:14 +0200152 return device_register(&arm_dcc_dev);
Jean-Christophe PLAGNIOL-VILLARD4f572892009-02-22 15:49:28 +0100153}
154#endif