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York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright (C) 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
York Sunf749db32014-06-23 15:15:56 -070010#define CONFIG_REMAKE_ELF
Mingkai Hu9f3183d2015-10-26 19:47:50 +080011#define CONFIG_FSL_LAYERSCAPE
York Sunf749db32014-06-23 15:15:56 -070012#define CONFIG_FSL_LSCH3
Mingkai Hu9f3183d2015-10-26 19:47:50 +080013#define CONFIG_MP
York Sunf749db32014-06-23 15:15:56 -070014#define CONFIG_GICV3
Bhupesh Sharma9c66ce62015-01-06 13:11:21 -080015#define CONFIG_FSL_TZPC_BP147
York Sunf749db32014-06-23 15:15:56 -070016
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053017#include <asm/arch/ls2080a_stream_id.h>
Mingkai Hu9f3183d2015-10-26 19:47:50 +080018#include <asm/arch/config.h>
Minghuan Lian31d34c62015-03-20 19:28:16 -070019#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
20#define CONFIG_SYS_HAS_SERDES
21#endif
22
Mingkai Hu9f3183d2015-10-26 19:47:50 +080023/* Link Definitions */
24#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
25
Bhupesh Sharma422cb082015-03-19 09:20:43 -070026/* We need architecture specific misc initializations */
27#define CONFIG_ARCH_MISC_INIT
28
Aneesh Bansalbcb55f62016-04-06 22:25:51 +053029#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
30
York Sunf749db32014-06-23 15:15:56 -070031/* Link Definitions */
Yuan Yaoa646f662016-06-08 18:25:00 +080032#ifndef CONFIG_QSPI_BOOT
Scott Woodb2d5ac52015-03-24 13:25:02 -070033#ifdef CONFIG_SPL
34#define CONFIG_SYS_TEXT_BASE 0x80400000
35#else
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070036#define CONFIG_SYS_TEXT_BASE 0x30100000
Scott Woodb2d5ac52015-03-24 13:25:02 -070037#endif
Yuan Yaoa646f662016-06-08 18:25:00 +080038#endif
York Sunf749db32014-06-23 15:15:56 -070039
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053040#ifdef CONFIG_EMU
York Sunf749db32014-06-23 15:15:56 -070041#define CONFIG_SYS_NO_FLASH
Prabhakar Kushwahae211c122014-07-16 09:21:12 +053042#endif
York Sunf749db32014-06-23 15:15:56 -070043
44#define CONFIG_SUPPORT_RAW_INITRD
45
46#define CONFIG_SKIP_LOWLEVEL_INIT
47#define CONFIG_BOARD_EARLY_INIT_F 1
48
Scott Woodb2d5ac52015-03-24 13:25:02 -070049#ifndef CONFIG_SPL
York Sunf749db32014-06-23 15:15:56 -070050#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Scott Woodb2d5ac52015-03-24 13:25:02 -070051#endif
York Sunf749db32014-06-23 15:15:56 -070052#ifndef CONFIG_SYS_FSL_DDR4
53#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
54#define CONFIG_SYS_DDR_RAW_TIMING
55#endif
York Sunf749db32014-06-23 15:15:56 -070056
57#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
58
Mingkai Hu9f3183d2015-10-26 19:47:50 +080059#define CONFIG_VERY_BIG_RAM
York Sunf749db32014-06-23 15:15:56 -070060#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
61#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
62#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
63#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sund9c68b12014-08-13 10:21:05 -070064#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
65
York Sun8bfa3012014-09-08 12:20:01 -070066/*
67 * SMP Definitinos
68 */
69#define CPU_RELEASE_ADDR secondary_boot_func
70
York Sund9c68b12014-08-13 10:21:05 -070071#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053072#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sund9c68b12014-08-13 10:21:05 -070073#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
74/*
75 * DDR controller use 0 as the base address for binding.
76 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
77 */
78#define CONFIG_SYS_DP_DDR_BASE_PHY 0
79#define CONFIG_DP_DDR_CTRL 2
80#define CONFIG_DP_DDR_NUM_CTRLS 1
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053081#endif
York Sunf749db32014-06-23 15:15:56 -070082
83/* Generic Timer Definitions */
York Sun207774b2015-03-20 19:28:08 -070084/*
85 * This is not an accurate number. It is used in start.S. The frequency
86 * will be udpated later when get_bus_freq(0) is available.
87 */
88#define COUNTER_FREQUENCY 25000000 /* 25MHz */
York Sunf749db32014-06-23 15:15:56 -070089
90/* Size of malloc() pool */
Prabhakar Kushwahaaa66acb2015-03-19 09:20:47 -070091#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
York Sunf749db32014-06-23 15:15:56 -070092
93/* I2C */
York Sunf749db32014-06-23 15:15:56 -070094#define CONFIG_SYS_I2C
95#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +020096#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
97#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -070098#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
99#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
York Sunf749db32014-06-23 15:15:56 -0700100
101/* Serial Port */
York Sun7288c2c2015-03-20 19:28:23 -0700102#define CONFIG_CONS_INDEX 1
York Sunf749db32014-06-23 15:15:56 -0700103#define CONFIG_SYS_NS16550_SERIAL
104#define CONFIG_SYS_NS16550_REG_SIZE 1
105#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
106
107#define CONFIG_BAUDRATE 115200
108#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
109
110/* IFC */
111#define CONFIG_FSL_IFC
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700112
York Sunf749db32014-06-23 15:15:56 -0700113/*
York Sun7288c2c2015-03-20 19:28:23 -0700114 * During booting, IFC is mapped at the region of 0x30000000.
115 * But this region is limited to 256MB. To accommodate NOR, promjet
116 * and FPGA. This region is divided as below:
117 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
118 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
119 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
120 *
121 * To accommodate bigger NOR flash and other devices, we will map IFC
122 * chip selects to as below:
123 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
124 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
125 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
126 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
127 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
128 *
129 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
York Sunf749db32014-06-23 15:15:56 -0700130 * CONFIG_SYS_FLASH_BASE has the final address (core view)
131 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
132 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
133 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
134 */
York Sun7288c2c2015-03-20 19:28:23 -0700135
York Sunf749db32014-06-23 15:15:56 -0700136#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
137#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
138#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
139
York Sun7288c2c2015-03-20 19:28:23 -0700140#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
141#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
142
York Sun7288c2c2015-03-20 19:28:23 -0700143#ifndef __ASSEMBLY__
144unsigned long long get_qixis_addr(void);
145#endif
146#define QIXIS_BASE get_qixis_addr()
147#define QIXIS_BASE_PHYS 0x20000000
148#define QIXIS_BASE_PHYS_EARLY 0xC000000
Yangbo Lu8b064602015-03-20 19:28:31 -0700149#define QIXIS_STAT_PRES1 0xb
150#define QIXIS_SDID_MASK 0x07
151#define QIXIS_ESDHC_NO_ADAPTER 0x7
York Sun7288c2c2015-03-20 19:28:23 -0700152
153#define CONFIG_SYS_NAND_BASE 0x530000000ULL
154#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530155
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700156/* Debug Server firmware */
Stuart Yoderb0ba9d42015-05-28 14:54:15 +0530157#define CONFIG_FSL_DEBUG_SERVER
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700158/* 2 sec timeout */
159#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
160
York Sunf749db32014-06-23 15:15:56 -0700161/* MC firmware */
162#define CONFIG_FSL_MC_ENET
York Sunf749db32014-06-23 15:15:56 -0700163/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
J. German Rivera125e2bc2015-03-20 19:28:18 -0700164#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
165#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
166#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
167#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
York Sun3c1d2182016-04-04 11:41:26 -0700168/* For LS2085A */
J. German Riverac1000c12015-07-02 11:28:58 +0530169#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
170#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
York Sunf749db32014-06-23 15:15:56 -0700171
Prabhakar Kushwaha5c055082015-06-02 10:55:52 +0530172/*
173 * Carve out a DDR region which will not be used by u-boot/Linux
174 *
175 * It will be used by MC and Debug Server. The MC region must be
176 * 512MB aligned, so the min size to hide is 512MB.
177 */
Bhupesh Sharma422cb082015-03-19 09:20:43 -0700178#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
York Sunc0492142015-12-07 11:08:58 -0800179#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024)
Pratiyush Mohan Srivastava52c11d42015-12-22 16:49:34 +0530180#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
York Sunc0492142015-12-07 11:08:58 -0800181#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
York Sunf749db32014-06-23 15:15:56 -0700182#endif
183
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700184/* PCIe */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400185#define CONFIG_PCIE1 /* PCIE controller 1 */
186#define CONFIG_PCIE2 /* PCIE controller 2 */
187#define CONFIG_PCIE3 /* PCIE controller 3 */
188#define CONFIG_PCIE4 /* PCIE controller 4 */
Prabhakar Kushwaha252b17e2015-05-28 14:53:58 +0530189#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
Prabhakar Kushwaha06b53012015-11-09 16:42:20 +0530190#ifdef CONFIG_LS2080A
Prabhakar Kushwaha44937212015-11-09 16:42:07 +0530191#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
Prabhakar Kushwaha06b53012015-11-09 16:42:20 +0530192#endif
193
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700194#define CONFIG_SYS_PCI_64BIT
195
196#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
197#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
198#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
199#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
200
201#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
202#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
203#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
204
205#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
206#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
207#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
208
York Sunf749db32014-06-23 15:15:56 -0700209/* Command line configuration */
York Sunf749db32014-06-23 15:15:56 -0700210#define CONFIG_CMD_ENV
York Sunf749db32014-06-23 15:15:56 -0700211
212/* Miscellaneous configurable options */
213#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
York Sun8bfa3012014-09-08 12:20:01 -0700214#define CONFIG_ARCH_EARLY_INIT_R
York Sunf749db32014-06-23 15:15:56 -0700215
216/* Physical Memory Map */
217/* fixme: these need to be checked against the board */
218#define CONFIG_CHIP_SELECTS_PER_CTRL 4
York Sunf749db32014-06-23 15:15:56 -0700219
York Sund9c68b12014-08-13 10:21:05 -0700220#define CONFIG_NR_DRAM_BANKS 3
York Sunf749db32014-06-23 15:15:56 -0700221
York Sunf749db32014-06-23 15:15:56 -0700222#define CONFIG_HWCONFIG
223#define HWCONFIG_BUFFER_SIZE 128
224
225#define CONFIG_DISPLAY_CPUINFO
226
Alison Wang1d3a76f2015-11-13 16:49:06 +0800227/* Allow to overwrite serial and ethaddr */
228#define CONFIG_ENV_OVERWRITE
229
York Sunf749db32014-06-23 15:15:56 -0700230/* Initial environment variables */
231#define CONFIG_EXTRA_ENV_SETTINGS \
232 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
233 "loadaddr=0x80100000\0" \
234 "kernel_addr=0x100000\0" \
235 "ramdisk_addr=0x800000\0" \
236 "ramdisk_size=0x2000000\0" \
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700237 "fdt_high=0xa0000000\0" \
York Sunf749db32014-06-23 15:15:56 -0700238 "initrd_high=0xffffffffffffffff\0" \
239 "kernel_start=0x581200000\0" \
Stuart Yoder052ddd52015-01-06 13:18:57 -0800240 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha97421bd2015-07-01 16:28:22 +0530241 "kernel_size=0x2800000\0" \
Prabhakar Kushwaha16ed8562016-02-03 17:03:51 +0530242 "console=ttyAMA0,38400n8\0" \
243 "mcinitcmd=fsl_mc start mc 0x580300000" \
244 " 0x580800000 \0"
York Sunf749db32014-06-23 15:15:56 -0700245
Prabhakar Kushwaha56cd0762015-08-02 09:11:44 +0530246#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
York Suned77b702016-02-29 15:58:20 -0800247 "earlycon=uart8250,mmio,0x21c0500 " \
Bhupesh Sharma34cc7542015-05-28 14:54:02 +0530248 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
Ashish Kumar9e71bb9c2016-01-14 18:12:29 +0530249 " hugepagesz=2m hugepages=256"
Prabhakar Kushwaha9f3e1b82016-02-03 17:04:07 +0530250#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
251 " cp.b $kernel_start $kernel_load" \
252 " $kernel_size && bootm $kernel_load"
York Sunf749db32014-06-23 15:15:56 -0700253
York Sunf749db32014-06-23 15:15:56 -0700254/* Monitor Command Prompt */
255#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
York Sunf749db32014-06-23 15:15:56 -0700256#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
257 sizeof(CONFIG_SYS_PROMPT) + 16)
York Sunf749db32014-06-23 15:15:56 -0700258#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
259#define CONFIG_SYS_LONGHELP
260#define CONFIG_CMDLINE_EDITING 1
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700261#define CONFIG_AUTO_COMPLETE
York Sunf749db32014-06-23 15:15:56 -0700262#define CONFIG_SYS_MAXARGS 64 /* max command args */
263
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700264#define CONFIG_PANIC_HANG /* do not reset board on panic */
265
Scott Woodb2d5ac52015-03-24 13:25:02 -0700266#define CONFIG_SPL_BSS_START_ADDR 0x80100000
267#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
268#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
269#define CONFIG_SPL_ENV_SUPPORT
270#define CONFIG_SPL_FRAMEWORK
271#define CONFIG_SPL_I2C_SUPPORT
272#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
273#define CONFIG_SPL_LIBCOMMON_SUPPORT
274#define CONFIG_SPL_LIBGENERIC_SUPPORT
275#define CONFIG_SPL_MAX_SIZE 0x16000
276#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
277#define CONFIG_SPL_NAND_SUPPORT
278#define CONFIG_SPL_SERIAL_SUPPORT
279#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
280#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
281#define CONFIG_SPL_TEXT_BASE 0x1800a000
282
283#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
284#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
285#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
286#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
Yuan Yao74cac002016-06-08 18:24:58 +0800287#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
Scott Woodb2d5ac52015-03-24 13:25:02 -0700288
Bhupesh Sharma34cc7542015-05-28 14:54:02 +0530289#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
290
Aneesh Bansalbcb55f62016-04-06 22:25:51 +0530291/* Hash command with SHA acceleration supported in hardware */
292#ifdef CONFIG_FSL_CAAM
293#define CONFIG_CMD_HASH
294#define CONFIG_SHA_HW_ACCEL
295#endif
296
York Sunf749db32014-06-23 15:15:56 -0700297#endif /* __LS2_COMMON_H */