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wdenk945af8d2003-07-16 21:53:01 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenk945af8d2003-07-16 21:53:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
wdenkcbd8a352004-02-24 02:00:03 +000032#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenk945af8d2003-07-16 21:53:01 +000033#define CONFIG_ICECUBE 1 /* ... on IceCube board */
34
wdenkb2001f22003-12-20 22:45:10 +000035#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk945af8d2003-07-16 21:53:01 +000036
37#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38#define BOOTFLAG_WARM 0x02 /* Software reboot */
39
Becky Bruce31d82672008-05-08 19:02:12 -050040#define CONFIG_HIGH_BATS 1 /* High BATs supported */
41
wdenk945af8d2003-07-16 21:53:01 +000042/*
43 * Serial console configuration
44 */
45#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
46#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
47#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
48
wdenk96e48cf2003-08-05 18:22:44 +000049
50#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
51/*
52 * PCI Mapping:
53 * 0x40000000 - 0x4fffffff - PCI Memory
54 * 0x50000000 - 0x50ffffff - PCI IO Space
55 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020056#define CONFIG_PCI
57
58#if defined(CONFIG_PCI)
wdenk96e48cf2003-08-05 18:22:44 +000059#define CONFIG_PCI_PNP 1
60#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050061#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenk96e48cf2003-08-05 18:22:44 +000062
63#define CONFIG_PCI_MEM_BUS 0x40000000
64#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65#define CONFIG_PCI_MEM_SIZE 0x10000000
66
67#define CONFIG_PCI_IO_BUS 0x50000000
68#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69#define CONFIG_PCI_IO_SIZE 0x01000000
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020070#endif
wdenk96e48cf2003-08-05 18:22:44 +000071
wdenke1599e82004-10-10 23:27:33 +000072#define CFG_XLB_PIPELINING 1
73
wdenk96e48cf2003-08-05 18:22:44 +000074#define CONFIG_NET_MULTI 1
Marian Balakowicz63ff0042005-10-28 22:30:33 +020075#define CONFIG_MII 1
wdenk96e48cf2003-08-05 18:22:44 +000076#define CONFIG_EEPRO100 1
77#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkf54ebdf2003-09-17 15:10:32 +000078#define CONFIG_NS8382X 1
wdenk96e48cf2003-08-05 18:22:44 +000079
Jon Loeliger11799432007-07-10 09:02:57 -050080#else
Marian Balakowicz63ff0042005-10-28 22:30:33 +020081#define CONFIG_MII 1
wdenk96e48cf2003-08-05 18:22:44 +000082#endif
83
wdenk132ba5f2004-02-27 08:20:54 +000084/* Partitions */
85#define CONFIG_MAC_PARTITION
86#define CONFIG_DOS_PARTITION
wdenk64f70be2004-09-28 20:34:50 +000087#define CONFIG_ISO_PARTITION
wdenk132ba5f2004-02-27 08:20:54 +000088
wdenk80885a92004-02-26 23:46:20 +000089/* USB */
Markus Klotzbuecherae3b7702006-11-27 11:46:46 +010090#define CONFIG_USB_OHCI_NEW
wdenk80885a92004-02-26 23:46:20 +000091#define CONFIG_USB_STORAGE
Markus Klotzbuecher72657572007-06-06 11:49:43 +020092#define CFG_OHCI_BE_CONTROLLER
Markus Klotzbuecherae3b7702006-11-27 11:46:46 +010093#undef CFG_USB_OHCI_BOARD_INIT
Markus Klotzbuecher72657572007-06-06 11:49:43 +020094#define CFG_USB_OHCI_CPU_INIT 1
Markus Klotzbuecherae3b7702006-11-27 11:46:46 +010095#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
96#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
97#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
98
wdenk414eec32005-04-02 22:37:54 +000099#define CONFIG_TIMESTAMP /* Print image info with timestamp */
100
wdenk945af8d2003-07-16 21:53:01 +0000101
Jon Loeliger348f2582007-07-08 13:46:18 -0500102/*
Jon Loeliger11799432007-07-10 09:02:57 -0500103 * BOOTP options
104 */
105#define CONFIG_BOOTP_BOOTFILESIZE
106#define CONFIG_BOOTP_BOOTPATH
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109
110
111/*
Jon Loeliger348f2582007-07-08 13:46:18 -0500112 * Command line configuration.
113 */
114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_EEPROM
117#define CONFIG_CMD_FAT
118#define CONFIG_CMD_I2C
119#define CONFIG_CMD_IDE
120#define CONFIG_CMD_NFS
121#define CONFIG_CMD_SNTP
Jon Loeliger11799432007-07-10 09:02:57 -0500122#define CONFIG_CMD_USB
123
124#if defined(CONFIG_PCI)
125#define CONFIG_CMD_PCI
126#endif
Jon Loeliger348f2582007-07-08 13:46:18 -0500127
wdenk945af8d2003-07-16 21:53:01 +0000128
wdenk5cf9da42003-11-07 13:42:26 +0000129#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
130# define CFG_LOWBOOT 1
131# define CFG_LOWBOOT16 1
132#endif
133#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100134#if defined(CONFIG_LITE5200B)
135# error CFG_LOWBOOT08 is incompatible with the Lite5200B
136#else
wdenk5cf9da42003-11-07 13:42:26 +0000137# define CFG_LOWBOOT 1
138# define CFG_LOWBOOT08 1
139#endif
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100140#endif
wdenk5cf9da42003-11-07 13:42:26 +0000141
wdenk945af8d2003-07-16 21:53:01 +0000142/*
143 * Autobooting
144 */
145#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk5cf9da42003-11-07 13:42:26 +0000146
147#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100148 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk5cf9da42003-11-07 13:42:26 +0000149 "echo"
150
151#undef CONFIG_BOOTARGS
152
153#define CONFIG_EXTRA_ENV_SETTINGS \
154 "netdev=eth0\0" \
155 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100156 "nfsroot=${serverip}:${rootpath}\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000157 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100158 "addip=setenv bootargs ${bootargs} " \
159 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
160 ":${hostname}:${netdev}:off panic=1\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000161 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100162 "bootm ${kernel_addr}\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000163 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100164 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
165 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000166 "rootpath=/opt/eldk/ppc_82xx\0" \
167 "bootfile=/tftpboot/MPC5200/uImage\0" \
168 ""
169
170#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk945af8d2003-07-16 21:53:01 +0000171
wdenkacf98e72003-09-16 11:39:10 +0000172#if defined(CONFIG_MPC5200)
173/*
174 * IPB Bus clocking configuration.
175 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100176#if defined(CONFIG_LITE5200B)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200177#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100178#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200179#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkacf98e72003-09-16 11:39:10 +0000180#endif
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100181#endif /* CONFIG_MPC5200 */
Stefan Roesee59581c2006-11-28 17:55:49 +0100182
183/* pass open firmware flat tree */
Grant Likelycf2817a2007-09-06 09:46:23 -0600184#define CONFIG_OF_LIBFDT 1
Stefan Roesee59581c2006-11-28 17:55:49 +0100185#define CONFIG_OF_BOARD_SETUP 1
186
Stefan Roesee59581c2006-11-28 17:55:49 +0100187#define OF_CPU "PowerPC,5200@0"
188#define OF_SOC "soc5200@f0000000"
Domen Puncer39f23cd2007-04-20 11:13:16 +0200189#define OF_TBCLK (bd->bi_busfreq / 4)
Stefan Roesee59581c2006-11-28 17:55:49 +0100190#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
191
wdenk945af8d2003-07-16 21:53:01 +0000192/*
193 * I2C configuration
194 */
wdenk531716e2003-09-13 19:01:12 +0000195#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
dzuab209d52003-09-30 14:08:43 +0000196#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
197
198#define CFG_I2C_SPEED 100000 /* 100 kHz */
wdenk531716e2003-09-13 19:01:12 +0000199#define CFG_I2C_SLAVE 0x7F
200
201/*
202 * EEPROM configuration
203 */
204#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
205#define CFG_I2C_EEPROM_ADDR_LEN 1
206#define CFG_EEPROM_PAGE_WRITE_BITS 3
dzuab209d52003-09-30 14:08:43 +0000207#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenk945af8d2003-07-16 21:53:01 +0000208
209/*
210 * Flash configuration
211 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100212#if defined(CONFIG_LITE5200B)
213#define CFG_FLASH_BASE 0xFE000000
214#define CFG_FLASH_SIZE 0x01000000
215#if !defined(CFG_LOWBOOT)
216#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
217#else /* CFG_LOWBOOT */
218#if defined(CFG_LOWBOOT08)
219# error CFG_LOWBOOT08 is incompatible with the Lite5200B
220#endif
221#if defined(CFG_LOWBOOT16)
222#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
223#endif
224#endif /* CFG_LOWBOOT */
225#else /* !CONFIG_LITE5200B (IceCube)*/
wdenk4b248f32004-03-14 16:51:43 +0000226#define CFG_FLASH_BASE 0xFF000000
wdenk7152b1d2003-09-05 23:19:14 +0000227#define CFG_FLASH_SIZE 0x01000000
wdenk5cf9da42003-11-07 13:42:26 +0000228#if !defined(CFG_LOWBOOT)
wdenk4b248f32004-03-14 16:51:43 +0000229#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
wdenk5cf9da42003-11-07 13:42:26 +0000230#else /* CFG_LOWBOOT */
231#if defined(CFG_LOWBOOT08)
wdenk4b248f32004-03-14 16:51:43 +0000232#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
wdenk7152b1d2003-09-05 23:19:14 +0000233#endif
wdenk5cf9da42003-11-07 13:42:26 +0000234#if defined(CFG_LOWBOOT16)
wdenk4b248f32004-03-14 16:51:43 +0000235#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
wdenk5cf9da42003-11-07 13:42:26 +0000236#endif
237#endif /* CFG_LOWBOOT */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100238#endif /* CONFIG_LITE5200B */
wdenk5cf9da42003-11-07 13:42:26 +0000239#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
wdenk7152b1d2003-09-05 23:19:14 +0000240
wdenk945af8d2003-07-16 21:53:01 +0000241#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
242
243#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
244#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
245
wdenk96e48cf2003-08-05 18:22:44 +0000246#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
wdenk945af8d2003-07-16 21:53:01 +0000247
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100248#if defined(CONFIG_LITE5200B)
249#define CFG_FLASH_CFI_DRIVER
250#define CFG_FLASH_CFI
251#define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
252#endif
253
wdenk945af8d2003-07-16 21:53:01 +0000254
255/*
256 * Environment settings
257 */
wdenk96e48cf2003-08-05 18:22:44 +0000258#define CFG_ENV_IS_IN_FLASH 1
wdenk945af8d2003-07-16 21:53:01 +0000259#define CFG_ENV_SIZE 0x10000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100260#if defined(CONFIG_LITE5200B)
261#define CFG_ENV_SECT_SIZE 0x20000
262#else
wdenk96e48cf2003-08-05 18:22:44 +0000263#define CFG_ENV_SECT_SIZE 0x10000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100264#endif
wdenk96e48cf2003-08-05 18:22:44 +0000265#define CONFIG_ENV_OVERWRITE 1
wdenk945af8d2003-07-16 21:53:01 +0000266
267/*
268 * Memory map
269 */
wdenk4b248f32004-03-14 16:51:43 +0000270#define CFG_MBAR 0xF0000000
wdenk945af8d2003-07-16 21:53:01 +0000271#define CFG_SDRAM_BASE 0x00000000
wdenke0ac62d2003-08-17 18:55:18 +0000272#define CFG_DEFAULT_MBAR 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000273
274/* Use SRAM until RAM will be available */
275#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
276#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
277
278
279#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
280#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
281#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
282
283#define CFG_MONITOR_BASE TEXT_BASE
284#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
wdenk96e48cf2003-08-05 18:22:44 +0000285# define CFG_RAMBOOT 1
wdenk945af8d2003-07-16 21:53:01 +0000286#endif
287
wdenkaf6d1df2003-12-03 23:53:42 +0000288#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk945af8d2003-07-16 21:53:01 +0000289#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
290#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
291
292/*
293 * Ethernet configuration
294 */
wdenkcbd8a352004-02-24 02:00:03 +0000295#define CONFIG_MPC5xxx_FEC 1
wdenk04a85b32004-04-15 18:22:41 +0000296/*
wdenk7e780362004-04-08 22:31:29 +0000297 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
298 */
299/* #define CONFIG_FEC_10MBIT 1 */
wdenkd4ca31c2004-01-02 14:00:00 +0000300#define CONFIG_PHY_ADDR 0x00
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100301#if defined(CONFIG_LITE5200B)
302#define CONFIG_FEC_MII100 1
303#endif
wdenk945af8d2003-07-16 21:53:01 +0000304
305/*
306 * GPIO configuration
307 */
wdenkb2001f22003-12-20 22:45:10 +0000308#ifdef CONFIG_MPC5200_DDR
309#define CFG_GPS_PORT_CONFIG 0x90000004
310#else
wdenkc3d98ed2003-09-18 20:10:12 +0000311#define CFG_GPS_PORT_CONFIG 0x10000004
wdenkb2001f22003-12-20 22:45:10 +0000312#endif
wdenk945af8d2003-07-16 21:53:01 +0000313
314/*
315 * Miscellaneous configurable options
316 */
317#define CFG_LONGHELP /* undef to save memory */
318#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500319#if defined(CONFIG_CMD_KGDB)
wdenk945af8d2003-07-16 21:53:01 +0000320#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
321#else
322#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
323#endif
324#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
325#define CFG_MAXARGS 16 /* max number of command args */
326#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
327
328#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
329#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
330
331#define CFG_LOAD_ADDR 0x100000 /* default load address */
332
333#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
334
Jon Loeliger348f2582007-07-08 13:46:18 -0500335#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
336#if defined(CONFIG_CMD_KGDB)
337# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
338#endif
339
wdenk945af8d2003-07-16 21:53:01 +0000340/*
341 * Various low-level settings
342 */
wdenkb13fb012003-10-30 21:49:38 +0000343#if defined(CONFIG_MPC5200)
wdenk4f7cb082003-09-11 23:06:34 +0000344#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
345#define CFG_HID0_FINAL HID0_ICE
wdenkb13fb012003-10-30 21:49:38 +0000346#else
347#define CFG_HID0_INIT 0
348#define CFG_HID0_FINAL 0
349#endif
wdenk945af8d2003-07-16 21:53:01 +0000350
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100351#if defined(CONFIG_LITE5200B)
352#define CFG_CS1_START CFG_FLASH_BASE
353#define CFG_CS1_SIZE CFG_FLASH_SIZE
354#define CFG_CS1_CFG 0x00047800
355#define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
356#define CFG_CS0_SIZE CFG_FLASH_SIZE
357#define CFG_BOOTCS_START CFG_CS0_START
358#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
359#define CFG_BOOTCS_CFG 0x00047800
360#else /* IceCube aka Lite5200 */
wdenkb2001f22003-12-20 22:45:10 +0000361#ifdef CONFIG_MPC5200_DDR
362
wdenk7e780362004-04-08 22:31:29 +0000363#define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
wdenkb2001f22003-12-20 22:45:10 +0000364#define CFG_BOOTCS_SIZE 0x00800000
365#define CFG_BOOTCS_CFG 0x00047801
wdenk7e780362004-04-08 22:31:29 +0000366#define CFG_CS1_START CFG_FLASH_BASE
wdenkb2001f22003-12-20 22:45:10 +0000367#define CFG_CS1_SIZE 0x00800000
368#define CFG_CS1_CFG 0x00047800
369
370#else /* !CONFIG_MPC5200_DDR */
371
wdenk945af8d2003-07-16 21:53:01 +0000372#define CFG_BOOTCS_START CFG_FLASH_BASE
373#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
374#define CFG_BOOTCS_CFG 0x00047801
375#define CFG_CS0_START CFG_FLASH_BASE
376#define CFG_CS0_SIZE CFG_FLASH_SIZE
377
wdenkb2001f22003-12-20 22:45:10 +0000378#endif /* CONFIG_MPC5200_DDR */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100379#endif /*CONFIG_LITE5200B */
wdenkb2001f22003-12-20 22:45:10 +0000380
wdenk945af8d2003-07-16 21:53:01 +0000381#define CFG_CS_BURST 0x00000000
382#define CFG_CS_DEADCYCLE 0x33333333
383
384#define CFG_RESET_ADDRESS 0xff000000
385
wdenk132ba5f2004-02-27 08:20:54 +0000386/*-----------------------------------------------------------------------
wdenkc3f9d492004-03-14 00:59:59 +0000387 * USB stuff
388 *-----------------------------------------------------------------------
389 */
wdenk4d13cba2004-03-14 14:09:05 +0000390#define CONFIG_USB_CLOCK 0x0001BBBB
391#define CONFIG_USB_CONFIG 0x00001000
wdenkc3f9d492004-03-14 00:59:59 +0000392
393/*-----------------------------------------------------------------------
wdenk132ba5f2004-02-27 08:20:54 +0000394 * IDE/ATA stuff Supports IDE harddisk
395 *-----------------------------------------------------------------------
396 */
397
398#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
399
400#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
401#undef CONFIG_IDE_LED /* LED for ide not supported */
402
403#define CONFIG_IDE_RESET /* reset for ide supported */
404#define CONFIG_IDE_PREINIT
405
406#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
wdenk64f70be2004-09-28 20:34:50 +0000407#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
wdenk132ba5f2004-02-27 08:20:54 +0000408
409#define CFG_ATA_IDE0_OFFSET 0x0000
410
411#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
412
413/* Offset for data I/O */
414#define CFG_ATA_DATA_OFFSET (0x0060)
415
416/* Offset for normal register accesses */
417#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
418
419/* Offset for alternate registers */
wdenk4b248f32004-03-14 16:51:43 +0000420#define CFG_ATA_ALT_OFFSET (0x005C)
wdenk132ba5f2004-02-27 08:20:54 +0000421
422/* Interval between registers */
423#define CFG_ATA_STRIDE 4
424
wdenk64f70be2004-09-28 20:34:50 +0000425#define CONFIG_ATAPI 1
426
wdenk945af8d2003-07-16 21:53:01 +0000427#endif /* __CONFIG_H */