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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
wdenkcbd8a352004-02-24 02:00:03 +000032#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenk945af8d2003-07-16 21:53:01 +000033#define CONFIG_ICECUBE 1 /* ... on IceCube board */
34
wdenkb2001f22003-12-20 22:45:10 +000035#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk945af8d2003-07-16 21:53:01 +000036
37#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38#define BOOTFLAG_WARM 0x02 /* Software reboot */
39
wdenk96e48cf2003-08-05 18:22:44 +000040#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
wdenk945af8d2003-07-16 21:53:01 +000041#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
43#endif
44
45/*
46 * Serial console configuration
47 */
48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51
wdenk96e48cf2003-08-05 18:22:44 +000052
53#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
54/*
55 * PCI Mapping:
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
58 */
59#define CONFIG_PCI 1
60#define CONFIG_PCI_PNP 1
61#define CONFIG_PCI_SCAN_SHOW 1
62
63#define CONFIG_PCI_MEM_BUS 0x40000000
64#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65#define CONFIG_PCI_MEM_SIZE 0x10000000
66
67#define CONFIG_PCI_IO_BUS 0x50000000
68#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69#define CONFIG_PCI_IO_SIZE 0x01000000
70
71#define CONFIG_NET_MULTI 1
72#define CONFIG_EEPRO100 1
73#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkf54ebdf2003-09-17 15:10:32 +000074#define CONFIG_NS8382X 1
wdenk96e48cf2003-08-05 18:22:44 +000075
76#define ADD_PCI_CMD CFG_CMD_PCI
77
78#else /* MPC5100 */
79
80#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
81
82#endif
83
wdenk945af8d2003-07-16 21:53:01 +000084/*
85 * Supported commands
86 */
wdenk531716e2003-09-13 19:01:12 +000087#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
88 CFG_CMD_I2C | CFG_CMD_EEPROM)
wdenk945af8d2003-07-16 21:53:01 +000089
90/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91#include <cmd_confdefs.h>
92
wdenk5cf9da42003-11-07 13:42:26 +000093#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
94# define CFG_LOWBOOT 1
95# define CFG_LOWBOOT16 1
96#endif
97#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
98# define CFG_LOWBOOT 1
99# define CFG_LOWBOOT08 1
100#endif
101
wdenk945af8d2003-07-16 21:53:01 +0000102/*
103 * Autobooting
104 */
105#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk5cf9da42003-11-07 13:42:26 +0000106
107#define CONFIG_PREBOOT "echo;" \
108 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
109 "echo"
110
111#undef CONFIG_BOOTARGS
112
113#define CONFIG_EXTRA_ENV_SETTINGS \
114 "netdev=eth0\0" \
115 "nfsargs=setenv bootargs root=/dev/nfs rw " \
116 "nfsroot=$(serverip):$(rootpath)\0" \
117 "ramargs=setenv bootargs root=/dev/ram rw\0" \
118 "addip=setenv bootargs $(bootargs) " \
119 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
120 ":$(hostname):$(netdev):off panic=1\0" \
121 "flash_nfs=run nfsargs addip;" \
122 "bootm $(kernel_addr)\0" \
123 "flash_self=run ramargs addip;" \
124 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
125 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
126 "rootpath=/opt/eldk/ppc_82xx\0" \
127 "bootfile=/tftpboot/MPC5200/uImage\0" \
128 ""
129
130#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk945af8d2003-07-16 21:53:01 +0000131
wdenkacf98e72003-09-16 11:39:10 +0000132#if defined(CONFIG_MPC5200)
133/*
134 * IPB Bus clocking configuration.
135 */
136#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
137#endif
wdenk945af8d2003-07-16 21:53:01 +0000138/*
139 * I2C configuration
140 */
wdenk531716e2003-09-13 19:01:12 +0000141#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
dzuab209d52003-09-30 14:08:43 +0000142#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
143
144#define CFG_I2C_SPEED 100000 /* 100 kHz */
wdenk531716e2003-09-13 19:01:12 +0000145#define CFG_I2C_SLAVE 0x7F
146
147/*
148 * EEPROM configuration
149 */
150#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
151#define CFG_I2C_EEPROM_ADDR_LEN 1
152#define CFG_EEPROM_PAGE_WRITE_BITS 3
dzuab209d52003-09-30 14:08:43 +0000153#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenk945af8d2003-07-16 21:53:01 +0000154
155/*
156 * Flash configuration
157 */
wdenk7152b1d2003-09-05 23:19:14 +0000158#define CFG_FLASH_BASE 0xff000000
159#define CFG_FLASH_SIZE 0x01000000
wdenk5cf9da42003-11-07 13:42:26 +0000160#if !defined(CFG_LOWBOOT)
wdenk7152b1d2003-09-05 23:19:14 +0000161#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000 + 0x800000)
wdenk5cf9da42003-11-07 13:42:26 +0000162#else /* CFG_LOWBOOT */
163#if defined(CFG_LOWBOOT08)
164#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000 + 0x800000)
wdenk7152b1d2003-09-05 23:19:14 +0000165#endif
wdenk5cf9da42003-11-07 13:42:26 +0000166#if defined(CFG_LOWBOOT16)
167#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000)
168#endif
169#endif /* CFG_LOWBOOT */
170#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
wdenk7152b1d2003-09-05 23:19:14 +0000171
wdenk945af8d2003-07-16 21:53:01 +0000172#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
173
174#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
175#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
176
wdenk96e48cf2003-08-05 18:22:44 +0000177#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
wdenk945af8d2003-07-16 21:53:01 +0000178
179
180/*
181 * Environment settings
182 */
wdenk96e48cf2003-08-05 18:22:44 +0000183#define CFG_ENV_IS_IN_FLASH 1
wdenk945af8d2003-07-16 21:53:01 +0000184#define CFG_ENV_SIZE 0x10000
wdenk96e48cf2003-08-05 18:22:44 +0000185#define CFG_ENV_SECT_SIZE 0x10000
186#define CONFIG_ENV_OVERWRITE 1
wdenk945af8d2003-07-16 21:53:01 +0000187
188/*
189 * Memory map
190 */
191#define CFG_MBAR 0xf0000000
192#define CFG_SDRAM_BASE 0x00000000
wdenke0ac62d2003-08-17 18:55:18 +0000193#define CFG_DEFAULT_MBAR 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000194
195/* Use SRAM until RAM will be available */
196#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
197#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
198
199
200#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
201#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
202#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
203
204#define CFG_MONITOR_BASE TEXT_BASE
205#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
wdenk96e48cf2003-08-05 18:22:44 +0000206# define CFG_RAMBOOT 1
wdenk945af8d2003-07-16 21:53:01 +0000207#endif
208
wdenkaf6d1df2003-12-03 23:53:42 +0000209#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk945af8d2003-07-16 21:53:01 +0000210#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
211#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
212
213/*
214 * Ethernet configuration
215 */
wdenkcbd8a352004-02-24 02:00:03 +0000216#define CONFIG_MPC5xxx_FEC 1
wdenk35656de2003-09-14 19:08:39 +0000217#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
wdenkd4ca31c2004-01-02 14:00:00 +0000218#define CONFIG_PHY_ADDR 0x00
wdenk945af8d2003-07-16 21:53:01 +0000219
220/*
221 * GPIO configuration
222 */
wdenkb2001f22003-12-20 22:45:10 +0000223#ifdef CONFIG_MPC5200_DDR
224#define CFG_GPS_PORT_CONFIG 0x90000004
225#else
wdenkc3d98ed2003-09-18 20:10:12 +0000226#define CFG_GPS_PORT_CONFIG 0x10000004
wdenkb2001f22003-12-20 22:45:10 +0000227#endif
wdenk945af8d2003-07-16 21:53:01 +0000228
229/*
230 * Miscellaneous configurable options
231 */
232#define CFG_LONGHELP /* undef to save memory */
233#define CFG_PROMPT "=> " /* Monitor Command Prompt */
234#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
235#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
236#else
237#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
238#endif
239#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
240#define CFG_MAXARGS 16 /* max number of command args */
241#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
242
243#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
244#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
245
246#define CFG_LOAD_ADDR 0x100000 /* default load address */
247
248#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
249
250/*
251 * Various low-level settings
252 */
wdenkb13fb012003-10-30 21:49:38 +0000253#if defined(CONFIG_MPC5200)
wdenk4f7cb082003-09-11 23:06:34 +0000254#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
255#define CFG_HID0_FINAL HID0_ICE
wdenkb13fb012003-10-30 21:49:38 +0000256#else
257#define CFG_HID0_INIT 0
258#define CFG_HID0_FINAL 0
259#endif
wdenk945af8d2003-07-16 21:53:01 +0000260
wdenkb2001f22003-12-20 22:45:10 +0000261#ifdef CONFIG_MPC5200_DDR
262
263#define CFG_BOOTCS_START 0xff800000
264#define CFG_BOOTCS_SIZE 0x00800000
265#define CFG_BOOTCS_CFG 0x00047801
266#define CFG_CS1_START 0xff000000
267#define CFG_CS1_SIZE 0x00800000
268#define CFG_CS1_CFG 0x00047800
269
270#else /* !CONFIG_MPC5200_DDR */
271
wdenk945af8d2003-07-16 21:53:01 +0000272#define CFG_BOOTCS_START CFG_FLASH_BASE
273#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
274#define CFG_BOOTCS_CFG 0x00047801
275#define CFG_CS0_START CFG_FLASH_BASE
276#define CFG_CS0_SIZE CFG_FLASH_SIZE
277
wdenkb2001f22003-12-20 22:45:10 +0000278#endif /* CONFIG_MPC5200_DDR */
279
wdenk945af8d2003-07-16 21:53:01 +0000280#define CFG_CS_BURST 0x00000000
281#define CFG_CS_DEADCYCLE 0x33333333
282
283#define CFG_RESET_ADDRESS 0xff000000
284
285#endif /* __CONFIG_H */