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Wolfgang Denkdc17fb62005-08-03 22:32:02 +02001/*
2 * (C) Copyright 2004
3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC8220 1
32#define CONFIG_YUKON8220 1 /* ... on Yukon board */
33
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0xfff00000
35
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050036#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050037#define CONFIG_HIGH_BATS 1 /* High BATs supported */
38
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020039/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
40 determine the CPU speed. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
42#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020043
44#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45#define BOOTFLAG_WARM 0x02 /* Software reboot */
46
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020047/*
48 * Serial console configuration
49 */
50
51/* Define this for PSC console
52#define CONFIG_PSC_CONSOLE 1
53*/
54
55#define CONFIG_EXTUART_CONSOLE 1
56
57#ifdef CONFIG_EXTUART_CONSOLE
58# define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059# define CONFIG_SYS_NS16550_SERIAL
60# define CONFIG_SYS_NS16550
61# define CONFIG_SYS_NS16550_REG_SIZE 1
62# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
63# define CONFIG_SYS_NS16550_CLK 18432000
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020064#endif
65
66#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
67
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020069
70#define CONFIG_TIMESTAMP /* Print image info with timestamp */
71
Jon Loeligera5562902007-07-08 15:31:57 -050072
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020073/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050074 * BOOTP options
75 */
76#define CONFIG_BOOTP_BOOTFILESIZE
77#define CONFIG_BOOTP_BOOTPATH
78#define CONFIG_BOOTP_GATEWAY
79#define CONFIG_BOOTP_HOSTNAME
80
81
82/*
Jon Loeligera5562902007-07-08 15:31:57 -050083 * Command line configuration.
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020084 */
Jon Loeligera5562902007-07-08 15:31:57 -050085#include <config_cmd_default.h>
86
87#define CONFIG_CMD_BOOTD
88#define CONFIG_CMD_CACHE
89#define CONFIG_CMD_DHCP
90#define CONFIG_CMD_DIAG
91#define CONFIG_CMD_EEPROM
92#define CONFIG_CMD_ELF
93#define CONFIG_CMD_I2C
94#define CONFIG_CMD_NET
95#define CONFIG_CMD_NFS
96#define CONFIG_CMD_PCI
97#define CONFIG_CMD_PING
98#define CONFIG_CMD_REGINFO
99#define CONFIG_CMD_SDRAM
100#define CONFIG_CMD_SNTP
101
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200102
103#define CONFIG_NET_MULTI
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200104#define CONFIG_MII
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200105
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200106/*
107 * Autobooting
108 */
109#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
110#define CONFIG_BOOTARGS "root=/dev/ram rw"
111#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
112#define CONFIG_HAS_ETH1
113#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
114#define CONFIG_IPADDR 192.162.1.2
115#define CONFIG_NETMASK 255.255.255.0
116#define CONFIG_SERVERIP 192.162.1.1
117#define CONFIG_GATEWAYIP 192.162.1.1
118#define CONFIG_HOSTNAME yukon
119#define CONFIG_OVERWRITE_ETHADDR_ONCE
120
121
122/*
123 * I2C configuration
124 */
125#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_I2C_MODULE 1
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
129#define CONFIG_SYS_I2C_SLAVE 0x7F
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200130
131/*
132 * EEPROM configuration
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
135#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
136#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
137#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200138/*
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200139#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200140#define CONFIG_ENV_OFFSET 0
141#define CONFIG_ENV_SIZE 256
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200142*/
143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200145 else undefined it will boot from Intel Strata flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_AMD_BOOT 1
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200147
148/*
149 * Flexbus Chipselect configuration
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#if defined (CONFIG_SYS_AMD_BOOT)
152#define CONFIG_SYS_CS0_BASE 0xfff0
153#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
154#define CONFIG_SYS_CS0_CTRL 0x003f0d40
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_CS1_BASE 0xfe00
157#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
158#define CONFIG_SYS_CS1_CTRL 0x003f1540
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200159#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_CS0_BASE 0xff00
161#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
162#define CONFIG_SYS_CS0_CTRL 0x003f1540
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CS1_BASE 0xfe08
165#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
166#define CONFIG_SYS_CS1_CTRL 0x003f0d40
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200167#endif
168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_CS2_BASE 0xf100
170#define CONFIG_SYS_CS2_MASK 0x00040000
171#define CONFIG_SYS_CS2_CTRL 0x003f1140
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_CS3_BASE 0xf200
174#define CONFIG_SYS_CS3_MASK 0x00040000
175#define CONFIG_SYS_CS3_CTRL 0x003f1100
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200176
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
179#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#if defined (CONFIG_SYS_AMD_BOOT)
182#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
183#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
184#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200185#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
187#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
188#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200189#endif
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
192#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200193
194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
196#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
199#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
200#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
201#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
202#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200203
204#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
205#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_CHECKSUM
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200208/*
209 * Environment settings
210 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200211#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#if defined (CONFIG_SYS_AMD_BOOT)
213#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200214#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
215#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200217#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
218#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200219#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200221#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
222#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200224#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
225#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200226#endif
227
228#define CONFIG_ENV_OVERWRITE 1
229
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200230#if defined CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200231#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200232#undef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200233#elif defined CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200234#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200235#undef CONFIG_ENV_IS_IN_EEPROM
236#elif defined CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200237#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200238#undef CONFIG_ENV_IS_IN_FLASH
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200239#endif
240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#ifndef CONFIG_SYS_JFFS2_FIRST_SECTOR
242#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200243#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#ifndef CONFIG_SYS_JFFS2_FIRST_BANK
245#define CONFIG_SYS_JFFS2_FIRST_BANK 0
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200246#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#ifndef CONFIG_SYS_JFFS2_NUM_BANKS
248#define CONFIG_SYS_JFFS2_NUM_BANKS 1
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200249#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_JFFS2_LAST_BANK (CONFIG_SYS_JFFS2_FIRST_BANK + CONFIG_SYS_JFFS2_NUM_BANKS - 1)
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200251
252/*
253 * Memory map
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_MBAR 0xF0000000
256#define CONFIG_SYS_SDRAM_BASE 0x00000000
257#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
258#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
259#define CONFIG_SYS_SRAM_SIZE 0x8000
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200260
261/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
263#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
266#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
267#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200268
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200269#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
271# define CONFIG_SYS_RAMBOOT 1
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200272#endif
273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
275#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
276#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200277
278/* SDRAM configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
280#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
281#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
282#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200283
284/* SDRAM drive strength register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200286 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
287 (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
288 (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
289 (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
290
291/*
292 * Ethernet configuration
293 */
294#define CONFIG_MPC8220_FEC 1
295#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
296#define CONFIG_PHY_ADDR 0x18
297
298
299/*
300 * Miscellaneous configurable options
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_LONGHELP /* undef to save memory */
303#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5562902007-07-08 15:31:57 -0500304#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200306#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200308#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
310#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
311#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
314#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
Jon Loeligera5562902007-07-08 15:31:57 -0500321#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligera5562902007-07-08 15:31:57 -0500323#endif
324
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200325/*
326 * Various low-level settings
327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
329#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200330
331#endif /* __CONFIG_H */