blob: 37ef1058f90dad6b6517032664b8f37880ef0ebf [file] [log] [blame]
Wolfgang Denkdc17fb62005-08-03 22:32:02 +02001/*
2 * (C) Copyright 2004
3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC8220 1
32#define CONFIG_YUKON8220 1 /* ... on Yukon board */
33
34/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
35 determine the CPU speed. */
36#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
37#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
38
39#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
40#define BOOTFLAG_WARM 0x02 /* Software reboot */
41
42#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
43
44#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
45# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
46#endif
47
48/*
49 * Serial console configuration
50 */
51
52/* Define this for PSC console
53#define CONFIG_PSC_CONSOLE 1
54*/
55
56#define CONFIG_EXTUART_CONSOLE 1
57
58#ifdef CONFIG_EXTUART_CONSOLE
59# define CONFIG_CONS_INDEX 1
60# define CFG_NS16550_SERIAL
61# define CFG_NS16550
62# define CFG_NS16550_REG_SIZE 1
63# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
64# define CFG_NS16550_CLK 18432000
65#endif
66
67#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
68
69#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
70
71#define CONFIG_TIMESTAMP /* Print image info with timestamp */
72
73/*
74 * Supported commands
75 */
76#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
77 CFG_CMD_BOOTD | \
78 CFG_CMD_CACHE | \
79 CFG_CMD_DHCP | \
80 CFG_CMD_DIAG | \
81 CFG_CMD_EEPROM | \
82 CFG_CMD_ELF | \
83 CFG_CMD_I2C | \
84 CFG_CMD_NET | \
85 CFG_CMD_NFS | \
86 CFG_CMD_PCI | \
87 CFG_CMD_PING | \
88 CFG_CMD_REGINFO | \
89 CFG_CMD_SDRAM | \
90 CFG_CMD_SNTP )
91
92#define CONFIG_NET_MULTI
Marian Balakowicz63ff0042005-10-28 22:30:33 +020093#define CONFIG_MII
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020094
95/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
96#include <cmd_confdefs.h>
97
98/*
99 * Autobooting
100 */
101#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
102#define CONFIG_BOOTARGS "root=/dev/ram rw"
103#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
104#define CONFIG_HAS_ETH1
105#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
106#define CONFIG_IPADDR 192.162.1.2
107#define CONFIG_NETMASK 255.255.255.0
108#define CONFIG_SERVERIP 192.162.1.1
109#define CONFIG_GATEWAYIP 192.162.1.1
110#define CONFIG_HOSTNAME yukon
111#define CONFIG_OVERWRITE_ETHADDR_ONCE
112
113
114/*
115 * I2C configuration
116 */
117#define CONFIG_HARD_I2C 1
118#define CFG_I2C_MODULE 1
119
120#define CFG_I2C_SPEED 100000 /* 100 kHz */
121#define CFG_I2C_SLAVE 0x7F
122
123/*
124 * EEPROM configuration
125 */
126#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
127#define CFG_I2C_EEPROM_ADDR_LEN 1
128#define CFG_EEPROM_PAGE_WRITE_BITS 3
129#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
130/*
131#define CFG_ENV_IS_IN_EEPROM 1
132#define CFG_ENV_OFFSET 0
133#define CFG_ENV_SIZE 256
134*/
135
136/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
137 else undefined it will boot from Intel Strata flash */
138#define CFG_AMD_BOOT 1
139
140/*
141 * Flexbus Chipselect configuration
142 */
143#if defined (CFG_AMD_BOOT)
144#define CFG_CS0_BASE 0xfff0
145#define CFG_CS0_MASK 0x00080000 /* 512 KB */
146#define CFG_CS0_CTRL 0x003f0d40
147
148#define CFG_CS1_BASE 0xfe00
149#define CFG_CS1_MASK 0x01000000 /* 16 MB */
150#define CFG_CS1_CTRL 0x003f1540
151#else
152#define CFG_CS0_BASE 0xff00
153#define CFG_CS0_MASK 0x01000000 /* 16 MB */
154#define CFG_CS0_CTRL 0x003f1540
155
156#define CFG_CS1_BASE 0xfe08
157#define CFG_CS1_MASK 0x00080000 /* 512 KB */
158#define CFG_CS1_CTRL 0x003f0d40
159#endif
160
161#define CFG_CS2_BASE 0xf100
162#define CFG_CS2_MASK 0x00040000
163#define CFG_CS2_CTRL 0x003f1140
164
165#define CFG_CS3_BASE 0xf200
166#define CFG_CS3_MASK 0x00040000
167#define CFG_CS3_CTRL 0x003f1100
168
169
170#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
171#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
172
173#if defined (CFG_AMD_BOOT)
174#define CFG_AMD_BASE CFG_FLASH0_BASE
175#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
176#define CFG_FLASH_BASE CFG_AMD_BASE
177#else
178#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
179#define CFG_AMD_BASE CFG_FLASH1_BASE
180#define CFG_FLASH_BASE CFG_INTEL_BASE
181#endif
182
183#define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
184#define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
185
186
187#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
188#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
189
190#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
191#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
192#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
193#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
194#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
195
196#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
197#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
198
199#define CFG_FLASH_CHECKSUM
200/*
201 * Environment settings
202 */
203#define CFG_ENV_IS_IN_FLASH 1
204#if defined (CFG_AMD_BOOT)
205#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
206#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
207#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
208#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
209#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
210#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
211#else
212#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
213#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
214#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
215#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
216#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
217#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
218#endif
219
220#define CONFIG_ENV_OVERWRITE 1
221
222#if defined CFG_ENV_IS_IN_FLASH
223#undef CFG_ENV_IS_IN_NVRAM
224#undef CFG_ENV_IS_IN_EEPROM
225#elif defined CFG_ENV_IS_IN_NVRAM
226#undef CFG_ENV_IS_IN_FLASH
227#undef CFG_ENV_IS_IN_EEPROM
228#elif defined CFG_ENV_IS_IN_EEPROM
229#undef CFG_ENV_IS_IN_NVRAM
230#undef CFG_ENV_IS_IN_FLASH
231#endif
232
233#ifndef CFG_JFFS2_FIRST_SECTOR
234#define CFG_JFFS2_FIRST_SECTOR 0
235#endif
236#ifndef CFG_JFFS2_FIRST_BANK
237#define CFG_JFFS2_FIRST_BANK 0
238#endif
239#ifndef CFG_JFFS2_NUM_BANKS
240#define CFG_JFFS2_NUM_BANKS 1
241#endif
242#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
243
244/*
245 * Memory map
246 */
247#define CFG_MBAR 0xF0000000
248#define CFG_SDRAM_BASE 0x00000000
249#define CFG_DEFAULT_MBAR 0x80000000
250#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
251#define CFG_SRAM_SIZE 0x8000
252
253/* Use SRAM until RAM will be available */
254#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
255#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
256
257#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
258#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
259#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
260
261#define CFG_MONITOR_BASE TEXT_BASE
262#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
263# define CFG_RAMBOOT 1
264#endif
265
266#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
267#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
268#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
269
270/* SDRAM configuration */
271#define CFG_SDRAM_TOTAL_BANKS 2
272#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
273#define CFG_SDRAM_SPD_SIZE 0x40
274#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
275
276/* SDRAM drive strength register */
277#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
278 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
279 (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
280 (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
281 (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
282
283/*
284 * Ethernet configuration
285 */
286#define CONFIG_MPC8220_FEC 1
287#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
288#define CONFIG_PHY_ADDR 0x18
289
290
291/*
292 * Miscellaneous configurable options
293 */
294#define CFG_LONGHELP /* undef to save memory */
295#define CFG_PROMPT "=> " /* Monitor Command Prompt */
296#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
297#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
298#else
299#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
300#endif
301#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
302#define CFG_MAXARGS 16 /* max number of command args */
303#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
304
305#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
306#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
307
308#define CFG_LOAD_ADDR 0x100000 /* default load address */
309
310#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
311
312/*
313 * Various low-level settings
314 */
315#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
316#define CFG_HID0_FINAL HID0_ICE
317
318#endif /* __CONFIG_H */