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gerrit.cesnet.cz / github / trini / u-boot / 292260ca21723ab78d23fa2cf6b574cf17778991 / . / arch / powerpc / include / asm / fsl_serdes.h
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Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]1/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]5 */
6
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]7#ifndef __FSL_SERDES_H
8#define __FSL_SERDES_H
9
10#include <config.h>
11
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]12enum srds_prtcl {
13 NONE = 0,
14 PCIE1,
15 PCIE2,
16 PCIE3,
17 PCIE4,
18 SATA1,
19 SATA2,
20 SRIO1,
21 SRIO2,
Kumar Gala34a82582010-07-12 22:51:29 -0500[diff] [blame]22 SGMII_FM1_DTSEC1,
23 SGMII_FM1_DTSEC2,
24 SGMII_FM1_DTSEC3,
25 SGMII_FM1_DTSEC4,
26 SGMII_FM1_DTSEC5,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]27 SGMII_FM1_DTSEC6,
28 SGMII_FM1_DTSEC9,
29 SGMII_FM1_DTSEC10,
Kumar Gala34a82582010-07-12 22:51:29 -0500[diff] [blame]30 SGMII_FM2_DTSEC1,
31 SGMII_FM2_DTSEC2,
32 SGMII_FM2_DTSEC3,
33 SGMII_FM2_DTSEC4,
Timur Tabi99abf7d2012-08-14 06:47:21 +0000[diff] [blame]34 SGMII_FM2_DTSEC5,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]35 SGMII_FM2_DTSEC6,
36 SGMII_FM2_DTSEC9,
37 SGMII_FM2_DTSEC10,
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]38 SGMII_TSEC1,
39 SGMII_TSEC2,
40 SGMII_TSEC3,
41 SGMII_TSEC4,
42 XAUI_FM1,
43 XAUI_FM2,
44 AURORA,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]45 CPRI1,
46 CPRI2,
47 CPRI3,
48 CPRI4,
49 CPRI5,
50 CPRI6,
51 CPRI7,
52 CPRI8,
53 XAUI_FM1_MAC9,
54 XAUI_FM1_MAC10,
55 XAUI_FM2_MAC9,
56 XAUI_FM2_MAC10,
57 HIGIG_FM1_MAC9,
58 HIGIG_FM1_MAC10,
59 HIGIG_FM2_MAC9,
60 HIGIG_FM2_MAC10,
61 QSGMII_FM1_A, /* A indicates MACs 1-4 */
62 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
63 QSGMII_FM2_A,
64 QSGMII_FM2_B,
Shengzhou Liu82a55c12013-11-22 17:39:09 +0800[diff] [blame]65 XFI_FM1_MAC1,
66 XFI_FM1_MAC2,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]67 XFI_FM1_MAC9,
68 XFI_FM1_MAC10,
69 XFI_FM2_MAC9,
70 XFI_FM2_MAC10,
71 INTERLAKEN,
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]72 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]73 QSGMII_SW1_B,
Shengzhou Liuc35f8692014-10-23 17:20:57 +0800[diff] [blame]74 SGMII_2500_FM1_DTSEC1,
75 SGMII_2500_FM1_DTSEC2,
76 SGMII_2500_FM1_DTSEC3,
77 SGMII_2500_FM1_DTSEC4,
78 SGMII_2500_FM1_DTSEC5,
79 SGMII_2500_FM1_DTSEC6,
80 SGMII_2500_FM1_DTSEC9,
81 SGMII_2500_FM1_DTSEC10,
82 SGMII_2500_FM2_DTSEC1,
83 SGMII_2500_FM2_DTSEC2,
84 SGMII_2500_FM2_DTSEC3,
85 SGMII_2500_FM2_DTSEC4,
86 SGMII_2500_FM2_DTSEC5,
87 SGMII_2500_FM2_DTSEC6,
88 SGMII_2500_FM2_DTSEC9,
89 SGMII_2500_FM2_DTSEC10,
Codrin Ciubotariuc2a61cd2015-01-12 14:08:31 +0200[diff] [blame]90 SGMII_SW1_MAC1,
91 SGMII_SW1_MAC2,
92 SGMII_SW1_MAC3,
93 SGMII_SW1_MAC4,
94 SGMII_SW1_MAC5,
95 SGMII_SW1_MAC6,
Codrin Ciubotariu7d33a872015-01-12 14:08:30 +0200[diff] [blame]96 SERDES_PRCTL_COUNT /* Keep this item the last one */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]97};
98
99enum srds {
100 FSL_SRDS_1 = 0,
101 FSL_SRDS_2 = 1,
102 FSL_SRDS_3 = 2,
103 FSL_SRDS_4 = 3,
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]104};
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]105
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]106int is_serdes_configured(enum srds_prtcl device);
Kumar Galaaf025062010-05-22 13:21:39 -0500[diff] [blame]107void fsl_serdes_init(void);
Valentin Longchamp935b4022013-10-18 11:47:23 +0200[diff] [blame]108const char *serdes_clock_to_string(u32 clock);
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]109
Emil Medve3d28c5c2010-08-31 22:57:36 -0500[diff] [blame]110#ifdef CONFIG_FSL_CORENET
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]111#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
112int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
Shaveta Leekha40f398a2013-07-02 14:42:07 +0530[diff] [blame]113enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]114#else
Emil Medve3d28c5c2010-08-31 22:57:36 -0500[diff] [blame]115int serdes_get_first_lane(enum srds_prtcl device);
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]116#endif
Emil Medvedf8af0b2010-08-31 22:57:38 -0500[diff] [blame]117#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
118void serdes_reset_rx(enum srds_prtcl device);
119#endif
Emil Medve3d28c5c2010-08-31 22:57:36 -0500[diff] [blame]120#endif
121
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]122#endif /* __FSL_SERDES_H */