| David Feng | 0ae7653 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 1 | #ifndef __GIC_H__ |
| 2 | #define __GIC_H__ |
| Andre Przywara | 16212b5 | 2013-09-19 18:06:41 +0200 | [diff] [blame] | 3 | |
| David Feng | 0ae7653 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 4 | /* Register offsets for the ARM generic interrupt controller (GIC) */ |
| Andre Przywara | 16212b5 | 2013-09-19 18:06:41 +0200 | [diff] [blame] | 5 | |
| 6 | #define GIC_DIST_OFFSET 0x1000 |
| Andre Przywara | 16212b5 | 2013-09-19 18:06:41 +0200 | [diff] [blame] | 7 | #define GIC_CPU_OFFSET_A9 0x0100 |
| 8 | #define GIC_CPU_OFFSET_A15 0x2000 |
| David Feng | 0ae7653 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 9 | |
| 10 | /* Distributor Registers */ |
| 11 | #define GICD_CTLR 0x0000 |
| 12 | #define GICD_TYPER 0x0004 |
| 13 | #define GICD_IIDR 0x0008 |
| 14 | #define GICD_STATUSR 0x0010 |
| 15 | #define GICD_SETSPI_NSR 0x0040 |
| 16 | #define GICD_CLRSPI_NSR 0x0048 |
| 17 | #define GICD_SETSPI_SR 0x0050 |
| 18 | #define GICD_CLRSPI_SR 0x0058 |
| 19 | #define GICD_SEIR 0x0068 |
| 20 | #define GICD_IGROUPRn 0x0080 |
| 21 | #define GICD_ISENABLERn 0x0100 |
| 22 | #define GICD_ICENABLERn 0x0180 |
| 23 | #define GICD_ISPENDRn 0x0200 |
| 24 | #define GICD_ICPENDRn 0x0280 |
| 25 | #define GICD_ISACTIVERn 0x0300 |
| 26 | #define GICD_ICACTIVERn 0x0380 |
| 27 | #define GICD_IPRIORITYRn 0x0400 |
| 28 | #define GICD_ITARGETSRn 0x0800 |
| 29 | #define GICD_ICFGR 0x0c00 |
| 30 | #define GICD_IGROUPMODRn 0x0d00 |
| 31 | #define GICD_NSACRn 0x0e00 |
| 32 | #define GICD_SGIR 0x0f00 |
| 33 | #define GICD_CPENDSGIRn 0x0f10 |
| 34 | #define GICD_SPENDSGIRn 0x0f20 |
| 35 | #define GICD_IROUTERn 0x6000 |
| 36 | |
| 37 | /* Cpu Interface Memory Mapped Registers */ |
| Andre Przywara | 16212b5 | 2013-09-19 18:06:41 +0200 | [diff] [blame] | 38 | #define GICC_CTLR 0x0000 |
| 39 | #define GICC_PMR 0x0004 |
| David Feng | 0ae7653 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 40 | #define GICC_BPR 0x0008 |
| Andre Przywara | ba6a169 | 2013-09-19 18:06:44 +0200 | [diff] [blame] | 41 | #define GICC_IAR 0x000C |
| 42 | #define GICC_EOIR 0x0010 |
| David Feng | 0ae7653 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 43 | #define GICC_RPR 0x0014 |
| 44 | #define GICC_HPPIR 0x0018 |
| 45 | #define GICC_ABPR 0x001c |
| 46 | #define GICC_AIAR 0x0020 |
| 47 | #define GICC_AEOIR 0x0024 |
| 48 | #define GICC_AHPPIR 0x0028 |
| 49 | #define GICC_APRn 0x00d0 |
| 50 | #define GICC_NSAPRn 0x00e0 |
| 51 | #define GICC_IIDR 0x00fc |
| 52 | #define GICC_DIR 0x1000 |
| Andre Przywara | 16212b5 | 2013-09-19 18:06:41 +0200 | [diff] [blame] | 53 | |
| David Feng | 0ae7653 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 54 | #endif /* __GIC_H__ */ |