| Andre Przywara | 16212b5 | 2013-09-19 18:06:41 +0200 | [diff] [blame^] | 1 | #ifndef __GIC_V2_H__ |
| 2 | #define __GIC_V2_H__ | ||||
| 3 | |||||
| 4 | /* register offsets for the ARM generic interrupt controller (GIC) */ | ||||
| 5 | |||||
| 6 | #define GIC_DIST_OFFSET 0x1000 | ||||
| 7 | #define GICD_CTLR 0x0000 | ||||
| 8 | #define GICD_TYPER 0x0004 | ||||
| 9 | #define GICD_IGROUPRn 0x0080 | ||||
| 10 | #define GICD_SGIR 0x0F00 | ||||
| 11 | |||||
| 12 | #define GIC_CPU_OFFSET_A9 0x0100 | ||||
| 13 | #define GIC_CPU_OFFSET_A15 0x2000 | ||||
| 14 | #define GICC_CTLR 0x0000 | ||||
| 15 | #define GICC_PMR 0x0004 | ||||
| 16 | |||||
| 17 | #endif | ||||