Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Clock initialization for OMAP4 |
| 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Aneesh V <aneesh@ti.com> |
| 9 | * |
| 10 | * Based on previous work by: |
| 11 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 12 | * Rajendra Nayak <rnayak@ti.com> |
| 13 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 14 | * SPDX-License-Identifier: GPL-2.0+ |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 15 | */ |
| 16 | #include <common.h> |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 17 | #include <i2c.h> |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 18 | #include <asm/omap_common.h> |
Sanjeev Premi | 3b690eb | 2011-09-08 10:48:39 -0400 | [diff] [blame] | 19 | #include <asm/gpio.h> |
Lokesh Vutla | af1d002 | 2013-05-30 02:54:32 +0000 | [diff] [blame] | 20 | #include <asm/arch/clock.h> |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 21 | #include <asm/arch/sys_proto.h> |
| 22 | #include <asm/utils.h> |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 23 | #include <asm/omap_gpio.h> |
Lokesh Vutla | 9ca8bfe | 2013-02-04 04:21:59 +0000 | [diff] [blame] | 24 | #include <asm/emif.h> |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 25 | |
| 26 | #ifndef CONFIG_SPL_BUILD |
| 27 | /* |
| 28 | * printing to console doesn't work unless |
| 29 | * this code is executed from SPL |
| 30 | */ |
| 31 | #define printf(fmt, args...) |
| 32 | #define puts(s) |
| 33 | #endif |
| 34 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 35 | const u32 sys_clk_array[8] = { |
| 36 | 12000000, /* 12 MHz */ |
Lokesh Vutla | 97405d8 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 37 | 20000000, /* 20 MHz */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 38 | 16800000, /* 16.8 MHz */ |
| 39 | 19200000, /* 19.2 MHz */ |
| 40 | 26000000, /* 26 MHz */ |
| 41 | 27000000, /* 27 MHz */ |
| 42 | 38400000, /* 38.4 MHz */ |
| 43 | }; |
| 44 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 45 | static inline u32 __get_sys_clk_index(void) |
| 46 | { |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 47 | s8 ind; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 48 | /* |
| 49 | * For ES1 the ROM code calibration of sys clock is not reliable |
| 50 | * due to hw issue. So, use hard-coded value. If this value is not |
| 51 | * correct for any board over-ride this function in board file |
| 52 | * From ES2.0 onwards you will get this information from |
| 53 | * CM_SYS_CLKSEL |
| 54 | */ |
| 55 | if (omap_revision() == OMAP4430_ES1_0) |
| 56 | ind = OMAP_SYS_CLK_IND_38_4_MHZ; |
| 57 | else { |
| 58 | /* SYS_CLKSEL - 1 to match the dpll param array indices */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 59 | ind = (readl((*prcm)->cm_sys_clksel) & |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 60 | CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; |
| 61 | } |
| 62 | return ind; |
| 63 | } |
| 64 | |
| 65 | u32 get_sys_clk_index(void) |
| 66 | __attribute__ ((weak, alias("__get_sys_clk_index"))); |
| 67 | |
| 68 | u32 get_sys_clk_freq(void) |
| 69 | { |
| 70 | u8 index = get_sys_clk_index(); |
| 71 | return sys_clk_array[index]; |
| 72 | } |
| 73 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 74 | void setup_post_dividers(u32 const base, const struct dpll_params *params) |
| 75 | { |
| 76 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 77 | |
| 78 | /* Setup post-dividers */ |
| 79 | if (params->m2 >= 0) |
| 80 | writel(params->m2, &dpll_regs->cm_div_m2_dpll); |
| 81 | if (params->m3 >= 0) |
| 82 | writel(params->m3, &dpll_regs->cm_div_m3_dpll); |
| 83 | if (params->m4_h11 >= 0) |
| 84 | writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll); |
| 85 | if (params->m5_h12 >= 0) |
| 86 | writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll); |
| 87 | if (params->m6_h13 >= 0) |
| 88 | writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); |
| 89 | if (params->m7_h14 >= 0) |
| 90 | writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); |
SRICHARAN R | 47abc3d | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 91 | if (params->h21 >= 0) |
| 92 | writel(params->h21, &dpll_regs->cm_div_h21_dpll); |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 93 | if (params->h22 >= 0) |
| 94 | writel(params->h22, &dpll_regs->cm_div_h22_dpll); |
| 95 | if (params->h23 >= 0) |
| 96 | writel(params->h23, &dpll_regs->cm_div_h23_dpll); |
SRICHARAN R | 47abc3d | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 97 | if (params->h24 >= 0) |
| 98 | writel(params->h24, &dpll_regs->cm_div_h24_dpll); |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 99 | } |
| 100 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 101 | static inline void do_bypass_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 102 | { |
| 103 | struct dpll_regs *dpll_regs = (struct dpll_regs *)base; |
| 104 | |
| 105 | clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
| 106 | CM_CLKMODE_DPLL_DPLL_EN_MASK, |
| 107 | DPLL_EN_FAST_RELOCK_BYPASS << |
| 108 | CM_CLKMODE_DPLL_EN_SHIFT); |
| 109 | } |
| 110 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 111 | static inline void wait_for_bypass(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 112 | { |
| 113 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 114 | |
| 115 | if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, |
| 116 | LDELAY)) { |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 117 | printf("Bypassing DPLL failed %x\n", base); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 118 | } |
| 119 | } |
| 120 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 121 | static inline void do_lock_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 122 | { |
| 123 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 124 | |
| 125 | clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
| 126 | CM_CLKMODE_DPLL_DPLL_EN_MASK, |
| 127 | DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); |
| 128 | } |
| 129 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 130 | static inline void wait_for_lock(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 131 | { |
| 132 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 133 | |
| 134 | if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, |
| 135 | &dpll_regs->cm_idlest_dpll, LDELAY)) { |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 136 | printf("DPLL locking failed for %x\n", base); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 137 | hang(); |
| 138 | } |
| 139 | } |
| 140 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 141 | inline u32 check_for_lock(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 142 | { |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 143 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 144 | u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; |
| 145 | |
| 146 | return lock; |
| 147 | } |
| 148 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 149 | const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) |
| 150 | { |
| 151 | u32 sysclk_ind = get_sys_clk_index(); |
| 152 | return &dpll_data->mpu[sysclk_ind]; |
| 153 | } |
| 154 | |
| 155 | const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) |
| 156 | { |
| 157 | u32 sysclk_ind = get_sys_clk_index(); |
| 158 | return &dpll_data->core[sysclk_ind]; |
| 159 | } |
| 160 | |
| 161 | const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) |
| 162 | { |
| 163 | u32 sysclk_ind = get_sys_clk_index(); |
| 164 | return &dpll_data->per[sysclk_ind]; |
| 165 | } |
| 166 | |
| 167 | const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) |
| 168 | { |
| 169 | u32 sysclk_ind = get_sys_clk_index(); |
| 170 | return &dpll_data->iva[sysclk_ind]; |
| 171 | } |
| 172 | |
| 173 | const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) |
| 174 | { |
| 175 | u32 sysclk_ind = get_sys_clk_index(); |
| 176 | return &dpll_data->usb[sysclk_ind]; |
| 177 | } |
| 178 | |
| 179 | const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) |
| 180 | { |
| 181 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 182 | u32 sysclk_ind = get_sys_clk_index(); |
| 183 | return &dpll_data->abe[sysclk_ind]; |
| 184 | #else |
| 185 | return dpll_data->abe; |
| 186 | #endif |
| 187 | } |
| 188 | |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 189 | static const struct dpll_params *get_ddr_dpll_params |
| 190 | (struct dplls const *dpll_data) |
| 191 | { |
| 192 | u32 sysclk_ind = get_sys_clk_index(); |
| 193 | |
| 194 | if (!dpll_data->ddr) |
| 195 | return NULL; |
| 196 | return &dpll_data->ddr[sysclk_ind]; |
| 197 | } |
| 198 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 199 | static void do_setup_dpll(u32 const base, const struct dpll_params *params, |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 200 | u8 lock, char *dpll) |
| 201 | { |
| 202 | u32 temp, M, N; |
| 203 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 204 | |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 205 | if (!params) |
| 206 | return; |
| 207 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 208 | temp = readl(&dpll_regs->cm_clksel_dpll); |
| 209 | |
| 210 | if (check_for_lock(base)) { |
| 211 | /* |
| 212 | * The Dpll has already been locked by rom code using CH. |
| 213 | * Check if M,N are matching with Ideal nominal opp values. |
| 214 | * If matches, skip the rest otherwise relock. |
| 215 | */ |
| 216 | M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT; |
| 217 | N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT; |
| 218 | if ((M != (params->m)) || (N != (params->n))) { |
| 219 | debug("\n %s Dpll locked, but not for ideal M = %d," |
| 220 | "N = %d values, current values are M = %d," |
| 221 | "N= %d" , dpll, params->m, params->n, |
| 222 | M, N); |
| 223 | } else { |
| 224 | /* Dpll locked with ideal values for nominal opps. */ |
| 225 | debug("\n %s Dpll already locked with ideal" |
| 226 | "nominal opp values", dpll); |
| 227 | goto setup_post_dividers; |
| 228 | } |
| 229 | } |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 230 | |
| 231 | bypass_dpll(base); |
| 232 | |
| 233 | /* Set M & N */ |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 234 | temp &= ~CM_CLKSEL_DPLL_M_MASK; |
| 235 | temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; |
| 236 | |
| 237 | temp &= ~CM_CLKSEL_DPLL_N_MASK; |
| 238 | temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; |
| 239 | |
| 240 | writel(temp, &dpll_regs->cm_clksel_dpll); |
| 241 | |
| 242 | /* Lock */ |
| 243 | if (lock) |
| 244 | do_lock_dpll(base); |
| 245 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 246 | setup_post_dividers: |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 247 | setup_post_dividers(base, params); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 248 | |
| 249 | /* Wait till the DPLL locks */ |
| 250 | if (lock) |
| 251 | wait_for_lock(base); |
| 252 | } |
| 253 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 254 | u32 omap_ddr_clk(void) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 255 | { |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 256 | u32 ddr_clk, sys_clk_khz, omap_rev, divider; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 257 | const struct dpll_params *core_dpll_params; |
| 258 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 259 | omap_rev = omap_revision(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 260 | sys_clk_khz = get_sys_clk_freq() / 1000; |
| 261 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 262 | core_dpll_params = get_core_dpll_params(*dplls_data); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 263 | |
| 264 | debug("sys_clk %d\n ", sys_clk_khz * 1000); |
| 265 | |
| 266 | /* Find Core DPLL locked frequency first */ |
| 267 | ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / |
| 268 | (core_dpll_params->n + 1); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 269 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 270 | if (omap_rev < OMAP5430_ES1_0) { |
| 271 | /* |
| 272 | * DDR frequency is PHY_ROOT_CLK/2 |
| 273 | * PHY_ROOT_CLK = Fdpll/2/M2 |
| 274 | */ |
| 275 | divider = 4; |
| 276 | } else { |
| 277 | /* |
| 278 | * DDR frequency is PHY_ROOT_CLK |
| 279 | * PHY_ROOT_CLK = Fdpll/2/M2 |
| 280 | */ |
| 281 | divider = 2; |
| 282 | } |
| 283 | |
| 284 | ddr_clk = ddr_clk / divider / core_dpll_params->m2; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 285 | ddr_clk *= 1000; /* convert to Hz */ |
| 286 | debug("ddr_clk %d\n ", ddr_clk); |
| 287 | |
| 288 | return ddr_clk; |
| 289 | } |
| 290 | |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 291 | /* |
| 292 | * Lock MPU dpll |
| 293 | * |
| 294 | * Resulting MPU frequencies: |
| 295 | * 4430 ES1.0 : 600 MHz |
| 296 | * 4430 ES2.x : 792 MHz (OPP Turbo) |
| 297 | * 4460 : 920 MHz (OPP Turbo) - DCC disabled |
| 298 | */ |
| 299 | void configure_mpu_dpll(void) |
| 300 | { |
| 301 | const struct dpll_params *params; |
| 302 | struct dpll_regs *mpu_dpll_regs; |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 303 | u32 omap_rev; |
| 304 | omap_rev = omap_revision(); |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 305 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 306 | /* |
| 307 | * DCC and clock divider settings for 4460. |
| 308 | * DCC is required, if more than a certain frequency is required. |
| 309 | * For, 4460 > 1GHZ. |
| 310 | * 5430 > 1.4GHZ. |
| 311 | */ |
| 312 | if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 313 | mpu_dpll_regs = |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 314 | (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); |
| 315 | bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); |
| 316 | clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 317 | MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 318 | setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 319 | MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); |
| 320 | clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, |
| 321 | CM_CLKSEL_DCC_EN_MASK); |
| 322 | } |
| 323 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 324 | params = get_mpu_dpll_params(*dplls_data); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 325 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 326 | do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 327 | debug("MPU DPLL locked\n"); |
| 328 | } |
| 329 | |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 330 | #ifdef CONFIG_USB_EHCI_OMAP |
| 331 | static void setup_usb_dpll(void) |
| 332 | { |
| 333 | const struct dpll_params *params; |
| 334 | u32 sys_clk_khz, sd_div, num, den; |
| 335 | |
| 336 | sys_clk_khz = get_sys_clk_freq() / 1000; |
| 337 | /* |
| 338 | * USB: |
| 339 | * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction |
| 340 | * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) |
| 341 | * - where CLKINP is sys_clk in MHz |
| 342 | * Use CLKINP in KHz and adjust the denominator accordingly so |
| 343 | * that we have enough accuracy and at the same time no overflow |
| 344 | */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 345 | params = get_usb_dpll_params(*dplls_data); |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 346 | num = params->m * sys_clk_khz; |
| 347 | den = (params->n + 1) * 250 * 1000; |
| 348 | num += den - 1; |
| 349 | sd_div = num / den; |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 350 | clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 351 | CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, |
| 352 | sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); |
| 353 | |
| 354 | /* Now setup the dpll with the regular function */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 355 | do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 356 | } |
| 357 | #endif |
| 358 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 359 | static void setup_dplls(void) |
| 360 | { |
Anatolij Gustschin | 164a750 | 2011-12-03 06:46:14 +0000 | [diff] [blame] | 361 | u32 temp; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 362 | const struct dpll_params *params; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 363 | |
Anatolij Gustschin | 164a750 | 2011-12-03 06:46:14 +0000 | [diff] [blame] | 364 | debug("setup_dplls\n"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 365 | |
| 366 | /* CORE dpll */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 367 | params = get_core_dpll_params(*dplls_data); /* default - safest */ |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 368 | /* |
| 369 | * Do not lock the core DPLL now. Just set it up. |
| 370 | * Core DPLL will be locked after setting up EMIF |
| 371 | * using the FREQ_UPDATE method(freq_update_core()) |
| 372 | */ |
Lokesh Vutla | 9ca8bfe | 2013-02-04 04:21:59 +0000 | [diff] [blame] | 373 | if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 374 | do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, |
Lokesh Vutla | 753bae8 | 2012-05-22 00:03:26 +0000 | [diff] [blame] | 375 | DPLL_NO_LOCK, "core"); |
| 376 | else |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 377 | do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, |
Lokesh Vutla | 753bae8 | 2012-05-22 00:03:26 +0000 | [diff] [blame] | 378 | DPLL_LOCK, "core"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 379 | /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ |
| 380 | temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | |
| 381 | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | |
| 382 | (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 383 | writel(temp, (*prcm)->cm_clksel_core); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 384 | debug("Core DPLL configured\n"); |
| 385 | |
| 386 | /* lock PER dpll */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 387 | params = get_per_dpll_params(*dplls_data); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 388 | do_setup_dpll((*prcm)->cm_clkmode_dpll_per, |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 389 | params, DPLL_LOCK, "per"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 390 | debug("PER DPLL locked\n"); |
| 391 | |
| 392 | /* MPU dpll */ |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 393 | configure_mpu_dpll(); |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 394 | |
| 395 | #ifdef CONFIG_USB_EHCI_OMAP |
| 396 | setup_usb_dpll(); |
| 397 | #endif |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 398 | params = get_ddr_dpll_params(*dplls_data); |
| 399 | do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, |
| 400 | params, DPLL_LOCK, "ddr"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 401 | } |
| 402 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 403 | #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 404 | static void setup_non_essential_dplls(void) |
| 405 | { |
Anatolij Gustschin | 27ac87d | 2012-03-27 23:13:43 +0000 | [diff] [blame] | 406 | u32 abe_ref_clk; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 407 | const struct dpll_params *params; |
| 408 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 409 | /* IVA */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 410 | clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 411 | CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); |
| 412 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 413 | params = get_iva_dpll_params(*dplls_data); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 414 | do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 415 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 416 | /* Configure ABE dpll */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 417 | params = get_abe_dpll_params(*dplls_data); |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 418 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 419 | abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; |
Lokesh Vutla | 97405d8 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 420 | |
| 421 | if (omap_revision() == DRA752_ES1_0) |
| 422 | /* Select the sys clk for dpll_abe */ |
| 423 | clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, |
| 424 | CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, |
| 425 | CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 426 | #else |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 427 | abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; |
| 428 | /* |
| 429 | * We need to enable some additional options to achieve |
| 430 | * 196.608MHz from 32768 Hz |
| 431 | */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 432 | setbits_le32((*prcm)->cm_clkmode_dpll_abe, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 433 | CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| |
| 434 | CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| |
| 435 | CM_CLKMODE_DPLL_LPMODE_EN_MASK| |
| 436 | CM_CLKMODE_DPLL_REGM4XEN_MASK); |
| 437 | /* Spend 4 REFCLK cycles at each stage */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 438 | clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 439 | CM_CLKMODE_DPLL_RAMP_RATE_MASK, |
| 440 | 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); |
| 441 | #endif |
| 442 | |
| 443 | /* Select the right reference clk */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 444 | clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 445 | CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, |
| 446 | abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); |
| 447 | /* Lock the dpll */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 448 | do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 449 | } |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 450 | #endif |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 451 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 452 | u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 453 | { |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 454 | u32 offset_code; |
Nishanth Menon | 3acb553 | 2012-03-01 14:17:38 +0000 | [diff] [blame] | 455 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 456 | volt_offset -= pmic->base_offset; |
Nishanth Menon | 3acb553 | 2012-03-01 14:17:38 +0000 | [diff] [blame] | 457 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 458 | offset_code = (volt_offset + pmic->step - 1) / pmic->step; |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 459 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 460 | /* |
| 461 | * Offset codes 1-6 all give the base voltage in Palmas |
| 462 | * Offset code 0 switches OFF the SMPS |
| 463 | */ |
| 464 | return offset_code + pmic->start_code; |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 465 | } |
| 466 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 467 | void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 468 | { |
Nishanth Menon | a78274b | 2012-03-01 14:17:37 +0000 | [diff] [blame] | 469 | u32 offset_code; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 470 | u32 offset = volt_mv; |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 471 | int ret = 0; |
| 472 | |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 473 | if (!volt_mv) |
| 474 | return; |
| 475 | |
Lokesh Vutla | 4ca94d8 | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 476 | pmic->pmic_bus_init(); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 477 | /* See if we can first get the GPIO if needed */ |
| 478 | if (pmic->gpio_en) |
| 479 | ret = gpio_request(pmic->gpio, "PMIC_GPIO"); |
| 480 | |
| 481 | if (ret < 0) { |
| 482 | printf("%s: gpio %d request failed %d\n", __func__, |
| 483 | pmic->gpio, ret); |
| 484 | return; |
| 485 | } |
| 486 | |
| 487 | /* Pull the GPIO low to select SET0 register, while we program SET1 */ |
| 488 | if (pmic->gpio_en) |
| 489 | gpio_direction_output(pmic->gpio, 0); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 490 | |
| 491 | /* convert to uV for better accuracy in the calculations */ |
| 492 | offset *= 1000; |
| 493 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 494 | offset_code = get_offset_code(offset, pmic); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 495 | |
| 496 | debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, |
| 497 | offset_code); |
SRICHARAN R | 8de17f4 | 2012-03-12 02:25:38 +0000 | [diff] [blame] | 498 | |
Lokesh Vutla | 4ca94d8 | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 499 | if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 500 | printf("Scaling voltage failed for 0x%x\n", vcore_reg); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 501 | |
| 502 | if (pmic->gpio_en) |
| 503 | gpio_direction_output(pmic->gpio, 1); |
| 504 | } |
| 505 | |
Nishanth Menon | 18c9d55 | 2013-05-30 03:19:31 +0000 | [diff] [blame] | 506 | static u32 optimize_vcore_voltage(struct volts const *v) |
| 507 | { |
| 508 | u32 val; |
| 509 | if (!v->value) |
| 510 | return 0; |
| 511 | if (!v->efuse.reg) |
| 512 | return v->value; |
| 513 | |
| 514 | switch (v->efuse.reg_bits) { |
| 515 | case 16: |
| 516 | val = readw(v->efuse.reg); |
| 517 | break; |
| 518 | case 32: |
| 519 | val = readl(v->efuse.reg); |
| 520 | break; |
| 521 | default: |
| 522 | printf("Error: efuse 0x%08x bits=%d unknown\n", |
| 523 | v->efuse.reg, v->efuse.reg_bits); |
| 524 | return v->value; |
| 525 | } |
| 526 | |
| 527 | if (!val) { |
| 528 | printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", |
| 529 | v->efuse.reg, v->efuse.reg_bits, v->value); |
| 530 | return v->value; |
| 531 | } |
| 532 | |
| 533 | debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", |
| 534 | __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); |
| 535 | return val; |
| 536 | } |
| 537 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 538 | /* |
| 539 | * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
| 540 | * We set the maximum voltages allowed here because Smart-Reflex is not |
| 541 | * enabled in bootloader. Voltage initialization in the kernel will set |
| 542 | * these to the nominal values after enabling Smart-Reflex |
| 543 | */ |
| 544 | void scale_vcores(struct vcores_data const *vcores) |
| 545 | { |
Nishanth Menon | 18c9d55 | 2013-05-30 03:19:31 +0000 | [diff] [blame] | 546 | u32 val; |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 547 | |
Nishanth Menon | 18c9d55 | 2013-05-30 03:19:31 +0000 | [diff] [blame] | 548 | val = optimize_vcore_voltage(&vcores->core); |
| 549 | do_scale_vcore(vcores->core.addr, val, vcores->core.pmic); |
| 550 | |
| 551 | val = optimize_vcore_voltage(&vcores->mpu); |
| 552 | do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 553 | |
Andrii Tseglytskyi | e69c585 | 2013-05-20 22:42:09 +0000 | [diff] [blame] | 554 | /* Configure MPU ABB LDO after scale */ |
| 555 | abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, |
| 556 | (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, |
| 557 | (*prcm)->prm_abbldo_mpu_setup, |
| 558 | (*prcm)->prm_abbldo_mpu_ctrl, |
| 559 | (*prcm)->prm_irqstatus_mpu_2, |
| 560 | OMAP_ABB_MPU_TXDONE_MASK, |
| 561 | OMAP_ABB_FAST_OPP); |
| 562 | |
Nishanth Menon | 18c9d55 | 2013-05-30 03:19:31 +0000 | [diff] [blame] | 563 | val = optimize_vcore_voltage(&vcores->mm); |
| 564 | do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 565 | |
Nishanth Menon | 18c9d55 | 2013-05-30 03:19:31 +0000 | [diff] [blame] | 566 | val = optimize_vcore_voltage(&vcores->gpu); |
| 567 | do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic); |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 568 | |
Nishanth Menon | 18c9d55 | 2013-05-30 03:19:31 +0000 | [diff] [blame] | 569 | val = optimize_vcore_voltage(&vcores->eve); |
| 570 | do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic); |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 571 | |
Nishanth Menon | 18c9d55 | 2013-05-30 03:19:31 +0000 | [diff] [blame] | 572 | val = optimize_vcore_voltage(&vcores->iva); |
| 573 | do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 574 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 575 | if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { |
| 576 | /* Configure LDO SRAM "magic" bits */ |
| 577 | writel(2, (*prcm)->prm_sldo_core_setup); |
| 578 | writel(2, (*prcm)->prm_sldo_mpu_setup); |
| 579 | writel(2, (*prcm)->prm_sldo_mm_setup); |
| 580 | } |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 581 | } |
| 582 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 583 | static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 584 | { |
| 585 | clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, |
| 586 | enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 587 | debug("Enable clock domain - %x\n", clkctrl_reg); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 588 | } |
| 589 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 590 | static inline void wait_for_clk_enable(u32 clkctrl_addr) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 591 | { |
| 592 | u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; |
| 593 | u32 bound = LDELAY; |
| 594 | |
| 595 | while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || |
| 596 | (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { |
| 597 | |
| 598 | clkctrl = readl(clkctrl_addr); |
| 599 | idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> |
| 600 | MODULE_CLKCTRL_IDLEST_SHIFT; |
| 601 | if (--bound == 0) { |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 602 | printf("Clock enable failed for 0x%x idlest 0x%x\n", |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 603 | clkctrl_addr, clkctrl); |
| 604 | return; |
| 605 | } |
| 606 | } |
| 607 | } |
| 608 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 609 | static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 610 | u32 wait_for_enable) |
| 611 | { |
| 612 | clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, |
| 613 | enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 614 | debug("Enable clock module - %x\n", clkctrl_addr); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 615 | if (wait_for_enable) |
| 616 | wait_for_clk_enable(clkctrl_addr); |
| 617 | } |
| 618 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 619 | void freq_update_core(void) |
| 620 | { |
| 621 | u32 freq_config1 = 0; |
| 622 | const struct dpll_params *core_dpll_params; |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 623 | u32 omap_rev = omap_revision(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 624 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 625 | core_dpll_params = get_core_dpll_params(*dplls_data); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 626 | /* Put EMIF clock domain in sw wakeup mode */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 627 | enable_clock_domain((*prcm)->cm_memif_clkstctrl, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 628 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 629 | wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); |
| 630 | wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 631 | |
| 632 | freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | |
| 633 | SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; |
| 634 | |
| 635 | freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & |
| 636 | SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; |
| 637 | |
| 638 | freq_config1 |= (core_dpll_params->m2 << |
| 639 | SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & |
| 640 | SHADOW_FREQ_CONFIG1_M2_DIV_MASK; |
| 641 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 642 | writel(freq_config1, (*prcm)->cm_shadow_freq_config1); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 643 | if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 644 | (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 645 | puts("FREQ UPDATE procedure failed!!"); |
| 646 | hang(); |
| 647 | } |
| 648 | |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 649 | /* |
| 650 | * Putting EMIF in HW_AUTO is seen to be causing issues with |
Lubomir Popov | a8f408a | 2013-04-04 05:51:45 +0000 | [diff] [blame] | 651 | * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 652 | * in OMAP5430 ES1.0 silicon |
| 653 | */ |
| 654 | if (omap_rev != OMAP5430_ES1_0) { |
| 655 | /* Put EMIF clock domain back in hw auto mode */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 656 | enable_clock_domain((*prcm)->cm_memif_clkstctrl, |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 657 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 658 | wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); |
| 659 | wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 660 | } |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 661 | } |
| 662 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 663 | void bypass_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 664 | { |
| 665 | do_bypass_dpll(base); |
| 666 | wait_for_bypass(base); |
| 667 | } |
| 668 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 669 | void lock_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 670 | { |
| 671 | do_lock_dpll(base); |
| 672 | wait_for_lock(base); |
| 673 | } |
| 674 | |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 675 | void setup_clocks_for_console(void) |
| 676 | { |
| 677 | /* Do not add any spl_debug prints in this function */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 678 | clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 679 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP << |
| 680 | CD_CLKCTRL_CLKTRCTRL_SHIFT); |
| 681 | |
| 682 | /* Enable all UARTs - console will be on one of them */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 683 | clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 684 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 685 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 686 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 687 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 688 | clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 689 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 690 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 691 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 692 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 693 | clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 694 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 695 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 696 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 697 | |
Lubomir Popov | a8f408a | 2013-04-04 05:51:45 +0000 | [diff] [blame] | 698 | clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 699 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 700 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 701 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 702 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 703 | clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 704 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO << |
| 705 | CD_CLKCTRL_CLKTRCTRL_SHIFT); |
| 706 | } |
| 707 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 708 | void do_enable_clocks(u32 const *clk_domains, |
| 709 | u32 const *clk_modules_hw_auto, |
| 710 | u32 const *clk_modules_explicit_en, |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 711 | u8 wait_for_enable) |
| 712 | { |
| 713 | u32 i, max = 100; |
| 714 | |
| 715 | /* Put the clock domains in SW_WKUP mode */ |
| 716 | for (i = 0; (i < max) && clk_domains[i]; i++) { |
| 717 | enable_clock_domain(clk_domains[i], |
| 718 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
| 719 | } |
| 720 | |
| 721 | /* Clock modules that need to be put in HW_AUTO */ |
| 722 | for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) { |
| 723 | enable_clock_module(clk_modules_hw_auto[i], |
| 724 | MODULE_CLKCTRL_MODULEMODE_HW_AUTO, |
| 725 | wait_for_enable); |
| 726 | }; |
| 727 | |
| 728 | /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ |
| 729 | for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { |
| 730 | enable_clock_module(clk_modules_explicit_en[i], |
| 731 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, |
| 732 | wait_for_enable); |
| 733 | }; |
| 734 | |
| 735 | /* Put the clock domains in HW_AUTO mode now */ |
| 736 | for (i = 0; (i < max) && clk_domains[i]; i++) { |
| 737 | enable_clock_domain(clk_domains[i], |
| 738 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
| 739 | } |
| 740 | } |
| 741 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 742 | void prcm_init(void) |
| 743 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 744 | switch (omap_hw_init_context()) { |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 745 | case OMAP_INIT_CONTEXT_SPL: |
| 746 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 747 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
Aneesh V | 25223a6 | 2011-07-21 09:29:29 -0400 | [diff] [blame] | 748 | enable_basic_clocks(); |
Lokesh Vutla | 3332b24 | 2013-05-30 03:19:30 +0000 | [diff] [blame] | 749 | timer_init(); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 750 | scale_vcores(*omap_vcores); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 751 | setup_dplls(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 752 | #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 753 | setup_non_essential_dplls(); |
| 754 | enable_non_essential_clocks(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 755 | #endif |
Lokesh Vutla | 0b1b60c | 2013-04-17 20:49:40 +0000 | [diff] [blame] | 756 | setup_warmreset_time(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 757 | break; |
| 758 | default: |
| 759 | break; |
| 760 | } |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 761 | |
| 762 | if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) |
| 763 | enable_basic_uboot_clocks(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 764 | } |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 765 | |
| 766 | void gpi2c_init(void) |
| 767 | { |
| 768 | static int gpi2c = 1; |
| 769 | |
| 770 | if (gpi2c) { |
| 771 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 772 | gpi2c = 0; |
| 773 | } |
| 774 | } |