Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Clock initialization for OMAP4 |
| 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Aneesh V <aneesh@ti.com> |
| 9 | * |
| 10 | * Based on previous work by: |
| 11 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 12 | * Rajendra Nayak <rnayak@ti.com> |
| 13 | * |
| 14 | * See file CREDITS for list of people who contributed to this |
| 15 | * project. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or |
| 18 | * modify it under the terms of the GNU General Public License as |
| 19 | * published by the Free Software Foundation; either version 2 of |
| 20 | * the License, or (at your option) any later version. |
| 21 | * |
| 22 | * This program is distributed in the hope that it will be useful, |
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 25 | * GNU General Public License for more details. |
| 26 | * |
| 27 | * You should have received a copy of the GNU General Public License |
| 28 | * along with this program; if not, write to the Free Software |
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 30 | * MA 02111-1307 USA |
| 31 | */ |
| 32 | #include <common.h> |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame^] | 33 | #include <i2c.h> |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 34 | #include <asm/omap_common.h> |
Sanjeev Premi | 3b690eb | 2011-09-08 10:48:39 -0400 | [diff] [blame] | 35 | #include <asm/gpio.h> |
Lokesh Vutla | af1d002 | 2013-05-30 02:54:32 +0000 | [diff] [blame] | 36 | #include <asm/arch/clock.h> |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 37 | #include <asm/arch/sys_proto.h> |
| 38 | #include <asm/utils.h> |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 39 | #include <asm/omap_gpio.h> |
Lokesh Vutla | 9ca8bfe | 2013-02-04 04:21:59 +0000 | [diff] [blame] | 40 | #include <asm/emif.h> |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 41 | |
| 42 | #ifndef CONFIG_SPL_BUILD |
| 43 | /* |
| 44 | * printing to console doesn't work unless |
| 45 | * this code is executed from SPL |
| 46 | */ |
| 47 | #define printf(fmt, args...) |
| 48 | #define puts(s) |
| 49 | #endif |
| 50 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 51 | const u32 sys_clk_array[8] = { |
| 52 | 12000000, /* 12 MHz */ |
| 53 | 13000000, /* 13 MHz */ |
| 54 | 16800000, /* 16.8 MHz */ |
| 55 | 19200000, /* 19.2 MHz */ |
| 56 | 26000000, /* 26 MHz */ |
| 57 | 27000000, /* 27 MHz */ |
| 58 | 38400000, /* 38.4 MHz */ |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 59 | 20000000, /* 20 MHz */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 60 | }; |
| 61 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 62 | static inline u32 __get_sys_clk_index(void) |
| 63 | { |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 64 | s8 ind; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 65 | /* |
| 66 | * For ES1 the ROM code calibration of sys clock is not reliable |
| 67 | * due to hw issue. So, use hard-coded value. If this value is not |
| 68 | * correct for any board over-ride this function in board file |
| 69 | * From ES2.0 onwards you will get this information from |
| 70 | * CM_SYS_CLKSEL |
| 71 | */ |
| 72 | if (omap_revision() == OMAP4430_ES1_0) |
| 73 | ind = OMAP_SYS_CLK_IND_38_4_MHZ; |
| 74 | else { |
| 75 | /* SYS_CLKSEL - 1 to match the dpll param array indices */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 76 | ind = (readl((*prcm)->cm_sys_clksel) & |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 77 | CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 78 | /* |
| 79 | * SYS_CLKSEL value for 20MHz is 0. This is introduced newly |
| 80 | * in DRA7XX socs. SYS_CLKSEL -1 will be greater than |
| 81 | * NUM_SYS_CLK. So considering the last 3 bits as the index |
| 82 | * for the dpll param array. |
| 83 | */ |
| 84 | ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 85 | } |
| 86 | return ind; |
| 87 | } |
| 88 | |
| 89 | u32 get_sys_clk_index(void) |
| 90 | __attribute__ ((weak, alias("__get_sys_clk_index"))); |
| 91 | |
| 92 | u32 get_sys_clk_freq(void) |
| 93 | { |
| 94 | u8 index = get_sys_clk_index(); |
| 95 | return sys_clk_array[index]; |
| 96 | } |
| 97 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 98 | void setup_post_dividers(u32 const base, const struct dpll_params *params) |
| 99 | { |
| 100 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 101 | |
| 102 | /* Setup post-dividers */ |
| 103 | if (params->m2 >= 0) |
| 104 | writel(params->m2, &dpll_regs->cm_div_m2_dpll); |
| 105 | if (params->m3 >= 0) |
| 106 | writel(params->m3, &dpll_regs->cm_div_m3_dpll); |
| 107 | if (params->m4_h11 >= 0) |
| 108 | writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll); |
| 109 | if (params->m5_h12 >= 0) |
| 110 | writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll); |
| 111 | if (params->m6_h13 >= 0) |
| 112 | writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); |
| 113 | if (params->m7_h14 >= 0) |
| 114 | writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); |
SRICHARAN R | 47abc3d | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 115 | if (params->h21 >= 0) |
| 116 | writel(params->h21, &dpll_regs->cm_div_h21_dpll); |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 117 | if (params->h22 >= 0) |
| 118 | writel(params->h22, &dpll_regs->cm_div_h22_dpll); |
| 119 | if (params->h23 >= 0) |
| 120 | writel(params->h23, &dpll_regs->cm_div_h23_dpll); |
SRICHARAN R | 47abc3d | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 121 | if (params->h24 >= 0) |
| 122 | writel(params->h24, &dpll_regs->cm_div_h24_dpll); |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 123 | } |
| 124 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 125 | static inline void do_bypass_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 126 | { |
| 127 | struct dpll_regs *dpll_regs = (struct dpll_regs *)base; |
| 128 | |
| 129 | clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
| 130 | CM_CLKMODE_DPLL_DPLL_EN_MASK, |
| 131 | DPLL_EN_FAST_RELOCK_BYPASS << |
| 132 | CM_CLKMODE_DPLL_EN_SHIFT); |
| 133 | } |
| 134 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 135 | static inline void wait_for_bypass(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 136 | { |
| 137 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 138 | |
| 139 | if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, |
| 140 | LDELAY)) { |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 141 | printf("Bypassing DPLL failed %x\n", base); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 142 | } |
| 143 | } |
| 144 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 145 | static inline void do_lock_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 146 | { |
| 147 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 148 | |
| 149 | clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
| 150 | CM_CLKMODE_DPLL_DPLL_EN_MASK, |
| 151 | DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); |
| 152 | } |
| 153 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 154 | static inline void wait_for_lock(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 155 | { |
| 156 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 157 | |
| 158 | if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, |
| 159 | &dpll_regs->cm_idlest_dpll, LDELAY)) { |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 160 | printf("DPLL locking failed for %x\n", base); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 161 | hang(); |
| 162 | } |
| 163 | } |
| 164 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 165 | inline u32 check_for_lock(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 166 | { |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 167 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 168 | u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; |
| 169 | |
| 170 | return lock; |
| 171 | } |
| 172 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 173 | const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) |
| 174 | { |
| 175 | u32 sysclk_ind = get_sys_clk_index(); |
| 176 | return &dpll_data->mpu[sysclk_ind]; |
| 177 | } |
| 178 | |
| 179 | const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) |
| 180 | { |
| 181 | u32 sysclk_ind = get_sys_clk_index(); |
| 182 | return &dpll_data->core[sysclk_ind]; |
| 183 | } |
| 184 | |
| 185 | const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) |
| 186 | { |
| 187 | u32 sysclk_ind = get_sys_clk_index(); |
| 188 | return &dpll_data->per[sysclk_ind]; |
| 189 | } |
| 190 | |
| 191 | const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) |
| 192 | { |
| 193 | u32 sysclk_ind = get_sys_clk_index(); |
| 194 | return &dpll_data->iva[sysclk_ind]; |
| 195 | } |
| 196 | |
| 197 | const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) |
| 198 | { |
| 199 | u32 sysclk_ind = get_sys_clk_index(); |
| 200 | return &dpll_data->usb[sysclk_ind]; |
| 201 | } |
| 202 | |
| 203 | const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) |
| 204 | { |
| 205 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 206 | u32 sysclk_ind = get_sys_clk_index(); |
| 207 | return &dpll_data->abe[sysclk_ind]; |
| 208 | #else |
| 209 | return dpll_data->abe; |
| 210 | #endif |
| 211 | } |
| 212 | |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 213 | static const struct dpll_params *get_ddr_dpll_params |
| 214 | (struct dplls const *dpll_data) |
| 215 | { |
| 216 | u32 sysclk_ind = get_sys_clk_index(); |
| 217 | |
| 218 | if (!dpll_data->ddr) |
| 219 | return NULL; |
| 220 | return &dpll_data->ddr[sysclk_ind]; |
| 221 | } |
| 222 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 223 | static void do_setup_dpll(u32 const base, const struct dpll_params *params, |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 224 | u8 lock, char *dpll) |
| 225 | { |
| 226 | u32 temp, M, N; |
| 227 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 228 | |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 229 | if (!params) |
| 230 | return; |
| 231 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 232 | temp = readl(&dpll_regs->cm_clksel_dpll); |
| 233 | |
| 234 | if (check_for_lock(base)) { |
| 235 | /* |
| 236 | * The Dpll has already been locked by rom code using CH. |
| 237 | * Check if M,N are matching with Ideal nominal opp values. |
| 238 | * If matches, skip the rest otherwise relock. |
| 239 | */ |
| 240 | M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT; |
| 241 | N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT; |
| 242 | if ((M != (params->m)) || (N != (params->n))) { |
| 243 | debug("\n %s Dpll locked, but not for ideal M = %d," |
| 244 | "N = %d values, current values are M = %d," |
| 245 | "N= %d" , dpll, params->m, params->n, |
| 246 | M, N); |
| 247 | } else { |
| 248 | /* Dpll locked with ideal values for nominal opps. */ |
| 249 | debug("\n %s Dpll already locked with ideal" |
| 250 | "nominal opp values", dpll); |
| 251 | goto setup_post_dividers; |
| 252 | } |
| 253 | } |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 254 | |
| 255 | bypass_dpll(base); |
| 256 | |
| 257 | /* Set M & N */ |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 258 | temp &= ~CM_CLKSEL_DPLL_M_MASK; |
| 259 | temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; |
| 260 | |
| 261 | temp &= ~CM_CLKSEL_DPLL_N_MASK; |
| 262 | temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; |
| 263 | |
| 264 | writel(temp, &dpll_regs->cm_clksel_dpll); |
| 265 | |
| 266 | /* Lock */ |
| 267 | if (lock) |
| 268 | do_lock_dpll(base); |
| 269 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 270 | setup_post_dividers: |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 271 | setup_post_dividers(base, params); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 272 | |
| 273 | /* Wait till the DPLL locks */ |
| 274 | if (lock) |
| 275 | wait_for_lock(base); |
| 276 | } |
| 277 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 278 | u32 omap_ddr_clk(void) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 279 | { |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 280 | u32 ddr_clk, sys_clk_khz, omap_rev, divider; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 281 | const struct dpll_params *core_dpll_params; |
| 282 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 283 | omap_rev = omap_revision(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 284 | sys_clk_khz = get_sys_clk_freq() / 1000; |
| 285 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 286 | core_dpll_params = get_core_dpll_params(*dplls_data); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 287 | |
| 288 | debug("sys_clk %d\n ", sys_clk_khz * 1000); |
| 289 | |
| 290 | /* Find Core DPLL locked frequency first */ |
| 291 | ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / |
| 292 | (core_dpll_params->n + 1); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 293 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 294 | if (omap_rev < OMAP5430_ES1_0) { |
| 295 | /* |
| 296 | * DDR frequency is PHY_ROOT_CLK/2 |
| 297 | * PHY_ROOT_CLK = Fdpll/2/M2 |
| 298 | */ |
| 299 | divider = 4; |
| 300 | } else { |
| 301 | /* |
| 302 | * DDR frequency is PHY_ROOT_CLK |
| 303 | * PHY_ROOT_CLK = Fdpll/2/M2 |
| 304 | */ |
| 305 | divider = 2; |
| 306 | } |
| 307 | |
| 308 | ddr_clk = ddr_clk / divider / core_dpll_params->m2; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 309 | ddr_clk *= 1000; /* convert to Hz */ |
| 310 | debug("ddr_clk %d\n ", ddr_clk); |
| 311 | |
| 312 | return ddr_clk; |
| 313 | } |
| 314 | |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 315 | /* |
| 316 | * Lock MPU dpll |
| 317 | * |
| 318 | * Resulting MPU frequencies: |
| 319 | * 4430 ES1.0 : 600 MHz |
| 320 | * 4430 ES2.x : 792 MHz (OPP Turbo) |
| 321 | * 4460 : 920 MHz (OPP Turbo) - DCC disabled |
| 322 | */ |
| 323 | void configure_mpu_dpll(void) |
| 324 | { |
| 325 | const struct dpll_params *params; |
| 326 | struct dpll_regs *mpu_dpll_regs; |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 327 | u32 omap_rev; |
| 328 | omap_rev = omap_revision(); |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 329 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 330 | /* |
| 331 | * DCC and clock divider settings for 4460. |
| 332 | * DCC is required, if more than a certain frequency is required. |
| 333 | * For, 4460 > 1GHZ. |
| 334 | * 5430 > 1.4GHZ. |
| 335 | */ |
| 336 | if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 337 | mpu_dpll_regs = |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 338 | (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); |
| 339 | bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); |
| 340 | clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 341 | MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 342 | setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 343 | MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); |
| 344 | clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, |
| 345 | CM_CLKSEL_DCC_EN_MASK); |
| 346 | } |
| 347 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 348 | params = get_mpu_dpll_params(*dplls_data); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 349 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 350 | do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 351 | debug("MPU DPLL locked\n"); |
| 352 | } |
| 353 | |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 354 | #ifdef CONFIG_USB_EHCI_OMAP |
| 355 | static void setup_usb_dpll(void) |
| 356 | { |
| 357 | const struct dpll_params *params; |
| 358 | u32 sys_clk_khz, sd_div, num, den; |
| 359 | |
| 360 | sys_clk_khz = get_sys_clk_freq() / 1000; |
| 361 | /* |
| 362 | * USB: |
| 363 | * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction |
| 364 | * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) |
| 365 | * - where CLKINP is sys_clk in MHz |
| 366 | * Use CLKINP in KHz and adjust the denominator accordingly so |
| 367 | * that we have enough accuracy and at the same time no overflow |
| 368 | */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 369 | params = get_usb_dpll_params(*dplls_data); |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 370 | num = params->m * sys_clk_khz; |
| 371 | den = (params->n + 1) * 250 * 1000; |
| 372 | num += den - 1; |
| 373 | sd_div = num / den; |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 374 | clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 375 | CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, |
| 376 | sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); |
| 377 | |
| 378 | /* Now setup the dpll with the regular function */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 379 | do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 380 | } |
| 381 | #endif |
| 382 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 383 | static void setup_dplls(void) |
| 384 | { |
Anatolij Gustschin | 164a750 | 2011-12-03 06:46:14 +0000 | [diff] [blame] | 385 | u32 temp; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 386 | const struct dpll_params *params; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 387 | |
Anatolij Gustschin | 164a750 | 2011-12-03 06:46:14 +0000 | [diff] [blame] | 388 | debug("setup_dplls\n"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 389 | |
| 390 | /* CORE dpll */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 391 | params = get_core_dpll_params(*dplls_data); /* default - safest */ |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 392 | /* |
| 393 | * Do not lock the core DPLL now. Just set it up. |
| 394 | * Core DPLL will be locked after setting up EMIF |
| 395 | * using the FREQ_UPDATE method(freq_update_core()) |
| 396 | */ |
Lokesh Vutla | 9ca8bfe | 2013-02-04 04:21:59 +0000 | [diff] [blame] | 397 | if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 398 | do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, |
Lokesh Vutla | 753bae8 | 2012-05-22 00:03:26 +0000 | [diff] [blame] | 399 | DPLL_NO_LOCK, "core"); |
| 400 | else |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 401 | do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, |
Lokesh Vutla | 753bae8 | 2012-05-22 00:03:26 +0000 | [diff] [blame] | 402 | DPLL_LOCK, "core"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 403 | /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ |
| 404 | temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | |
| 405 | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | |
| 406 | (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 407 | writel(temp, (*prcm)->cm_clksel_core); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 408 | debug("Core DPLL configured\n"); |
| 409 | |
| 410 | /* lock PER dpll */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 411 | params = get_per_dpll_params(*dplls_data); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 412 | do_setup_dpll((*prcm)->cm_clkmode_dpll_per, |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 413 | params, DPLL_LOCK, "per"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 414 | debug("PER DPLL locked\n"); |
| 415 | |
| 416 | /* MPU dpll */ |
Aneesh V | b4dc644 | 2011-07-21 09:29:36 -0400 | [diff] [blame] | 417 | configure_mpu_dpll(); |
Govindraj.R | 860004c | 2012-02-06 03:55:36 +0000 | [diff] [blame] | 418 | |
| 419 | #ifdef CONFIG_USB_EHCI_OMAP |
| 420 | setup_usb_dpll(); |
| 421 | #endif |
Lokesh Vutla | ea8eff1 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 422 | params = get_ddr_dpll_params(*dplls_data); |
| 423 | do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, |
| 424 | params, DPLL_LOCK, "ddr"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 425 | } |
| 426 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 427 | #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 428 | static void setup_non_essential_dplls(void) |
| 429 | { |
Anatolij Gustschin | 27ac87d | 2012-03-27 23:13:43 +0000 | [diff] [blame] | 430 | u32 abe_ref_clk; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 431 | const struct dpll_params *params; |
| 432 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 433 | /* IVA */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 434 | clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 435 | CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); |
| 436 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 437 | params = get_iva_dpll_params(*dplls_data); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 438 | do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 439 | |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 440 | /* Configure ABE dpll */ |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 441 | params = get_abe_dpll_params(*dplls_data); |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 442 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 443 | abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; |
| 444 | #else |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 445 | abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; |
| 446 | /* |
| 447 | * We need to enable some additional options to achieve |
| 448 | * 196.608MHz from 32768 Hz |
| 449 | */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 450 | setbits_le32((*prcm)->cm_clkmode_dpll_abe, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 451 | CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| |
| 452 | CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| |
| 453 | CM_CLKMODE_DPLL_LPMODE_EN_MASK| |
| 454 | CM_CLKMODE_DPLL_REGM4XEN_MASK); |
| 455 | /* Spend 4 REFCLK cycles at each stage */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 456 | clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 457 | CM_CLKMODE_DPLL_RAMP_RATE_MASK, |
| 458 | 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); |
| 459 | #endif |
| 460 | |
| 461 | /* Select the right reference clk */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 462 | clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 463 | CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, |
| 464 | abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); |
| 465 | /* Lock the dpll */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 466 | do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 467 | } |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 468 | #endif |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 469 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 470 | u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 471 | { |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 472 | u32 offset_code; |
Nishanth Menon | 3acb553 | 2012-03-01 14:17:38 +0000 | [diff] [blame] | 473 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 474 | volt_offset -= pmic->base_offset; |
Nishanth Menon | 3acb553 | 2012-03-01 14:17:38 +0000 | [diff] [blame] | 475 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 476 | offset_code = (volt_offset + pmic->step - 1) / pmic->step; |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 477 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 478 | /* |
| 479 | * Offset codes 1-6 all give the base voltage in Palmas |
| 480 | * Offset code 0 switches OFF the SMPS |
| 481 | */ |
| 482 | return offset_code + pmic->start_code; |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 483 | } |
| 484 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 485 | void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 486 | { |
Nishanth Menon | a78274b | 2012-03-01 14:17:37 +0000 | [diff] [blame] | 487 | u32 offset_code; |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 488 | u32 offset = volt_mv; |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 489 | int ret = 0; |
| 490 | |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame^] | 491 | if (!volt_mv) |
| 492 | return; |
| 493 | |
Lokesh Vutla | 4ca94d8 | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 494 | pmic->pmic_bus_init(); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 495 | /* See if we can first get the GPIO if needed */ |
| 496 | if (pmic->gpio_en) |
| 497 | ret = gpio_request(pmic->gpio, "PMIC_GPIO"); |
| 498 | |
| 499 | if (ret < 0) { |
| 500 | printf("%s: gpio %d request failed %d\n", __func__, |
| 501 | pmic->gpio, ret); |
| 502 | return; |
| 503 | } |
| 504 | |
| 505 | /* Pull the GPIO low to select SET0 register, while we program SET1 */ |
| 506 | if (pmic->gpio_en) |
| 507 | gpio_direction_output(pmic->gpio, 0); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 508 | |
| 509 | /* convert to uV for better accuracy in the calculations */ |
| 510 | offset *= 1000; |
| 511 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 512 | offset_code = get_offset_code(offset, pmic); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 513 | |
| 514 | debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, |
| 515 | offset_code); |
SRICHARAN R | 8de17f4 | 2012-03-12 02:25:38 +0000 | [diff] [blame] | 516 | |
Lokesh Vutla | 4ca94d8 | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 517 | if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 518 | printf("Scaling voltage failed for 0x%x\n", vcore_reg); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 519 | |
| 520 | if (pmic->gpio_en) |
| 521 | gpio_direction_output(pmic->gpio, 1); |
| 522 | } |
| 523 | |
| 524 | /* |
| 525 | * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
| 526 | * We set the maximum voltages allowed here because Smart-Reflex is not |
| 527 | * enabled in bootloader. Voltage initialization in the kernel will set |
| 528 | * these to the nominal values after enabling Smart-Reflex |
| 529 | */ |
| 530 | void scale_vcores(struct vcores_data const *vcores) |
| 531 | { |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 532 | do_scale_vcore(vcores->core.addr, vcores->core.value, |
| 533 | vcores->core.pmic); |
| 534 | |
| 535 | do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, |
| 536 | vcores->mpu.pmic); |
| 537 | |
Andrii Tseglytskyi | e69c585 | 2013-05-20 22:42:09 +0000 | [diff] [blame] | 538 | /* Configure MPU ABB LDO after scale */ |
| 539 | abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2, |
| 540 | (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, |
| 541 | (*prcm)->prm_abbldo_mpu_setup, |
| 542 | (*prcm)->prm_abbldo_mpu_ctrl, |
| 543 | (*prcm)->prm_irqstatus_mpu_2, |
| 544 | OMAP_ABB_MPU_TXDONE_MASK, |
| 545 | OMAP_ABB_FAST_OPP); |
| 546 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 547 | do_scale_vcore(vcores->mm.addr, vcores->mm.value, |
| 548 | vcores->mm.pmic); |
| 549 | |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame^] | 550 | do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, |
| 551 | vcores->gpu.pmic); |
| 552 | |
| 553 | do_scale_vcore(vcores->eve.addr, vcores->eve.value, |
| 554 | vcores->eve.pmic); |
| 555 | |
| 556 | do_scale_vcore(vcores->iva.addr, vcores->iva.value, |
| 557 | vcores->iva.pmic); |
| 558 | |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 559 | if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { |
| 560 | /* Configure LDO SRAM "magic" bits */ |
| 561 | writel(2, (*prcm)->prm_sldo_core_setup); |
| 562 | writel(2, (*prcm)->prm_sldo_mpu_setup); |
| 563 | writel(2, (*prcm)->prm_sldo_mm_setup); |
| 564 | } |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 565 | } |
| 566 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 567 | static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 568 | { |
| 569 | clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, |
| 570 | enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 571 | debug("Enable clock domain - %x\n", clkctrl_reg); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 572 | } |
| 573 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 574 | static inline void wait_for_clk_enable(u32 clkctrl_addr) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 575 | { |
| 576 | u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; |
| 577 | u32 bound = LDELAY; |
| 578 | |
| 579 | while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || |
| 580 | (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { |
| 581 | |
| 582 | clkctrl = readl(clkctrl_addr); |
| 583 | idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> |
| 584 | MODULE_CLKCTRL_IDLEST_SHIFT; |
| 585 | if (--bound == 0) { |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 586 | printf("Clock enable failed for 0x%x idlest 0x%x\n", |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 587 | clkctrl_addr, clkctrl); |
| 588 | return; |
| 589 | } |
| 590 | } |
| 591 | } |
| 592 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 593 | static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 594 | u32 wait_for_enable) |
| 595 | { |
| 596 | clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, |
| 597 | enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 598 | debug("Enable clock module - %x\n", clkctrl_addr); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 599 | if (wait_for_enable) |
| 600 | wait_for_clk_enable(clkctrl_addr); |
| 601 | } |
| 602 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 603 | void freq_update_core(void) |
| 604 | { |
| 605 | u32 freq_config1 = 0; |
| 606 | const struct dpll_params *core_dpll_params; |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 607 | u32 omap_rev = omap_revision(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 608 | |
SRICHARAN R | ee9447b | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 609 | core_dpll_params = get_core_dpll_params(*dplls_data); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 610 | /* Put EMIF clock domain in sw wakeup mode */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 611 | enable_clock_domain((*prcm)->cm_memif_clkstctrl, |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 612 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 613 | wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); |
| 614 | wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 615 | |
| 616 | freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | |
| 617 | SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; |
| 618 | |
| 619 | freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & |
| 620 | SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; |
| 621 | |
| 622 | freq_config1 |= (core_dpll_params->m2 << |
| 623 | SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & |
| 624 | SHADOW_FREQ_CONFIG1_M2_DIV_MASK; |
| 625 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 626 | writel(freq_config1, (*prcm)->cm_shadow_freq_config1); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 627 | if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 628 | (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 629 | puts("FREQ UPDATE procedure failed!!"); |
| 630 | hang(); |
| 631 | } |
| 632 | |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 633 | /* |
| 634 | * Putting EMIF in HW_AUTO is seen to be causing issues with |
Lubomir Popov | a8f408a | 2013-04-04 05:51:45 +0000 | [diff] [blame] | 635 | * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 636 | * in OMAP5430 ES1.0 silicon |
| 637 | */ |
| 638 | if (omap_rev != OMAP5430_ES1_0) { |
| 639 | /* Put EMIF clock domain back in hw auto mode */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 640 | enable_clock_domain((*prcm)->cm_memif_clkstctrl, |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 641 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 642 | wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); |
| 643 | wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); |
SRICHARAN R | f401073 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 644 | } |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 645 | } |
| 646 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 647 | void bypass_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 648 | { |
| 649 | do_bypass_dpll(base); |
| 650 | wait_for_bypass(base); |
| 651 | } |
| 652 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 653 | void lock_dpll(u32 const base) |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 654 | { |
| 655 | do_lock_dpll(base); |
| 656 | wait_for_lock(base); |
| 657 | } |
| 658 | |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 659 | void setup_clocks_for_console(void) |
| 660 | { |
| 661 | /* Do not add any spl_debug prints in this function */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 662 | clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 663 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP << |
| 664 | CD_CLKCTRL_CLKTRCTRL_SHIFT); |
| 665 | |
| 666 | /* Enable all UARTs - console will be on one of them */ |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 667 | clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 668 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 669 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 670 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 671 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 672 | clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 673 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 674 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 675 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 676 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 677 | clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 678 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 679 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 680 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 681 | |
Lubomir Popov | a8f408a | 2013-04-04 05:51:45 +0000 | [diff] [blame] | 682 | clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 683 | MODULE_CLKCTRL_MODULEMODE_MASK, |
| 684 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << |
| 685 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 686 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 687 | clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 688 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO << |
| 689 | CD_CLKCTRL_CLKTRCTRL_SHIFT); |
| 690 | } |
| 691 | |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 692 | void do_enable_clocks(u32 const *clk_domains, |
| 693 | u32 const *clk_modules_hw_auto, |
| 694 | u32 const *clk_modules_explicit_en, |
Sricharan | 2e5ba48 | 2011-11-15 09:49:58 -0500 | [diff] [blame] | 695 | u8 wait_for_enable) |
| 696 | { |
| 697 | u32 i, max = 100; |
| 698 | |
| 699 | /* Put the clock domains in SW_WKUP mode */ |
| 700 | for (i = 0; (i < max) && clk_domains[i]; i++) { |
| 701 | enable_clock_domain(clk_domains[i], |
| 702 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
| 703 | } |
| 704 | |
| 705 | /* Clock modules that need to be put in HW_AUTO */ |
| 706 | for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) { |
| 707 | enable_clock_module(clk_modules_hw_auto[i], |
| 708 | MODULE_CLKCTRL_MODULEMODE_HW_AUTO, |
| 709 | wait_for_enable); |
| 710 | }; |
| 711 | |
| 712 | /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ |
| 713 | for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { |
| 714 | enable_clock_module(clk_modules_explicit_en[i], |
| 715 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, |
| 716 | wait_for_enable); |
| 717 | }; |
| 718 | |
| 719 | /* Put the clock domains in HW_AUTO mode now */ |
| 720 | for (i = 0; (i < max) && clk_domains[i]; i++) { |
| 721 | enable_clock_domain(clk_domains[i], |
| 722 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
| 723 | } |
| 724 | } |
| 725 | |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 726 | void prcm_init(void) |
| 727 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 728 | switch (omap_hw_init_context()) { |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 729 | case OMAP_INIT_CONTEXT_SPL: |
| 730 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 731 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
Aneesh V | 25223a6 | 2011-07-21 09:29:29 -0400 | [diff] [blame] | 732 | enable_basic_clocks(); |
SRICHARAN R | 3fcdd4a | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 733 | scale_vcores(*omap_vcores); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 734 | setup_dplls(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 735 | #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 736 | setup_non_essential_dplls(); |
| 737 | enable_non_essential_clocks(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 738 | #endif |
Lokesh Vutla | 0b1b60c | 2013-04-17 20:49:40 +0000 | [diff] [blame] | 739 | setup_warmreset_time(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 740 | break; |
| 741 | default: |
| 742 | break; |
| 743 | } |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 744 | |
| 745 | if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) |
| 746 | enable_basic_uboot_clocks(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 747 | } |
Lokesh Vutla | 63fc0c7 | 2013-05-30 03:19:29 +0000 | [diff] [blame^] | 748 | |
| 749 | void gpi2c_init(void) |
| 750 | { |
| 751 | static int gpi2c = 1; |
| 752 | |
| 753 | if (gpi2c) { |
| 754 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 755 | gpi2c = 0; |
| 756 | } |
| 757 | } |