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Haavard Skinnemoen64ff2352007-10-29 13:02:54 +01001/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1003 CPU daughterboard
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000027#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020028
Andreas Bießmann4de58bc2011-04-18 04:12:38 +000029#define CONFIG_AVR32
30#define CONFIG_AT32AP
31#define CONFIG_AT32AP7002
32#define CONFIG_ATSTK1004
33#define CONFIG_ATSTK1000
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010034
Andreas Bießmann4de58bc2011-04-18 04:12:38 +000035#define CONFIG_ATSTK1000_EXT_FLASH
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010036
37/*
38 * Timer clock frequency. We're using the CPU-internal COUNT register
39 * for this, so this is equivalent to the CPU core clock frequency
40 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_HZ 1000
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010042
43/*
44 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
45 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
46 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010048 */
Andreas Bießmann4de58bc2011-04-18 04:12:38 +000049#define CONFIG_PLL
50#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_OSC0_HZ 20000000
52#define CONFIG_SYS_PLL0_DIV 1
53#define CONFIG_SYS_PLL0_MUL 7
54#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010055/*
56 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010058 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_CLKDIV_CPU 0
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010060/*
61 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010063 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_CLKDIV_HSB 1
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010065/*
66 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010068 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_CLKDIV_PBA 2
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010070/*
71 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010073 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010075
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070076/* Reserve VM regions for SDRAM and NOR flash */
77#define CONFIG_SYS_NR_VM_REGIONS 2
78
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010079/*
80 * The PLLOPT register controls the PLL like this:
81 * icp = PLLOPT<2>
82 * ivco = PLLOPT<1:0>
83 *
84 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010087
Andreas Bießmannf4278b72010-11-04 23:15:31 +000088#define CONFIG_USART_BASE ATMEL_BASE_USART1
89#define CONFIG_USART_ID 1
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010090
91/* User serviceable stuff */
Andreas Bießmann4de58bc2011-04-18 04:12:38 +000092#define CONFIG_DOS_PARTITION
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010093
Andreas Bießmann4de58bc2011-04-18 04:12:38 +000094#define CONFIG_CMDLINE_TAG
95#define CONFIG_SETUP_MEMORY_TAGS
96#define CONFIG_INITRD_TAG
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010097
98#define CONFIG_STACKSIZE (2048)
99
100#define CONFIG_BAUDRATE 115200
101#define CONFIG_BOOTARGS \
102 "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
103
104#define CONFIG_BOOTCOMMAND \
105 "mmcinit; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
106
107/*
108 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
109 * data on the serial line may interrupt the boot sequence.
110 */
111#define CONFIG_BOOTDELAY 1
Andreas Bießmann4de58bc2011-04-18 04:12:38 +0000112#define CONFIG_AUTOBOOT
113#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200114#define CONFIG_AUTOBOOT_PROMPT \
115 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100116#define CONFIG_AUTOBOOT_DELAY_STR "d"
117#define CONFIG_AUTOBOOT_STOP_STR " "
118
119/*
120 * Command line configuration.
121 */
122#include <config_cmd_default.h>
123
124#define CONFIG_CMD_ASKENV
125#define CONFIG_CMD_EXT2
126#define CONFIG_CMD_FAT
127#define CONFIG_CMD_JFFS2
128#define CONFIG_CMD_MMC
129
130#undef CONFIG_CMD_FPGA
131#undef CONFIG_CMD_NET
132#undef CONFIG_CMD_NFS
133#undef CONFIG_CMD_SETGETDCR
134#undef CONFIG_CMD_XIMG
135
Andreas Bießmann4de58bc2011-04-18 04:12:38 +0000136#define CONFIG_ATMEL_USART
137#define CONFIG_PORTMUX_PIO
138#define CONFIG_SYS_HSDRAMC
139#define CONFIG_MMC
140#define CONFIG_ATMEL_MCI
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_DCACHE_LINESZ 32
143#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100144
145#define CONFIG_NR_DRAM_BANKS 1
146
147/* External flash on STK1000 */
148#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200150#define CONFIG_FLASH_CFI_DRIVER 1
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100151#endif
152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_BASE 0x00000000
154#define CONFIG_SYS_FLASH_SIZE 0x800000
155#define CONFIG_SYS_MAX_FLASH_BANKS 1
156#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann47293c12011-04-18 04:12:44 +0000159#define CONFIG_SYS_TEXT_BASE 0x00000000
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
162#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
163#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100164
Andreas Bießmann4de58bc2011-04-18 04:12:38 +0000165#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200166#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MALLOC_LEN (256*1024)
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100172
Haavard Skinnemoenb2e1d5b2007-11-22 17:04:13 +0100173/* Allow 2MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
175#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100176
177/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_PROMPT "U-Boot> "
179#define CONFIG_SYS_CBSIZE 256
180#define CONFIG_SYS_MAXARGS 16
181#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmann4de58bc2011-04-18 04:12:38 +0000182#define CONFIG_SYS_LONGHELP
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
185#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
186#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100187
188#endif /* __CONFIG_H */