blob: fc9585e84d2d21eeca8d0e23ca88d6a672e35529 [file] [log] [blame]
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +01001/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1003 CPU daughterboard
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020027#include <asm/arch/memory-map.h>
28
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +010029#define CONFIG_AVR32 1
30#define CONFIG_AT32AP 1
31#define CONFIG_AT32AP7002 1
32#define CONFIG_ATSTK1004 1
33#define CONFIG_ATSTK1000 1
34
35#define CONFIG_ATSTK1000_EXT_FLASH 1
36
37/*
38 * Timer clock frequency. We're using the CPU-internal COUNT register
39 * for this, so this is equivalent to the CPU core clock frequency
40 */
41#define CFG_HZ 1000
42
43/*
44 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
45 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
46 * PLL frequency.
47 * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz
48 */
49#define CONFIG_PLL 1
50#define CFG_POWER_MANAGER 1
51#define CFG_OSC0_HZ 20000000
52#define CFG_PLL0_DIV 1
53#define CFG_PLL0_MUL 7
54#define CFG_PLL0_SUPPRESS_CYCLES 16
55/*
56 * Set the CPU running at:
57 * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz
58 */
59#define CFG_CLKDIV_CPU 0
60/*
61 * Set the HSB running at:
62 * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz
63 */
64#define CFG_CLKDIV_HSB 1
65/*
66 * Set the PBA running at:
67 * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz
68 */
69#define CFG_CLKDIV_PBA 2
70/*
71 * Set the PBB running at:
72 * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz
73 */
74#define CFG_CLKDIV_PBB 1
75
76/*
77 * The PLLOPT register controls the PLL like this:
78 * icp = PLLOPT<2>
79 * ivco = PLLOPT<1:0>
80 *
81 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
82 */
83#define CFG_PLL0_OPT 0x04
84
85#undef CONFIG_USART0
86#define CONFIG_USART1 1
87#undef CONFIG_USART2
88#undef CONFIG_USART3
89
90/* User serviceable stuff */
91#define CONFIG_DOS_PARTITION 1
92
93#define CONFIG_CMDLINE_TAG 1
94#define CONFIG_SETUP_MEMORY_TAGS 1
95#define CONFIG_INITRD_TAG 1
96
97#define CONFIG_STACKSIZE (2048)
98
99#define CONFIG_BAUDRATE 115200
100#define CONFIG_BOOTARGS \
101 "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
102
103#define CONFIG_BOOTCOMMAND \
104 "mmcinit; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
105
106/*
107 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
108 * data on the serial line may interrupt the boot sequence.
109 */
110#define CONFIG_BOOTDELAY 1
111#define CONFIG_AUTOBOOT 1
112#define CONFIG_AUTOBOOT_KEYED 1
113#define CONFIG_AUTOBOOT_PROMPT \
114 "Press SPACE to abort autoboot in %d seconds\n"
115#define CONFIG_AUTOBOOT_DELAY_STR "d"
116#define CONFIG_AUTOBOOT_STOP_STR " "
117
118/*
119 * Command line configuration.
120 */
121#include <config_cmd_default.h>
122
123#define CONFIG_CMD_ASKENV
124#define CONFIG_CMD_EXT2
125#define CONFIG_CMD_FAT
126#define CONFIG_CMD_JFFS2
127#define CONFIG_CMD_MMC
128
129#undef CONFIG_CMD_FPGA
130#undef CONFIG_CMD_NET
131#undef CONFIG_CMD_NFS
132#undef CONFIG_CMD_SETGETDCR
133#undef CONFIG_CMD_XIMG
134
135#define CONFIG_ATMEL_USART 1
136#define CONFIG_PIO2 1
137#define CFG_HSDRAMC 1
138#define CONFIG_MMC 1
139
140#define CFG_DCACHE_LINESZ 32
141#define CFG_ICACHE_LINESZ 32
142
143#define CONFIG_NR_DRAM_BANKS 1
144
145/* External flash on STK1000 */
146#if 0
147#define CFG_FLASH_CFI 1
148#define CFG_FLASH_CFI_DRIVER 1
149#endif
150
151#define CFG_FLASH_BASE 0x00000000
152#define CFG_FLASH_SIZE 0x800000
153#define CFG_MAX_FLASH_BANKS 1
154#define CFG_MAX_FLASH_SECT 135
155
156#define CFG_MONITOR_BASE CFG_FLASH_BASE
157
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200158#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
159#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
160#define CFG_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100161
162#define CFG_ENV_IS_IN_FLASH 1
163#define CFG_ENV_SIZE 65536
164#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
165
166#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
167
168#define CFG_MALLOC_LEN (256*1024)
169
Haavard Skinnemoenb2e1d5b2007-11-22 17:04:13 +0100170/* Allow 2MB for the kernel run-time image */
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200171#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100172#define CFG_BOOTPARAMS_LEN (16 * 1024)
173
174/* Other configuration settings that shouldn't have to change all that often */
David Brownell55ac7a72008-02-22 12:54:39 -0800175#define CFG_PROMPT "U-Boot> "
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100176#define CFG_CBSIZE 256
177#define CFG_MAXARGS 16
178#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
179#define CFG_LONGHELP 1
180
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200181#define CFG_MEMTEST_START EBI_SDRAM_BASE
Haavard Skinnemoen64ff2352007-10-29 13:02:54 +0100182#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
183#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
184
185#endif /* __CONFIG_H */